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 File: make, Node: Copying, Next: Bugs, Prev: Top, Up: Top Copying Conditions ****************** (Clarified 11 Feb 1988) The license agreements of most software companies keep you at the mercy of those companies. By contrast, our general public license is intended to give everyone the right to share GNU Make. To make sure that you get the rights we want you to have, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. Hence this license agreement. Specifically, we want to make sure that you have the right to give away copies of GNU Make, that you receive source code or else can get it if you want it, that you can change GNU Make or use pieces of it in new free programs, and that you know you can do these things. To make sure that everyone has such rights, we have to forbid you to deprive anyone else of these rights. For example, if you distribute copies of GNU Make, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must tell them their rights. Also, for our own protection, we must make certain that everyone finds out that there is no warranty for GNU Make. If GNU Make is modified by someone else and passed on, we want its recipients to know that what they have is not what we distributed, so that any problems introduced by others will not reflect on our reputation. Therefore we (Richard Stallman and the Free Software Foundation, Inc.) make the following terms which say what you must do to be allowed to distribute or change GNU Make. Copying Policies ================ 1. You may copy and distribute verbatim copies of GNU Make source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy a valid copyright notice ``Copyright (C) 1988 Free Software Foundation, Inc.'' (or with whatever year is appropriate), and include following the copyright notice a verbatim copy of the above disclaimer of warranty and of this License. You may charge a distribution fee for the physical act of transferring a copy. 2. You may modify your copy or copies of GNU Make or any portion of it, and copy and distribute such modifications under the terms of Paragraph 1 above, provided that you also do the following: * cause the modified files to carry prominent notices stating that you changed the files and the date of any change; and * cause the whole of any work that you distribute or publish, that in whole or in part contains or is a derivative of Bison or any part thereof, to be licensed at no charge to all third parties on terms identical to those contained in this License Agreement (except that you may choose to grant more extensive warranty protection to some or all third parties, at your option). * You may charge a distribution fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. Mere aggregation of another unrelated program with this program (or its derivative) on a volume of a storage or distribution medium does not bring the other program under the scope of these terms. 3. You may copy and distribute GNU Make (or a portion or derivative of it, under Paragraph 2) in object code or executable form under the terms of Paragraphs 1 and 2 above provided that you also do one of the following: * accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Paragraphs 1 and 2 above; or, * accompany it with a written offer, valid for at least three years, to give any third party free (except for a nominal shipping charge) a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Paragraphs 1 and 2 above; or, * accompany it with the information you received as to where the corresponding source code may be obtained. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form alone.) For an executable file, complete source code means all the source code for all modules it contains; but, as a special exception, it need not include source code for modules which are standard libraries that accompany the operating system on which the executable file runs. 4. You may not copy, sublicense, distribute or transfer GNU Make except as expressly provided under this License Agreement. Any attempt otherwise to copy, sublicense, distribute or transfer GNU Make is void and your rights to use the program under this License agreement shall be automatically terminated. However, parties who have received computer software programs from you with this License Agreement will not have their licenses terminated so long as such parties remain in full compliance. 5. If you wish to incorporate parts of GNU Make into other free programs whose distribution conditions are different, write to the Free Software Foundation at 675 Mass Ave, Cambridge, MA 02139. We have not yet worked out a simple rule that can be stated here, but we will often permit this. We will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software. Your comments and suggestions about our licensing policies and our software are welcome! Please contact the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, or call (617) 876-3296. NO WARRANTY =========== BECAUSE GNU MAKE IS LICENSED FREE OF CHARGE, WE PROVIDE ABSOLUTELY NO WARRANTY, TO THE EXTENT PERMITTED BY APPLICABLE STATE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING, THE FREE SOFTWARE FOUNDATION, INC, RICHARD M. STALLMAN AND/OR OTHER PARTIES PROVIDE GNU MAKE "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF GNU MAKE IS WITH YOU. SHOULD GNU MAKE PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW WILL RICHARD M. STALLMAN, THE FREE SOFTWARE FOUNDATION, INC., AND/OR ANY OTHER PARTY WHO MAY MODIFY AND REDISTRIBUTE GNU MAKE AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY LOST PROFITS, LOST MONIES, OR OTHER SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS) GNU MAKE, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, OR FOR ANY CLAIM BY ANY OTHER PARTY.  File: make, Node: Top, Next: Copying, Up: (DIR) Overview of `make' ****************** The purpose of the `make' utility is to determine automatically which pieces of a large program need to be recompiled, and issue the commands to recompile them. This manual describes the GNU implementation of `make', which was implemented by Richard Stallman and Roland McGrath. Our examples show C programs, since they are most common, but you can use `make' with any programming language whose compiler can be run with a shell command. In fact, `make' is not limited to programs. You can use it to describe any task where some files must be updated automatically from others whenever the others change. To prepare to use `make', you must write a file called the "makefile" that describes the relationships among files in your program, and the states the commands for updating each file. In a program, typically the executable file is updated from object files, which are in turn made by compiling source files. Once a suitable makefile exists, each time you change some source files, this simple shell command: make suffices to perform all necessary recompilations. The `make' program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated. For each of those files, it issues the commands recorded in the data base. * Menu: * Copying:: Copying conditions for GNU Make. * Bugs:: If you have problems, or think you've found a bug. * Simple:: A simple example explained. * Makefiles:: The data base contains rules and variable definitions. * Rules:: A rule says how and when to remake one file. * Commands:: A rule contains shell commands that say how to remake. * Variables:: A variable holds a text string for substitution into rules. * Conditionals::Makefiles that do one thing or another depending on variable values. * Functions:: Functions can do text-processing within `make'. * Running:: How to run `make'; how you can adjust the way `make' uses the makefile. * Implicit:: Implicit rules take over if the makefile doesn't say how a file is to be remade. * Archives:: How to use `make' to update archive files. * Features:: GNU `make''s advanced features and how GNU `make' relates to other versions of `make'. * Missing:: Features of other `make's not supported by GNU `make'. * Concept Index::Index of cross-references to where concepts are discussed. * Name Index:: Index of cross-references for names of `make''s variables, functions, special targets and directives.  File: make, Node: Bugs, Next: Simple, Prev: Copying, Up: Top Problems and Bugs ================= If you have problems with GNU `make' or think you've found a bug, please report it to Roland McGrath; he doesn't promise to do anything but he might well want to fix it. Before reporting a bug, make sure you've actually found a real bug. Carefully reread the documentation and see if it really says you can do what you're trying to do. If it's not clear whether you should be able to do something or not, report that too; it's a bug in the documentation! Before reporting a bug or trying to fix it yourself, try to isolate it to the smallest possible makefile that reproduces the problem. Then send us the makefile and the exact results `make' gave you. Also say what you expected to occur; this will help us decide whether the problem was really in the documentation. Once you've got a precise problem, send email to (Internet) `bug-gnu-utils@prep.ai.mit.edu' or (UUCP) `mit-eddie!prep.ai.mit.edu!bug-gnu-utils'. Please include the version number of `make' you are using. You can get this information with the command `make -v -f /dev/null'. Non-bug suggestions are always welcome as well. If you have questions about things that are unclear in the documentation or are just obscure features, ask Roland McGrath; he'll be happy to help you out (but no promises). You can send him electronic mail at Internet address `roland@wheaties.ai.mit.edu' or UUCP path `mit-eddie!wheaties.ai.mit.edu!roland'.  File: make, Node: Simple, Next: Makefiles, Prev: Bugs, Up: Top Simple Example of `make' ======================== Suppose we have a text editor consisting of eight C source files and three header files. We need a makefile to tell `make' how to compile and link the editor. Assume that all the C files include `defs.h', but only those defining editing commands include `commands.h' and only low level files that change the editor buffer include `buffer.h'. To recompile the editor, each changed C source file must be recompiled. If a header file has changed, to be safe each C source file that includes the header file must be recompiled. Each compilation produces an object file corresponding to the source file. Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable editor. Here is a straightforward makefile that describes these criteria and says how to compile and link when the time comes: edit : main.o kbd.o commands.o display.o \ insert.o search.o files.o utils.o cc -o edit main.o kbd.o commands.o display.o \ insert.o search.o files.o utils.o main.o : main.c defs.h cc -c main.c kbd.o : kbd.c defs.h command.h cc -c kbd.c commands.o : command.c defs.h command.h cc -c commands.c display.o : display.c defs.h buffer.h cc -c display.c insert.o : insert.c defs.h buffer.h cc -c insert.c search.o : search.c defs.h buffer.h cc -c search.c files.o : files.c defs.h buffer.h command.h cc -c files.c utils.o : utils.c defs.h cc -c utils.c We split each long line into two lines using a backslash-newline; this is like using one long line, but is easier to read. Each file that is generated by a program---that is to say, each file except for source files---is the "target" of a "rule" (*Note Rules::.). (In this example, these are the object files such as `main.o', `kbd.o', etc., and the executable file `edit'.) The target appears at the beginning of a line, followed by a colon. After the colon come the target's "dependencies": all the files that are used as input when the target file is updated. A target file needs to be recompiled or relinked if any of its dependencies changes. In addition, any dependencies that are themselves automatically generated should be updated first. In this example, `edit' depends on each of the eight object files; the object file `main.o' depends on the source file `main.c' and on the header file `defs.h'. By default, `make' starts with the first rule (not counting rules whose target names start with `.'). This is called the "default goal". Therefore, we put the rule for the executable program `edit' first. The other rules are processed because their targets appear as dependencies of the goal. After each line containing a target and dependencies come one or more lines of shell commands that say how to update the target file. These lines start with a tab to tell `make' that they are command lines. But `make' does not know anything about how the commands work. It is up to you to supply commands that will update the target file properly. All `make' does is execute the commands you have specified when the target file needs to be updated. How `make' Processes This Makefile ---------------------------------- After reading the makefile, `make' begins its real work by processing the first rule, the one for relinking `edit'; but before it can fully process this rule, it must process the rules for the files `edit' depends on: all the object files. Each of these files is processed according to its own rule. These rules say to update the `.o' file by compiling its source file. The recompilation must be done if the source file, or any of the header files named as dependencies, is more recent than the object file, or if the object file does not exist. Before recompiling an object file, `make' considers updating its dependencies, the source file and header files. This makefile does not specify anything to be done for them---the `.c' and `.h' files are not the targets of any rules---so nothing needs to be done. But automatically generated C programs, such as made by Yacc (or Bison), would be updated by their own rules at this time. After recompiling whichever object files need it, `make' can now decide whether to relink `edit'. This must be done if the file `edit' does not exist, or if any of the object files are newer than it. If an object file was just recompiled, it is now newer than `edit', so `edit' will be relinked. Variables Make Makefiles Simpler -------------------------------- In our example, we had to list all the object files twice in the rule for `edit' (repeated here): edit : main.o kbd.o commands.o display.o \ insert.o search.o files.o utils.o cc -o edit main.o kbd.o commands.o display.o \ insert.o search.o files.o utils.o Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other. We can eliminate the risk and simplify the makefile by using a "variable". Variables allow a text string to be defined once and substituted in multiple places later (*Note Variables::.). It's standard practice for every makefile to have a variable named `objects', `OBJECTS', `objs', `OBJS', `obj' or `OBJ' which is a list of all object file names. We would define such a variable `objects' with a line like this in the makefile: objects = main.o kbd.o commands.o display.o \ insert.o search.o files.o utils.o Then, each place we want to put a list of the object file names, we can substitute the variable's value by writing `$(objects)' (*Note Variables::.). Here is how the rule for `edit' looks as a result: edit : $(objects) cc -o edit $(objects) Letting `make' Deduce the Commands ---------------------------------- It is not necessary to spell out the commands for compiling the individual C source files, because `make' can figure them out: it has an "implicit rule" for updating a `.o' file from a correspondingly named `.c' file using a `cc -c' command. For example, it will use the command `cc -c main.c -o main.o' to compile `main.c' into `main.o'. We can therefore omit the commands from the rules for the object files. *note Implicit::. When a `.c' file is used automatically in this way, it is also automatically added to the list of dependencies. We can therefore omit the `.c' files from the dependencies, provided we omit the commands. Here is the entire example, with both of these changes, and a variable `objects' as suggested above: objects = main.o kbd.o commands.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) main.o : defs.h kbd.o : defs.h command.h commands.o : defs.h command.h display.o : defs.h buffer.h insert.o : defs.h buffer.h search.o : defs.h buffer.h files.o : defs.h buffer.h command.h utils.o : defs.h This is how we would write the makefile in actual practice. Another Style of Makefile ------------------------- Since the rules for the object files specify only dependencies, no commands, one can alternatively combine them by dependency instead of by target. Here is what it looks like: objects = main.o kbd.o commands.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) $(objects) : defs.h kbd.o commands.o files.o : command.h display.o insert.o search.o files.o : buffer.h Here `defs.h' is given as a dependency of all the object files; `commands.h' and `buffer.h' are dependencies of the specific object files listed for them. Whether this is better is a matter of taste: it is more compact, but some people dislike it because they find it clearer to put all the information about each target in one place.  File: make, Node: Makefiles, Next: Rules, Prev: Simple, Up: Top Writing Makefiles ***************** The information that tells `make' how to recompile a system comes from reading a data base called the "makefile". * Menu: * Contents: Makefile Contents. Overview of what you put in a makefile. * Names: Makefile Names. Where `make' finds the makefile. * MAKEFILES Variable:: The environment can specify extra makefiles. * Include:: How one makefile can use another makefile.  File: make, Node: Makefile Contents, Next: Makefile Names, Prev: Makefiles, Up: Makefiles What Makefiles Contain ====================== Makefiles contain four kinds of things: "rules", "variable definitions", "directives" and "comments". Rules, variables and directives are described at length in later chapters. * A rule says when and how to remake one or more files, called the rule's "targets". It lists the other files that the targets "depend on", and may also give commands to use to create or update the targets. *note Rules::. * A variable definition is a line that specifies a text string value for a "variable" that can be substituted into the text later. The simple makefile example (*Note Simple::.) shows a variable definition for `objects' as a list of all object files. *note Variables::, for full details. * A directive is a command for `make' to do something special while reading the makefile. These include: * Reading another makefile (*Note Include::.). * Deciding (based on the values of variables) whether to use or ignore a part of the makefile (*Note Conditionals::.). * Defining a variable from a verbatim string containing multiple lines (*Note Defining::.). * `#' in a line of a makefile starts a comment. It and the rest of the line are ignored. Comments may appear on any of the lines in the makefile, except within a `define' directive, and perhaps within commands (where the shell decides what is a comment). A line containing just a comment (with perhaps spaces before it) is effectively blank, and is ignored.  File: make, Node: Makefile Names, Next: MAKEFILES Variable, Prev: Makefile Contents, Up: Makefiles What Name to Give Your Makefile =============================== By default, when `make' looks for the makefile, it tries the names `./makefile' and `./Makefile' in that order. So normally you call your makefile by one of these two names, and `make' finds it automatically. We recommend `Makefile' because it appears prominently near the beginning of a directory listing (right near other important files such as `README'). If `make' finds neither of these two names, it does not use any makefile. Then you must specify a goal with a command argument, and `make' will attempt to figure out how to remake it using only its built-in implicit rules. *note Implicit::. If you want to use a nonstandard name for your makefile, you can specify the makefile name with the `-f' option. The arguments `-f NAME' tell `make' to read the file NAME as the makefile. If you use more than one `-f' option, you can specify several makefiles. All the makefiles are effectively concatenated in the order specified. The default makefile names `./makefile' and `./Makefile' are not used if you specify `-f'.  File: make, Node: MAKEFILES Variable, Next: Include, Prev: Makefile Names, Up: Makefiles The Variable `MAKEFILES' ======================== If the environment variable `MAKEFILES' is defined, `make' considers its value as a list of names (separated by whitespace) of additional makefiles to be read before the others. This works much like the `include' directive: various directories are searched for those files and the default goal is never taken from them. *note Include::. In addition, it is not an error if the files listed in `MAKEFILES' are not found. The main use of `MAKEFILES' is in communication between recursive invocations of `make' (*Note Recursion::.). It usually isn't desirable to set the environment variable before a top-level invocation of `make', because it is usually better not to mess with a makefile from outside. However, if you are running `make' without a specific makefile, a makefile in `MAKEFILES' can do useful things to help the built-in implicit rules work better, such as defining search paths. Some users are tempted to set `MAKEFILES' in the environment automatically on login, and program makefiles to expect this to be done. This is a very bad idea, because such makefiles will fail to work if run by anyone else. It is much better to write explicit `include' directives in the makefiles.  File: make, Node: Include, Prev: MAKEFILES Variable, Up: Makefiles Including Other Makefiles ========================= The `include' directive tells `make' to suspend reading the current makefile and read another makefile before continuing. The directive is a line in the makefile that looks like this: include FILENAME Extra spaces are allowed and ignored at the beginning of the line, but a tab is not allowed. (If the line begins with a tab, it will be considered a command line.) Whitespace is required between `include' and FILENAME; extra whitespace is ignored there and at the end of the directive. A comment starting with `#' is allowed at the end of the line. Reading of the containing makefile is temporarily suspended while the file FILENAME is read as a makefile. When that is finished, `make' goes on with reading the makefile in which the directive appears. The default goal target is never taken from an included makefile (*Note Goals::.). One occasion for using `include' directives is when several programs, handled by individual makefiles in various directories, need to use a common set of variable definitions (*Note Setting::.) or pattern rules (*Note Pattern Rules::.). Another such occasion is when you want to automatically generate dependencies from source files; the dependencies can be put in a file that is included by the main makefile. This practice is generally cleaner than that of somehow appending the dependencies to the end of the main makefile as has been traditionally done with other versions of `make'. If the specified name does not start with a slash, and the file is not found in the current directory, several other directories are searched. First, any directories you have specified with the `-I' option are searched (*Note Options::.). Then the following directories (if they exist) are searched, in this order: `/usr/gnu/include', `/usr/local/include', `/usr/include'. If an included makefile cannot be found in any of these directories, a warning message is generated, but it is not a fatal error.  File: make, Node: Rules, Next: Commands, Prev: Makefiles, Up: Top Writing Rules ************* A "rule" appears in the makefile and says when and how to remake certain files, called the rule's "targets" (usually only one per rule). It lists the other files that are the "dependencies" of the target, and "commands" to use to create or update the target. The order of rules is not significant, except for determining the "default goal": the target for `make' to consider, if you do not otherwise specify one. The default goal comes from the first rule (not counting included makefiles) whose target does not start with a period. Therefore, the first rule is normally one for compiling the entire program or all the programs described by the makefile. *note Goals::. * Menu: * Rule Example:: An explained example of a rule. * Rule Syntax:: General syntax of rules, with explanation. * Wildcards:: Using wildcard characters like `*' in file names. * Directory Search:: Searching other directories for source files. * Phony Targets:: Using a target that isn't a real file's name. * Special Targets:: Targets with special built-in meanings. * Empty Targets:: Real files that are empty--only the date matters. * Multiple Targets:: When it is useful to have several targets in a rule. * Static Pattern:: Static pattern rules apply to multiple targets and can vary the dependencies according to the target name. * Multiple Rules:: Using several rules with the same target. * Double-Colon:: Special kind of rule allowing several independent rules for one target. * Commands:: Special features and details of how commands in a rule are executed.  File: make, Node: Rule Example, Next: Rule Syntax, Prev: Rules, Up: Rules Rule Example ------------ Here is an example of a rule: foo.o : foo.c defs.h # module for twiddling the frobs cc -c -g foo.c Its target is `foo.o' and its dependencies are `foo.c' and `defs.h'. It has one command, which is `cc -c -g foo.c'. The command line starts with a tab to identify it as a command. This rule says two things: * How to decide whether `foo.o' is out of date: it is out of date if it does not exist, or if either `foo.c' or `defs.h' is more recent than it. * How to update the file `foo.o': by running `cc' as stated. The command does not explicitly mention `defs.h', but we presume that `foo.c' includes it, and that that is why `defs.h' was added to the dependencies.  File: make, Node: Rule Syntax, Next: Wildcards, Prev: Rule Example, Up: Rules Rule Syntax =========== In general, a rule looks like this: TARGETS : DEPENDENCIES COMMAND COMMAND ... or like this: TARGETS : DEPENDENCIES ; COMMAND COMMAND COMMAND ... The TARGETS are file names, separated by spaces. Wild card characters may be used (*Note Wildcards::.) and a name of the form `A(M)' represents member M in archive file A (*Note Archive Members::.). Usually there is only one target per rule, but occasionally there is a reason to have more (*Note Multiple Targets::.). The COMMAND lines start with a tab character. The first command may appear on the line after the dependencies, with a tab character, or may appear on the same line, with a semicolon. Either way, the effect is the same. *note Commands::. Because dollar signs are used to start variable references, if you really want a dollar sign in the rule you must write two of them (`$$'). *note Variables::. A long line may be split by inserting a backslash followed by a newline, but this is not required, as there is no limit on the length of a line. A rule tells `make' two things: when the targets are out of date, and how to update them when necessary. The criterion for being out of date is specified in terms of the DEPENDENCIES, which consist of file names separated by spaces. (Wildcards and archive members are allowed here too.) A target is out of date if it does not exist or if it is older than any of the dependencies (by comparison of last-modification times). The idea is that the contents of the target file are computed based on information in the dependencies, so if any of the dependencies changes, the contents of the existing target file are no longer necessarily valid. How to update is specified by COMMANDS. These are lines to be executed by the shell (normally `sh'), but with some extra features (*Note Commands::.).  File: make, Node: Wildcards, Next: Directory Search, Prev: Rule Syntax, Up: Rules Using Wildcards Characters in File Names ======================================== A single file name can specify many files using "wildcard characters". The wildcard characters in `make' are `*', `?' and `[...]', the same as in the Bourne shell. For example, `*.c' specifies a list of all the files (in the working directory) whose names end in `.c'. Wildcard expansion happens automatically in targets, in dependencies, and in commands. In other contexts, wildcard expansion happens only if you request it explicitly with the `wildcard' function. The special significance of a wildcard character can be turned off by preceding it with a backslash. Thus, `foo\*bar' would refer to a specific file whose name consists of `foo', an asterisk, and `bar'. * Menu: * Examples: Wildcard Examples. Some simple examples. * Pitfall: Wildcard Pitfall. `*.o' won't do what you want! * Function: Wildcard Function. How to do wildcard expansion when defining a variable using the function `wildcard'.  File: make, Node: Wildcard Examples, Next: Wildcard Function, Prev: Wildcards, Up: Wildcards Wildcard Examples ----------------- Wildcards can be used in the commands of a rule. For example, here is a rule to delete all the object files: clean: rm -f *.o Wildcards are also useful in the dependencies of a rule. With the following rule in the makefile, `make print' will print all the `.c' files that have changed since the last time you printed them: print: *.c lpr -p $? touch print This rule uses `print' as an empty target file; *Note Empty Targets::.. Wildcard expansion does not happen when you define a variable. Thus, if you write this: objects=*.o then the value of the variable `objects' is the actual string `*.o'. However, if you use the value of `objects' in a target, dependency or command, wildcard expansion will take place at that time.  File: make, Node: Wildcard Pitfall, Next: Wildcard Function, Prev: Wildcard Examples, Up: Wildcards Pitfalls of Using Wildcards --------------------------- Now here is an example of a naive way of using wildcard expansion, that does not do what you would intend. Suppose you would like to say that the executable file `foo' is made from all the object files in the directory, and you write this: objects=*.o foo : $(objects) cc -o foo $(CFLAGS) $(objects) The value of `objects' is the actual string `*.o'. Wildcard expansion happens in the rule for `foo', so that each *existing* `.o' file becomes a dependency of `foo' and will be recompiled if necessary. But what if you delete all the `.o' files? Then `*.o' will expand into *nothing*. The target `foo' will have no dependencies and would be remade by linking no object files. This is not what you want! Actually you can use wildcard expansion for this purpose, but you need more sophisticated techniques, including the `wildcard' function and string substitution. *note Wildcard Function::.  File: make, Node: Wildcard Function, Prev: Wildcard Pitfall, Up: Wildcards The Function `wildcard' ----------------------- Wildcard expansion happens automatically in rules. But wildcard expansion does not normally take place when a variable is set, or inside the arguments of a function. If you want to do wildcard expansion in such places, you need to use the `wildcard' function, like this: $(wildcard PATTERN) This string, used anywhere in a makefile, is replaced by a space-separated list of names of existing files that match the pattern PATTERN. One use of the `wildcard' function is to get a list of all the C source files in a directory, like this: $(wildcard *.c) We can change the list of C source files into a list of object files by substituting `.o' for `.c' in the result, like this: $(subst .c,.o,$(wildcard *.c)) Here we have used another function, `subst' (*Note Text Functions::.). Thus, a makefile to compile all C source files in the directory and then link them together could be written as follows: objects:=$(subst .c,.o,$(wildcard *.c)) foo : $(objects) cc -o foo $(LDFLAGS) $(objects) (This takes advantage of the implicit rule for compiling C programs, so there is no need to write explicit rules for compiling the files.)  File: make, Node: Directory Search, Next: Phony Targets, Prev: Wildcards, Up: Rules Searching Directories for Dependencies ====================================== For large systems, it is often desirable to put sources in a separate directory from the binaries. The "directory search" features of `make' facilitate this by searching several directories automatically to find a dependency. When you redistribute the files among directories, you do not need to change the individual rules, just the search paths. * Menu: * General Search:: The `VPATH' variable specifies a search path that applies to every dependency. * Selective Search:: The `vpath' directive specifies a search path for a specified class of names. * Commands/Search:: How to write shell commands that work together with search paths. * Implicit/Search:: How search paths affect implicit rules. * Libraries/Search:: Directory search for link libraries.  File: make, Node: General Search, Next: Selective Search, Prev: Directory Search, Up: Directory Search `VPATH': Search Path for All Dependencies ----------------------------------------- The value of the variable `VPATH' is a list of directories which `make' should search (in the order specified) for dependency files. The directory names are separated by colons. For example: VPATH = src:../headers specifies a path containing two directories, `src' and `../headers'. Whenever a file listed as a dependency does not exist in the current directory, the directories listed in `VPATH' are searched for a file with that name. If a file is found in one of them, that file becomes the dependency. Rules may then specify the names of source files as if they all existed in the current directory. Using the value of `VPATH' set in the previous example, a rule like this: foo.o : foo.c is interpreted as if it were written like this: foo.o : src/foo.c assuming the file `foo.c' does not exist in the current directory but is found in the directory `src'.  File: make, Node: Selective Search, Next: Commands/Search, Prev: General Search, Up: Directory Search The `vpath' Directive --------------------- Similar to the `VPATH' variable but more selective is the `vpath' directive, which allows you to specify a search path for a particular class of filenames, those that match a particular pattern. Thus you can supply certain search directories for one class of filenames and other directories (or none) for other filenames. There are three forms of the `vpath' directive: `vpath PATTERN DIRECTORIES' Specify the search path DIRECTORIES for filenames that match `pattern'. If another path was previously specified for the same pattern, the new path replaces it. Note that it does *not* add to the old path for this pattern. The search path, DIRECTORIES, is a colon-separated list of directories to be searched, just like the search path used in the `VPATH' variable. `vpath PATTERN' Clear out the search path associated with PATTERN. `vpath' Clear all search paths previously specified with `vpath' directives. A `vpath' pattern is a string containing a `%' character. The string must match the filename of a dependency that is being searched for, the `%' character matching any sequence of zero or more characters (as in pattern rules; *Note Pattern Rules::.). (It is valid to omit the `%', but then the pattern must match the dependency exactly, which may not be very useful.) When a dependency fails to exist in the current directory, if the PATTERN in a `vpath' directive matches the name of the dependency file, then the DIRECTORIES in that directive are searched just like (and before) the directories in the `VPATH' variable. If several `vpath' patterns match the dependency file's name, then `make' processes each matching `vpath' directive one by one, searching all the directories mentioned in each directive. The `vpath' directives are processed in the order in which they appear in the makefiles.  File: make, Node: Commands/Search, Next: Implicit/Search, Prev: Selective Search, Up: Directory Search Writing Shell-Commands with Directory Search -------------------------------------------- When a dependency is found in another directory through directory search, this cannot change the commands of the rule; they will execute as written. Therefore, you must write the commands with care so that they will look for the dependency in the directory where `make' finds it. This is done with the "automatic variables" such as `$^' (*Note Automatic::.). For instance, the value of `$^' is a list of all the dependencies of the rule, including the names of the directories in which they were found, and the value of `$@' is the target. Thus: foo.o : foo.c cc -c $(CFLAGS) $^ -o $@ The variable `CFLAGS' exists so you can specify flags for C compilation by implicit rule; we use it here for consistency so it will affect all C compilations uniformly (*Note Implicit Variables::.). Often the dependencies include header files as well, which you don't want to mention in the commands. The function `firstword' can be used to extract just the first dependency from the entire list, as shown here (*Note Filename Functions::.): VPATH = src:../headers foo.o : foo.c defs.h hack.h cc -c $(CFLAGS) $(firstword $^) -o $@ Here the value of `$^' would be something like `src/foo.c ../headers/defs.h hack.h', from which `$(firstword $^)' extracts just `src/foo.c'.  File: make, Node: Implicit/Search, Next: Libraries/Search, Prev: Commands/Search, Up: Directory Search Directory Search and Implicit Rules ----------------------------------- The search through the directories specified in `VPATH' or with `vpath' happens also during consideration of implicit rules (*Note Implicit::.). For example, when a file `foo.o' has no explicit rule, `make' considers implicit rules, such as to compile `foo.c' if that file exists. If such a file is lacking in the current directory, the appropriate directories are searched for it. If `foo.c' exists (or is mentioned in the makefile) in any of the directories, the implicit rule for C compilation is applicable. The commands of all the built-in implicit rules normally use automatic variables as a matter of necessity; consequently they will use the file names found by directory search with no extra effort.  File: make, Node: Libraries/Search, Prev: Implicit/Search, Up: Directory Search Directory Search for Link Libraries ----------------------------------- Directory search applies in a special way to libraries used with the linker. This special feature comes into play when you write a dependency whose name is of the form `-lNAME'. (You can tell something funny is going on here because the dependency is normally the name of a file, and the *file name* of the library looks like `libNAME.a', not like `-lNAME'.) When a dependency's name has the form `-lNAME', `make' handles it specially by searching for the file `libNAME.a' in the directories `/lib' and `/usr/lib', and then using matching `vpath' search paths and the `VPATH' search path. For example, foo : foo.c -lcurses cc $^ -o $@ would cause the command `cc foo.c -lcurses -o foo' to be executed when `foo' is older than `foo.c' or than `libcurses.a' (which has probably been found by directory search in the file `/usr/lib/libcurses.a'). As shown by the example above, the file name found by directory search is used only for comparing the file time with the target file's time. It does not replace the file's name in later usage (such as in automatic variables like `$^'); the name remains unchanged, still starting with `-l'. This leads to the correct results because the linker will repeat the appropriate search when it processes its arguments.  File: make, Node: Phony Targets, Next: Empty Targets, Prev: Directory Search, Up: Rules Phony Targets ============= A phony target is one that is not really the name of a file. It is only a name for some commands to be executed when explicitly requested. If you write a rule whose commands will not create the target file, the commands will be executed every time the target comes up for remaking. Here is an example: clean: rm *.o temp Because the `rm' command does not create a file named `clean', probably no such file will ever exist. Therefore, the `rm' command will be executed every time you say `make clean'. The phony target will cease to work if anything ever does create a file named `clean' in this directory. Since there are no dependencies, the `clean' would be considered up to date and its commands would not be executed. To avoid this problem, you can explicitly declare the target to be phony, using the special target `.PHONY' (*Note Special Targets::.) as follows: .PHONY : clean Once this is done, `make' will run the commands regardless of whether there is a file named `clean'. A phony target should not be a dependency of a real target file; strange things can result from that. As long as you don't do that, the phony target commands will be executed only when the phony target is a goal (*Note Goals::.). Phony targets can have dependencies. When one directory contains multiple programs, it is most convenient to describe all of the programs in one makefile `./Makefile'. Since the target remade by default will be the first one in the makefile, it is common to make this a phony target named `all' and give it, as dependencies, all the individual programs. For example: all : prog1 prog2 prog3 .PHONY : all prog1 : prog1.o utils.o cc -o prog1 prog1.o utils.o prog2 : prog2.o cc -o prog2 prog2.o prog3 : prog3.o sort.o utils.o cc -o prog3 prog3.o sort.o utils.o Now you can say just `make' to remake all three programs, or specify as arguments the ones to remake (as in `make prog1 prog3'). When one phony target is a dependency of another, it serves as a subroutine of the other. For example, here `make cleanall' will delete the object files, the difference files, and the file `program': cleanall : cleanobj cleandiff rm program cleanobj : rm *.o cleandiff : rm *.diff  File: make, Node: Empty Targets, Next: Special Targets, Prev: Phony Targets, Up: Rules Empty Target Files to Record Events =================================== The "empty target" is a variant of the phony target; it is used to hold commands for an action that you request explicitly from time to time. Unlike a phony target, this target file can really exist; but the file's contents do not matter, and usually are empty. The purpose of the empty target file is to record, with its last-modification-time, when the rule's commands were last executed. It does so because one of the commands is a `touch' command to update the target file. The empty target file must have some dependencies. When you ask to remake the empty target, the commands are executed if any dependency is more recent than the target; in other words, if a dependency has changed since the last time you remade the target. Here is an example: print: foo.c bar.c lpr -p $? touch print With this rule, `make print' will execute the `lpr' command if either source file has changed since the last `make print'. The automatic variable `$?' is used to print only those files that have changed (*Note Automatic::.).  File: make, Node: Special Targets, Next: Multiple Targets, Prev: Empty Targets, Up: Rules Special Built-in Target Names ============================= Certain names have special meanings if they appear as targets. `.PHONY' The dependencies of the special target `.PHONY' are considered to be phony targets. When it is time to consider such a target, `make' will run its commands unconditionally, regardless of whether a file with that name exists or what its last-modification time is. *note Phony Targets::. `.SUFFIXES' The dependencies of the special target `.SUFFIXES' are the list of suffixes to be used in checking for suffix rules (*Note Suffix Rules::.). `.DEFAULT' The commands specified for `.DEFAULT' are used for any target for which no other commands are known (either explicitly or through an implicit rule). If `.DEFAULT' commands are specified, every nonexistent file mentioned as a dependency will have these commands executed on its behalf. *note Search Algorithm::. `.PRECIOUS' The targets which `.PRECIOUS' depends on are given this special treatment: if `make' is killed or interrupted during the execution of their commands, the target is not deleted. *note Interrupts::. `.IGNORE' Simply by being mentioned as a target, `.IGNORE' says to ignore errors in execution of commands. The dependencies and commands for `.IGNORE' are not meaningful. `.IGNORE' exists for historical compatibility. Since `.IGNORE' affects every command in the makefile, it is not very useful; we recommend you use the more selective ways to ignore errors in specific commands (*Note Errors::.). `.SILENT' Simply by being mentioned as a target, `.SILENT' says not to print commands before executing them. The dependencies and commands for `.SILENT' are not meaningful. `.SILENT' exists for historical compatibility. We recommend you use the more selective ways to silence specific commands (*Note Echoing::.). An entire class of special targets have names made of the concatenation of two implicit rule suffixes (two members of the list of dependencies of `.SUFFIXES'). Such special targets are suffix rules, an obsolete way of defining implicit rules (but a way still widely used). In principle, any target name could be special in this way if you break it in two and add both pieces to the suffix list. In practice, suffixes normally begin with `.', so these special target names also begin with `.'. *note Suffix Rules::. 