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Text File  |  1998-04-08  |  15.1 KB  |  319 lines
  1. FALCON REGISTERS 2
  2.  
  3. HOW to access the play/record-frame:
  4. You have to set bit 7 of $8901.w to select play- or record-shadowregister, 
  5. then access the frame-begin/end-registers! The play- and record-shadow-
  6. register are two seperate registers; they appear only at the same 
  7. addresses!
  8.  
  9. $FFFF8920 [R/W] :$00 __54__10 ........................... Track-Play-Control
  10.                        ||  ||
  11.                        ||  00---- play 1 track
  12.                        ||  01---- play 2 tracks
  13.                        ||  10---- play 3 tracks
  14.                        ||  11---- play 4 tracks
  15.                        00 ------- connect track 1 with speaker
  16.                        01 ------- connect track 2 with speaker
  17.                        10 ------- connect track 3 with speaker
  18.                        11 ------- connect track 4 with speaker
  19. $FFFF8921 [R/W] :$03 76____10 ........................... Sound-Mode-Control
  20.                      ||    ||
  21.                      ||    00---- nute condition (on STE: 6258 Hz)
  22.                      ||    01---- 12517 HZ 
  23.                      ||    10---- 25033 HZ
  24.                      ||    11---- 50066 HZ
  25.                      |+---------- 0:  8 Bit
  26.                      |            1: 16 Bit
  27.                      +----------- 0: Stereo
  28.                                   1: Mono
  29. Nice to know: The samplerate 6258 Hz was repleaced by a nute condition.
  30.               You can use it to deactivate the DMA-Transfer.
  31.  
  32. $FFFF8922 [R/-] :$00 not accessed by the XBIOS.
  33. $FFFF8923 [R/-] :$00 The FALCON has no 
  34. $FFFF8924 [R/-] :$00 Microwire-
  35. $FFFF8925 [R/-] :$00 Interface!!
  36. $FFFF8930 [R/W] :$01 76543210 ......... Sound-Source-Device-Prescale-Mode Hi 
  37.                      ||||||||
  38.                      ||||||||     Source-Device: EXT-INP
  39.                      |||||||+---- 1: Handshaking off
  40.                      |||||++----- Source-Clock
  41.                      ||||+------- set to zero
  42.                      ||||
  43.                      ||||         Source-Device: A/D-Converter
  44.                      |||+-------- set to zero
  45.                      ||+--------- 0: internal 25.175 MHz-Clock
  46.                      ||           1: extermal Clock
  47.                      ++---------- set to zero
  48. $FFFF8931 [R/W] :$11 76543210 ......... Sound-Source-Device-Prescale-Mode Lo
  49.                      ||||||||
  50.                      ||||||||     Source-Device: DMA-PLAY
  51.                      |||||||+---- 1: Handshaking off
  52.                      |||||++----- Source-Clock
  53.                      ||||+------- 0: if handshaking on and destination=
  54.                      ||||            DSP-REC
  55.                      ||||         1: if destination<>DSP-REC
  56.                      ||||         (this allows a automatic transfer from
  57.                      ||||         (memory to DSP without errors.)
  58.                      ||||         
  59.                      ||||         Source-Device: DSP-XMIT
  60.                      |||+-------- 1: Handshaking off
  61.                      |++--------- Source-Clock
  62.                      +----------- 0: Tristate, disconnect DSP from Multi-
  63.                                      plexer (only if you want to use the 
  64.                                      external SSI-Port)
  65.                                   1: connect DSP with Multiplexer
  66. Source-Clock can be :   %00: internal 25.175 MHz-Clock
  67.                         %01: external Clock
  68.                         %10: intermal 32 MHz-Clock,do not use it for the
  69.                              CODEC (A/D- and D/A-Converter).
  70.                         %11: not defined
  71.  
  72. $FFFF8932 [R/W] :$00 76543210 ........... Sound-Destination-Device-Matrix Hi
  73.                      ||||||||
  74.                      ||||||||     Source-Device for destination: EXT-OUT
  75.                      |||||||+---- 1: Handshaking off
  76.                      |||||++----- Source-Device
  77.                      ||||+------- set to zero
  78.                      ||||
  79.                      ||||         Source-Device for destination: DAC
  80.                      |||+-------- set to zero
  81.                      |++--------- Source-Device
  82.                      +----------- set to zero
  83. $FFFF8933 [R/W] :$00 76543210 ........... Sound-Destination-Device-Matrix Lo
  84.                      ||||||||
  85.                      ||||||||     Source-Device for destination: DMA-REC
  86.                      |||||||+---- 1: Handshaking off
  87.                      |||||++----- Source-Device
  88.                      ||||+------- 0: if handshaking on and source=DSP-XMIT
  89.                      ||||         1: if source<>DSP-XMIT 
  90.                      ||||         (this modus allows a automatic transfer 
  91.                      ||||         from DSP to memory without errors.)
  92.                      ||||
  93.                      ||||         Source-Device for destination: DSP-REC
  94.                      |||+-------- 1: Handshaking off
  95.                      |++--------- Source-Device
  96.                      +----------- 0: Tristate, disconnect DSP from Multi-
  97.                                      plexer (only if you want to use the 
  98.                                      external SSI-Port)
  99.                                   1: connect DSP with Multiplexer
  100. Source-Device can be:   %00: DMA-PLAY
  101.                         %01: DSP-XMIT (DSP send data)
  102.                         %10: EXT-INP (External Input)
  103.                         %11: A/D-Converter
  104.  
  105. $FFFF8934 [R/W] :$00 ____3210 ...................... Prescale external Clock
  106.                          ||||
  107.                          ++++----    0: switch to STE-compatible mode
  108.                                   1-15: Clock devided by 256, devided by
  109.                                         prescalevalue+1.
  110.                                   Documentation only allows values between 
  111.                                   0 and 15, but the XBIOS allows values 
  112.                                   between 0 and 255. The upper nibble is
  113.                                   cut by the hardware.  
  114. $FFFF8935 [R/W] :$01 ____3210 ... Prescale internal Clock (25.175 or 32 MHz)
  115.                          ||||
  116.                          ++++---- look above! According to the 
  117.                          ||||     Documentation you can only use the 
  118.                          ||||     following values for the CODEC(A/D- and
  119.                          ||||     D/A-Converter): 0,1,2,3,4,5,7,9,11  
  120.                          0000---- switch to STE-compatible mode
  121.                          0001---- CLK50K  49170 Hz
  122.                          0010---- CLK33K  32780 Hz
  123.                          0011---- CLK25K  24585 Hz
  124.                          0100---- CLK20K  19668 Hz
  125.                          0101---- CLK16K  16390 Hz
  126.                          0110---- CLK14K  14049 Hz (invalid for CODEC)
  127.                          0111---- CLK12K  12292 Hz
  128.                          1000---- CLK11K  10927 Hz (invalid for CODEC)
  129.                          1001---- CLK10K   9834 Hz
  130.                          1010---- CLK09K   8940 Hz (invalid for CODEC)
  131.                          1011---- CLK08K   8195 Hz
  132.                          1100---- CLK07K   7565 Hz (invalid for CODEC)
  133.                          1101---- CLK07K   7024 Hz (invalid for CODEC)
  134.                          1110---- CLK06K   6556 Hz (invalid for CODEC)
  135.                          1111---- CLK06K   6146 HZ (invalid for CODEC)
  136. $FFFF8936 [R/W] :$00 ______10 ......................... Track-Record-Control
  137.                            ||
  138.                            00---- record 1 track
  139.                            01---- record 2 tracks
  140.                            10---- record 3 tracks
  141.                            11---- record 4 tracks
  142. $FFFF8937 [R/W] :$03 ______10 .................... CODEC-Hardwareadder-Input 
  143.                            ||                      (ADDRIN-register)
  144.                            ||       Source-input of the 16-bit-hardwareadder
  145.                            ||
  146.                            |+---- 1: input from A/D-Converter
  147.                            +----- 1: input from Multiplexer
  148. NOTE: The CODEC-Hardwareadder-Input connects the D/A-Converter with the 
  149.       multiplexer or the A/D-Converter. It is also possible to connect both.
  150.       In this case the 16-bit-Hardwareadder mix the two signals.
  151.  
  152. $FFFF8938 [R/W] :$03 ______10 .......................... A/D-Converter-Input
  153.                            ||                            (ADCINPUT-register)
  154.                            |+---- 0: input from right mic-channel
  155.                            |      1: input from right PSG-channel
  156.                            +----- 0: input from left mic-channel
  157.                                   1: input from left PSG-channel
  158. $FFFF8939 [R/W] :$88 76543210 ..... Channel-Input-Amplifier in +1.5 dB steps
  159.                      ||||||||       (GAIN-register)
  160.                      ||||||||
  161.                      ||||++++---- 0-15: Gain right channel (RTGAIN) 
  162.                      ++++-------- 0-15: Gain of left channel (LTGAIN)
  163. $FFFF893A [R/W] :$07 ____3210 . Channel-Output-Amplifier in -1.5 dB-steps Hi
  164.                          ||||   (ATTEN-register)
  165.                          ||||
  166.                          ++++---- 0-15: Attenuation of feft channal(LTATTEN)
  167. $FFFF893B [R/W] :$70 7654____ ........................................... Lo
  168.                      ||||
  169.                      ++++------- 0-15: Attenuation of right channel(RTATTEN)
  170. $FFFF893C [R/W] :$64 ______10 .............................. CODEC-Status Hi
  171.                            ||
  172.                            |+---- 1: right channel-overflow
  173.                            +----- 1: left channel-overflow
  174. $FFFF893D [R/W] :$00 7654____ .............................. CODEC-Status Lo
  175.                      ||||
  176.                      |||+------ ?
  177.                      ||+------- ?
  178.                      |+-------- ?
  179.                      +--------- ?
  180. $FFFF893E [R/W] :$81 not accessed
  181. $FFFF893F [R/W] :$00 by the XBIOS
  182. $FFFF8940 [R/W] :$00 <===== Hi
  183. $FFFF8941 [R/W] :$00 _____210 ..............................GPx-Dataportpath
  184.                           |||
  185.                           +++---- bidirectional Dataportpath of the GP0-
  186.                                   GP2-Pins on the DSP-Connector
  187.                                   0: Pin set to Input (read data from GPx)
  188.                                   1: Pin set to Output (write data to GPx)
  189.                                      (normally %111)
  190. $FFFF8942 [R/W] :$00 <===== Hi 
  191. $FFFF8943 [R/W] :$07 _____210 ................................. GPx-Dataport
  192.                           |||
  193.                           +++---- Input/Output-Data-Bits of the 
  194.                                   GP0-GP2-Pins on the DSP-Connector. This
  195.                                   Pins can be used for userdef. operations.
  196.                                
  197.  
  198.  
  199. ****************************************************************************
  200.                        C L O C K  -  C H I P  ( T T )
  201. ****************************************************************************
  202.  
  203. $FFFF8960 [R/W] :$DF ******
  204. $FFFF8961 [R/W] :$FF Register Selection
  205. $FFFF8962 [R/W] :$DF ******
  206. $FFFF8963 [R/W] :$FF Data
  207.  
  208.  
  209.  
  210. ****************************************************************************
  211.                           B L I T T E R  ( S T E )
  212. ****************************************************************************
  213.  
  214. $FFFF8A00 [R/W] :$FF Halftone RAM $00 Hi
  215. $FFFF8A01 [R/W] :$FF                  Lo
  216. $FFFF8A02 [R/W] :$FF Halftone RAM $01 Hi
  217. $FFFF8A03 [R/W] :$FF                  Lo
  218. $FFFF8A04 [R/W] :$FF Halftone RAM $02 Hi
  219. $FFFF8A05 [R/W] :$FF                  Lo
  220. $FFFF8A06 [R/W] :$FF Halftone RAM $03 Hi
  221. $FFFF8A07 [R/W] :$FF                  Lo
  222. $FFFF8A08 [R/W] :$FF Halftone RAM $04 Hi
  223. $FFFF8A09 [R/W] :$FF                  Lo
  224. $FFFF8A0A [R/W] :$FF Halftone RAM $05 Hi
  225. $FFFF8A0B [R/W] :$FF                  Lo
  226. $FFFF8A0C [R/W] :$FF Halftone RAM $06 Hi
  227. $FFFF8A0D [R/W] :$FF                  Lo
  228. $FFFF8A0E [R/W] :$FF Halftone RAM $07 Hi
  229. $FFFF8A0F [R/W] :$FF                  Lo
  230. $FFFF8A10 [R/W] :$FF Halftone RAM $08 Hi
  231. $FFFF8A11 [R/W] :$FF                  Lo
  232. $FFFF8A12 [R/W] :$FF Halftone RAM $09 Hi
  233. $FFFF8A13 [R/W] :$FF                  Lo
  234. $FFFF8A14 [R/W] :$FF Halftone RAM $0A Hi
  235. $FFFF8A15 [R/W] :$FF                  Lo
  236. $FFFF8A16 [R/W] :$FF Halftone RAM $0B Hi
  237. $FFFF8A17 [R/W] :$FF                  Lo
  238. $FFFF8A18 [R/W] :$FF Halftone RAM $0C Hi
  239. $FFFF8A19 [R/W] :$FF                  Lo
  240. $FFFF8A1A [R/W] :$FF Halftone RAM $0D Hi
  241. $FFFF8A1B [R/W] :$FF                  Lo
  242. $FFFF8A1C [R/W] :$FF Halftone RAM $0E Hi
  243. $FFFF8A1D [R/W] :$FF                  Lo
  244. $FFFF8A1E [R/W] :$FF Halftone RAM $0F Hi
  245. $FFFF8A1F [R/W] :$FF                  Lo
  246. $FFFF8A20 [R/W] :$00 Source-X-Increment Hi
  247. $FFFF8A21 [R/W] :$00                    Lo
  248. $FFFF8A22 [R/W] :$FF Source-Y-Increment Hi
  249. $FFFF8A23 [R/W] :$00                    Lo
  250. $FFFF8A24 [R/W] :$00 ******
  251. $FFFF8A25 [R/W] :$E4 Source-Address Hi
  252. $FFFF8A26 [R/W] :$89                Mi
  253. $FFFF8A27 [R/W] :$6C                Lo
  254. $FFFF8A28 [R/W] :$FF End-Mask 1 Hi
  255. $FFFF8A29 [R/W] :$FF            Lo
  256. $FFFF8A2A [R/W] :$FF End-Mask 2 Hi
  257. $FFFF8A2B [R/W] :$FF            Lo
  258. $FFFF8A2C [R/W] :$FF End-Mask 3 Hi
  259. $FFFF8A2D [R/W] :$FF            Lo
  260. $FFFF8A2E [R/W] :$00 Destination-X-Increment Hi
  261. $FFFF8A2F [R/W] :$04                         Lo
  262. $FFFF8A30 [R/W] :$00 Destination-Y-Increment Hi
  263. $FFFF8A31 [R/W] :$54                         Lo
  264. $FFFF8A32 [R/W] :$00 ******
  265. $FFFF8A33 [R/W] :$3F Destination-Address Hi
  266. $FFFF8A34 [R/W] :$FD                     Mi
  267. $FFFF8A35 [R/W] :$EA                     Lo
  268. $FFFF8A36 [R/W] :$00 X-Count Hi
  269. $FFFF8A37 [R/W] :$14         Lo
  270. $FFFF8A38 [R/W] :$00 Y-Count Hi
  271. $FFFF8A39 [R/W] :$00         Lo
  272. $FFFF8A3A [R/W] :$01 Halftone-Operation
  273. $FFFF8A3B [R/W] :$03 Logic-Operation
  274. $FFFF8A3C [R/W] :$06 Line-Number
  275. $FFFF8A3D [R/W] :$00 Skew
  276. $FFFF8A3E [R/W] :$FF ******
  277. $FFFF8A3F [R/W] :$FF ******
  278.  
  279.  
  280.  
  281. ****************************************************************************
  282. S E R I A L  -  C O M M U N I C A T I O N S  -  C O N T R O L L E R  ( T T )
  283. ****************************************************************************
  284.  
  285. $FFFF8C80 [R/W] :$9F ******
  286. $FFFF8C81 [R/W] :$EC Register Selection Channel A
  287. $FFFF8C82 [R/W] :$FF ******
  288. $FFFF8C83 [R/W] :$FF Read / Write Data Channel A
  289. $FFFF8C84 [R/W] :$8F ******
  290. $FFFF8C85 [R/W] :$44 Register Selection Channel B
  291. $FFFF8C86 [R/W] :$FF ******
  292. $FFFF8C87 [R/W] :$FF Read / Write Data Channel B
  293.  
  294.  
  295.  
  296. ****************************************************************************
  297.         J O Y S T I C K  /  L I G H T P E N  -  P O R T S  ( S T E )
  298. ****************************************************************************
  299.  
  300. $FFFF9200 [R/W] :$BF Fire-Buttons 1-4 Hi
  301. $FFFF9201 [R/W] :$FF                  Lo
  302. $FFFF9202 [R/W] :$FF Joysticks 1-4 Hi
  303. $FFFF9203 [R/W] :$FF               Lo
  304. $FFFF9210 [R/W] :$8F Position Paddle 0 Hi
  305. $FFFF9211 [R/W] :$FF                   Lo
  306. $FFFF9212 [R/W] :$8F Position Paddle 1 Hi
  307. $FFFF9213 [R/W] :$FF                   Lo
  308. $FFFF9214 [R/W] :$8F Position Paddle 2 Hi
  309. $FFFF9215 [R/W] :$FF                   Lo
  310. $FFFF9216 [R/W] :$8F Position Paddle 3 Hi
  311. $FFFF9217 [R/W] :$FF                   Lo
  312. $FFFF9220 [R/W] :$00 Lightpen X-Position Hi
  313. $FFFF9221 [R/W] :$00                     Lo
  314. $FFFF9222 [R/W] :$00 Lightpen Y-Position Hi
  315. $FFFF9223 [R/W] :$00                     Lo
  316.  
  317.  
  318.  
  319.