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INTERNALS 1. Machine Descriptions A machine description has two parts: a file of instruc- tion patterns (`.md' file) and a C header file of macro definitions. The `.md' file for a target machine contains a pattern for each instruction that the target machine supports (or at least each instruction that is worth telling the compiler about). It may also contain comments. A semicolon causes the rest of the line to be a comment, unless the semicolon is inside a quoted string. See the next chapter for information on the C header file. 1.1. Everything about Instruction Patterns Each instruction pattern contains an incomplete RTL expression, with pieces to be filled in later, operand con- straints that restrict how the pieces can be filled in, and an output pattern or C code to generate the assembler out- put, all wrapped up in a define_insn expression. A define_insn is an RTL expression containing four or five operands: 1. An optional name. The presence of a name indicate that this instruction pattern can perform a cer- tain standard job for the RTL-generation pass of the compiler. This pass knows certain names and will use the instruction patterns with those names, if the names are defined in the machine description. The absence of a name is indicated by writing an empty string where the name should go. Nameless instruction patterns are never used for generating RTL code, but they may permit several simpler insns to be combined later on. Names that are not thus known and used in RTL- generation have no effect; they are equivalent to no name at all. 2. The RTL template (see section RTL Template) is a vector of incomplete RTL expressions which show what the instruction should look like. It is in- complete because it may contain match_operand, match_operator, and match_dup expressions that stand for operands of the instruction. If the vector has only one element, that element is the template for the instruction pattern. If the vector has multiple elements, then the in- struction pattern is a parallel expression con- taining the elements described. 3. A condition. This is a string which contains a C expression that is the final test to decide wheth- er an insn body matches this pattern. For a named pattern, the condition (if present) may not depend on the data in the insn being matched, but only the target-machine-type flags. The compiler needs to test these conditions during initialization in order to learn exactly which named instructions are available in a particular run. For nameless patterns, the condition is applied only when matching an individual insn, and only after the insn has matched the pattern's recogni- tion template. The insn's operands may be found in the vector operands. 4. The output template: a string that says how to output matching insns as assembler code. `%' in this string specifies where to substitute the value of an operand. See section Output Template. When simple substitution isn't general enough, you can specify a piece of C code to compute the out- put. See section Output Statement. 5. Optionally, a vector containing the values of at- tributes for insns matching this pattern. See section Insn Attributes. 1.2. Example of define_insn Here is an actual example of an instruction pattern, for the 68000/68020. (define_insn "tstsi" [(set (cc0) (match_operand:SI 0 "general_operand" "rm"))] "" "* { if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) return \"tstl %0\"; return \"cmpl #0,%0\"; }") This is an instruction that sets the condition codes based on the value of a general operand. It has no condi- tion, so any insn whose RTL description has the form shown may be handled according to this pattern. The name `tstsi' means ``test a SImode value'' and tells the RTL generation pass that, when it is necessary to test such a value, an insn to do so can be constructed using this pattern. The output control string is a piece of C code which chooses which output template to return based on the kind of operand and the specific type of CPU for which code is being generated. `"rm"' is an operand constraint. Its meaning is explained below. 1.3. RTL Template for Generating and Recognizing Insns The RTL template is used to define which insns match the particular pattern and how to find their operands. For named patterns, the RTL template also says how to construct an insn from specified operands. Construction involves substituting specified operands into a copy of the template. Matching involves determining the values that serve as the operands in the insn being matched. Both of these activities are controlled by special expression types that direct matching and substitution of the operands. (match_operand:m n predicate constraint) This expression is a placeholder for operand number n of the insn. When constructing an insn, operand number n will be substituted at this point. When matching an insn, whatever appears at this position in the insn will be taken as operand number n; but it must satisfy predicate or this instruction pattern will not match at all. Operand numbers must be chosen consecutively counting from zero in each instruction pattern. There may be only one match_operand expression in the pattern for each operand number. Usually operands are numbered in the order of appearance in match_operand expressions. predicate is a string that is the name of a C function that accepts two arguments, an expression and a machine mode. During matching, the function will be called with the putative operand as the expression and m as the mode argument (if m is not specified, VOIDmode will be used, which normally causes predicate to accept any mode). If it re- turns zero, this instruction pattern fails to match. predicate may be an empty string; then it means no test is to be done on the operand, so anything which occurs in this position is valid. Most of the time, predicate will reject modes oth- er than m---but not always. For example, the predicate address_operand uses m as the mode of memory ref that the address should be valid for. Many predicates accept const_int nodes even though their mode is VOIDmode. constraint controls reloading and the choice of the best register class to use for a value, as ex- plained later (see section Constraints). People are often unclear on the difference between the constraint and the predicate. The predicate helps decide whether a given insn matches the pat- tern. The constraint plays no role in this deci- sion; instead, it controls various decisions in the case of an insn which does match. On CISC machines, predicate is most often "general_operand". This function checks that the putative operand is either a constant, a register or a memory reference, and that it is valid for mode m. For an operand that must be a register, predicate should be "register_operand". It would be valid to use "general_operand", since the reload pass would copy any non-register operands through re- gisters, but this would make GNU CC do extra work, it would prevent invariant operands (such as con- stant) from being removed from loops, and it would prevent the register allocator from doing the best possible job. On RISC machines, it is usually most efficient to allow predicate to accept only objects that the constraints allow. For an operand that must be a constant, either use "immediate_operand" for predicate, or make the in- struction pattern's extra condition require a con- stant, or both. You cannot expect the constraints to do this work! If the constraints allow only constants, but the predicate allows something else, the compiler will crash when that case ar- ises. (match_scratch:m n constraint) This expression is also a placeholder for operand number n and indicates that operand must be a scratch or reg expression. When matching patterns, this is completely equivalent to (match_operand:m n "scratch_operand" pred) but, when generating RTL, it produces a (scratch:m) expression. If the last few expressions in a parallel are clobber expressions whose operands are either a hard register or match_scratch, the combiner can add them when necessary. See section Side Effects. (match_dup n) This expression is also a placeholder for operand number n. It is used when the operand needs to appear more than once in the insn. In construction, match_dup behaves exactly like match_operand: the operand is substituted into the insn being constructed. But in matching, match_dup behaves differently. It assumes that operand number n has already been determined by a match_operand appearing ear- lier in the recognition template, and it matches only an identical-looking expression. (match_operator:m n predicate [operands...]) This pattern is a kind of placeholder for a variable RTL expression code. When constructing an insn, it stands for an RTL expression whose expression code is taken from that of operand n, and whose operands are constructed from the patterns operands. When matching an expression, it matches an ex- pression if the function predicate returns nonzero on that expression and the patterns operands match the operands of the expression. Suppose that the function commutative_operator is defined as follows, to match any expression whose operator is one of the commutative ar- ithmetic operators of RTL and whose mode is mode: int commutative_operator (x, mode) rtx x; enum machine_mode mode; { enum rtx_code code = GET_CODE (x); if (GET_MODE (x) != mode) return 0; return GET_RTX_CLASS (code) == 'c' || code == EQ || code == NE; } Then the following pattern will match any RTL expression consisting of a commutative opera- tor applied to two general operands: (match_operator:SI 3 "commutative_operator" [(match_operand:SI 1 "general_operand" "g") (match_operand:SI 2 "general_operand" "g")]) Here the vector [operands...] contains two patterns because the expressions to be matched all contain two operands. When this pattern does match, the two operands of the commutative operator are recorded as operands 1 and 2 of the insn. (This is done by the two instances of match_operand.) Operand 3 of the insn will be the entire com- mutative expression: use GET_CODE (operands[3]) to see which commutative opera- tor was used. The machine mode m of match_operator works like that of match_operand: it is passed as the second argument to the predicate function, and that function is solely responsible for deciding whether the expression to be matched ``has'' that mode. When constructing an insn, argument 3 of the gen-function will specify the operation (i.e. the expression code) for the expression to be made. It should be an RTL expression, whose expression code is copied into a new expres- sion whose operands are arguments 1 and 2 of the gen-function. The subexpressions of argu- ment 3 are not used; only its expression code matters. When match_operator is used in a pattern for matching an insn, it usually best if the operand number of the match_operator is higher than that of the actual operands of the insn. This improves register allocation because the register allocator often looks at operands 1 and 2 of insns to see if it can do register tying. There is no way to specify constraints in match_operator. The operand of the insn which corresponds to the match_operator never has any constraints because it is never reloaded as a whole. However, if parts of its operands are matched by match_operand patterns, those parts may have constraints of their own. (address (match_operand:m n "address_operand" "")) This complex of expressions is a placeholder for an operand number n in a ``load address'' instruction: an operand which specifies a memory location in the usual way, but for which the actual operand value used is the ad- dress of the location, not the contents of the location. address expressions never appear in RTL code, only in machine descriptions. And they are used only in machine descriptions that do not use the operand constraint feature. When operand constraints are in use, the letter `p' in the constraint serves this purpose. m is the machine mode of the memory location being addressed, not the machine mode of the address itself. That mode is always the same on a given target machine (it is Pmode, which normally is SImode), so there is no point in mentioning it; thus, no machine mode is writ- ten in the address expression. If some day support is added for machines in which ad- dresses of different kinds of objects appear differently or are used differently (such as the PDP-10), different formats would perhaps need different machine modes and these modes might be written in the address expression. 1.4. Output Templates and Operand Substitution The output template is a string which specifies how to output the assembler code for an instruction pattern. Most of the template is a fixed string which is output literally. The character `%' is used to specify where to substitute an operand; it can also be used to identify places where dif- ferent variants of the assembler require different syntax. In the simplest case, a `%' followed by a digit n says to output operand n at that point in the string. `%' followed by a letter and a digit says to output an operand in an alternate fashion. Four letters have stan- dard, built-in meanings described below. The machine description macro PRINT_OPERAND can define additional letters with nonstandard meanings. `%cdigit' can be used to substitute an operand that is a constant value without the syntax that normally indicates an immediate operand. `%ndigit' is like `%cdigit' except that the value of the constant is negated before printing. `%adigit' can be used to substitute an operand as if it were a memory reference, with the actual operand treated as the address. This may be useful when outputting a ``load address'' instruction, because often the assembler syntax for such an instruction requires you to write the operand as if it were a memory reference. `%ldigit' is used to substitute a label_ref into a jump instruction. `%' followed by a punctuation character specifies a substitution that does not use an operand. Only one case is standard: `%%' outputs a `%' into the assembler code. Other nonstandard cases can be defined in the PRINT_OPERAND macro. You must also define which punctuation characters are valid with the PRINT_OPERAND_PUNCT_VALID_P macro. The template may generate multiple assembler instruc- tions. Write the text for the instructions, with `\;' between them. When the RTL contains two operands which are required by constraint to match each other, the output template must refer only to the lower-numbered operand. Matching operands are not always identical, and the rest of the compiler arranges to put the proper RTL expression for printing into the lower-numbered operand. One use of nonstandard letters or punctuation following `%' is to distinguish between different assembler languages for the same machine; for example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax requires periods in most opcode names, while MIT syntax does not. For exam- ple, the opcode `movel' in MIT syntax is `move.l' in Motorola syntax. The same file of patterns is used for both kinds of output syntax, but the character sequence `%.' is used in each place where Motorola syntax wants a period. The PRINT_OPERAND macro for Motorola syntax defines the sequence to output a period; the macro for MIT syntax defines it to do nothing. 1.5. C Statements for Generating Assembler Output Often a single fixed template string cannot produce correct and efficient assembler code for all the cases that are recognized by a single instruction pattern. For exam- ple, the opcodes may depend on the kinds of operands; or some unfortunate combinations of operands may require extra machine instructions. If the output control string starts with a `@', then it is actually a series of templates, each on a separate line. (Blank lines and leading spaces and tabs are ignored.) The templates correspond to the pattern's constraint alterna- tives (see section Multi-Alternative). For example, if a target machine has a two-address add instruction `addr' to add into a register and another `addm' to add a register to memory, you might write this pattern: (define_insn "addsi3" [(set (match_operand:SI 0 "general_operand" "r,m") (plus:SI (match_operand:SI 1 "general_operand" "0,0") (match_operand:SI 2 "general_operand" "g,r")))] "" "@ addr %1,%0 addm %1,%0") If the output control string starts with a `*', then it is not an output template but rather a piece of C program that should compute a template. It should execute a return statement to return the template-string you want. Most such templates use C string literals, which require doublequote characters to delimit them. To include these doublequote characters in the string, prefix each one with `\'. The operands may be found in the array operands, whose C data type is rtx []. It is very common to select different ways of generat- ing assembler code based on whether an immediate operand is within a certain range. Be careful when doing this, because the result of INTVAL is an integer on the host machine. If the host machine has more bits in an int than the target machine has in the mode in which the constant will be used, then some of the bits you get from INTVAL will be superflu- ous. For proper results, you must carefully disregard the values of those bits. It is possible to output an assembler instruction and then go on to output or compute more of them, using the sub- routine output_asm_insn. This receives two arguments: a template-string and a vector of operands. The vector may be operands, or it may be another array of rtx that you declare locally and initialize yourself. When an insn pattern has multiple alternatives in its constraints, often the appearance of the assembler code is determined mostly by which alternative was matched. When this is so, the C code can test the variable which_alternative, which is the ordinal number of the alter- native that was actually satisfied (0 for the first, 1 for the second alternative, etc.). For example, suppose there are two opcodes for storing zero, `clrreg' for registers and `clrmem' for memory loca- tions. Here is how a pattern could use which_alternative to choose between them: (define_insn "" [(set (match_operand:SI 0 "general_operand" "r,m") (const_int 0))] "" "* return (which_alternative == 0 ? \"clrreg %0\" : \"clrmem %0\"); ") The example above, where the assembler code to generate was solely determined by the alternative, could also have been specified as follows, having the output control string start with a `@': (define_insn "" [(set (match_operand:SI 0 "general_operand" "r,m") (const_int 0))] "" "@ clrreg %0 clrmem %0") 1.6. Operand Constraints Each match_operand in an instruction pattern can specify a constraint for the type of operands allowed. Con- straints can say whether an operand may be in a register, and which kinds of register; whether the operand can be a memory reference, and which kinds of address; whether the operand may be an immediate constant, and which possible values it may have. Constraints can also require two operands to match. 1.6.1. Simple Constraints The simplest kind of constraint is a string full of letters, each of which describes one kind of operand that is permitted. Here are the letters that are allowed: `m' A memory operand is allowed, with any kind of ad- dress that the machine supports in general. `o' A memory operand is allowed, but only if the ad- dress is offsettable. This means that adding a small integer (actually, the width in bytes of the operand, as determined by its machine mode) may be added to the address and the result is also a valid memory address. For example, an address which is constant is offsettable; so is an address that is the sum of a register and a constant (as long as a slightly larger constant is also within the range of address-offsets supported by the machine); but an autoincrement or autodecrement address is not offsettable. More complicated indirect/indexed addresses may or may not be offsettable depending on the other addressing modes that the machine supports. Note that in an output operand which can be matched by another operand, the constraint letter `o' is valid only when accompanied by both `<' (if the target machine has predecrement addressing) and `>' (if the target machine has preincrement addressing). `V' A memory operand that is not offsettable. In oth- er words, anything that would fit the `m' con- straint but not the `o' constraint. `<' A memory operand with autodecrement addressing (either predecrement or postdecrement) is allowed. `>' A memory operand with autoincrement addressing (either preincrement or postincrement) is allowed. `r' A register operand is allowed provided that it is in a general register. `d', `a', `f', ... Other letters can be defined in machine-dependent fashion to stand for particular classes of regis- ters. `d', `a' and `f' are defined on the 68000/68020 to stand for data, address and float- ing point registers. `i' An immediate integer operand (one with constant value) is allowed. This includes symbolic con- stants whose values will be known only at assembly time. `n' An immediate integer operand with a known numeric value is allowed. Many systems cannot support assembly-time constants for operands less than a word wide. Constraints for these operands should use `n' rather than `i'. `I', `J', `K', ... `P' Other letters in the range `I' through `P' may be defined in a machine-dependent fashion to permit immediate integer operands with explicit integer values in specified ranges. For example, on the 68000, `I' is defined to stand for the range of values 1 to 8. This is the range permitted as a shift count in the shift instructions. `E' An immediate floating operand (expression code const_double) is allowed, but only if the target floating point format is the same as that of the host machine (on which the compiler is running). `F' An immediate floating operand (expression code const_double) is allowed. `G', `H' `G' and `H' may be defined in a machine-dependent fashion to permit immediate floating operands in particular ranges of values. `s' An immediate integer operand whose value is not an explicit integer is allowed. This might appear strange; if an insn allows a constant operand with a value not known at compile time, it certainly must allow any known value. So why use `s' instead of `i'? Sometimes it allows better code to be generated. For example, on the 68000 in a fullword instruc- tion it is possible to use an immediate operand; but if the immediate value is between -128 and 127, better code results from loading the value into a register and using the register. This is because the load into the register can be done with a `moveq' instruction. We arrange for this to happen by defining the letter `K' to mean ``any integer outside the range -128 to 127'', and then specifying `Ks' in the operand constraints. `g' Any register, memory or immediate integer operand is allowed, except for registers that are not gen- eral registers. `X' Any operand whatsoever is allowed, even if it does not satisfy general_operand. This is normally used in the constraint of a match_scratch when certain alternatives will not actually require a scratch register. `0', `1', `2', ... `9' An operand that matches the specified operand number is allowed. If a digit is used together with letters within the same alternative, the di- git should come last. This is called a matching constraint and what it really means is that the assembler has only a sin- gle operand that fills two roles considered separate in the RTL insn. For example, an add insn has two input operands and one output operand in the RTL, but on most machines an add instruc- tion really has only two operands, one of them an input-output operand. Matching constraints work only in circumstances like that add insn. More precisely, the two operands that match must include one input-only operand and one output-only operand. Moreover, the digit must be a smaller number than the number of the operand that uses it in the constraint. For operands to match in a particular case usually means that they are identical-looking RTL expres- sions. But in a few special cases specific kinds of dissimilarity are allowed. For example, *x as an input operand will match *x++ as an output operand. For proper results in such cases, the output template should always use the output- operand's number when printing the operand. `p' An operand that is a valid memory address is al- lowed. This is for ``load address'' and ``push address'' instructions. `p' in the constraint must be accompanied by address_operand as the predicate in the match_operand. This predicate interprets the mode specified in the match_operand as the mode of the memory reference for which the address would be valid. `Q', `R', `S', ... `U' Letters in the range `Q' through `U' may be de- fined in a machine-dependent fashion to stand for arbitrary operand types. The machine description macro EXTRA_CONSTRAINT is passed the operand as its first argument and the constraint letter as its second operand. A typical use for this would be to distinguish certain types of memory references that affect other insn operands. Do not define these constraint letters to accept register references (reg); the reload pass does not expect this and would not handle it properly. In order to have valid assembler code, each operand must satisfy its constraint. But a failure to do so does not prevent the pattern from applying to an insn. Instead, it directs the compiler to modify the code so that the con- straint will be satisfied. Usually this is done by copying an operand into a register. Contrast, therefore, the two instruction patterns that follow: (define_insn "" [(set (match_operand:SI 0 "general_operand" "r") (plus:SI (match_dup 0) (match_operand:SI 1 "general_operand" "r")))] "" "...") which has two operands, one of which must appear in two places, and (define_insn "" [(set (match_operand:SI 0 "general_operand" "r") (plus:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "r")))] "" "...") which has three operands, two of which are required by a constraint to be identical. If we are considering an insn of the form (insn n prev next (set (reg:SI 3) (plus:SI (reg:SI 6) (reg:SI 109))) ...) the first pattern would not apply at all, because this insn does not contain two identical subexpressions in the right place. The pattern would say, ``That does not look like an add instruction; try other patterns.'' The second pattern would say, ``Yes, that's an add instruction, but there is something wrong with it.'' It would direct the reload pass of the compiler to generate additional insns to make the constraint true. The results might look like this: (insn n2 prev n (set (reg:SI 3) (reg:SI 6)) ...) (insn n n2 next (set (reg:SI 3) (plus:SI (reg:SI 3) (reg:SI 109))) ...) It is up to you to make sure that each operand, in each pattern, has constraints that can handle any RTL expression that could be present for that operand. (When multiple alternatives are in use, each pattern must, for each possi- ble combination of operand expressions, have at least one alternative which can handle that combination of operands.) The constraints don't need to allow any possible operand--- when this is the case, they do not constrain---but they must at least point the way to reloading any possible operand so that it will fit. o+ If the constraint accepts whatever operands the predicate permits, there is no problem: reloading is never necessary for this operand. For example, an operand whose constraints permit everything except registers is safe provided its predicate rejects registers. An operand whose predicate accepts only constant values is safe provided its constraints include the letter `i'. If any possible constant value is accepted, then nothing less than `i' will do; if the predicate is more selective, then the con- straints may also be more selective. o+ Any operand expression can be reloaded by copying it into a register. So if an operand's con- straints allow some kind of register, it is cer- tain to be safe. It need not permit all classes of registers; the compiler knows how to copy a re- gister into another register of the proper class in order to make an instruction valid. o+ A nonoffsettable memory reference can be reloaded by copying the address into a register. So if the constraint uses the letter `o', all memory refer- ences are taken care of. o+ A constant operand can be reloaded by allocating space in memory to hold it as preinitialized data. Then the memory reference can be used in place of the constant. So if the constraint uses the letters `o' or `m', constant operands are not a problem. o+ If the constraint permits a constant and a pseudo register used in an insn was not allocated to a hard register and is equivalent to a constant, the register will be replaced with the constant. If the predicate does not permit a constant and the insn is re-recognized for some reason, the com- piler will crash. Thus the predicate must always recognize any objects allowed by the constraint. If the operand's predicate can recognize registers, but the constraint does not permit them, it can make the com- piler crash. When this operand happens to be a register, the reload pass will be stymied, because it does not know how to copy a register temporarily into memory. 1.6.2. Multiple Alternative Constraints Sometimes a single instruction has multiple alternative sets of possible operands. For example, on the 68000, a logical-or instruction can combine register or an immediate value into memory, or it can combine any kind of operand into a register; but it cannot combine one memory location into another. These constraints are represented as multiple alterna- tives. An alternative can be described by a series of letters for each operand. The overall constraint for an operand is made from the letters for this operand from the first alternative, a comma, the letters for this operand from the second alternative, a comma, and so on until the last alternative. Here is how it is done for fullword logical-or on the 68000: (define_insn "iorsi3" [(set (match_operand:SI 0 "general_operand" "=m,d") (ior:SI (match_operand:SI 1 "general_operand" "%0,0") (match_operand:SI 2 "general_operand" "dKs,dmKs")))] ...) The first alternative has `m' (memory) for operand 0, `0' for operand 1 (meaning it must match operand 0), and `dKs' for operand 2. The second alternative has `d' (data register) for operand 0, `0' for operand 1, and `dmKs' for operand 2. The `=' and `%' in the constraints apply to all the alternatives; their meaning is explained in the next section (see section Class Preferences). If all the operands fit any one alternative, the instruction is valid. Otherwise, for each alternative, the compiler counts how many instructions must be added to copy the operands so that that alternative applies. The alterna- tive requiring the least copying is chosen. If two alterna- tives need the same amount of copying, the one that comes first is chosen. These choices can be altered with the `?' and `!' characters: ? Disparage slightly the alternative that the `?' appears in, as a choice when no alternative ap- plies exactly. The compiler regards this alterna- tive as one unit more costly for each `?' that ap- pears in it. ! Disparage severely the alternative that the `!' appears in. This alternative can still be used if it fits without reloading, but if reloading is needed, some other alternative will be used. When an insn pattern has multiple alternatives in its constraints, often the appearance of the assembler code is determined mostly by which alternative was matched. When this is so, the C code for writing the assembler code can use the variable which_alternative, which is the ordinal number of the alternative that was actually satisfied (0 for the first, 1 for the second alternative, etc.). See section Output Statement. 1.6.3. Register Class Preferences The operand constraints have another function: they enable the compiler to decide which kind of hardware regis- ter a pseudo register is best allocated to. The compiler examines the constraints that apply to the insns that use the pseudo register, looking for the machine-dependent letters such as `d' and `a' that specify classes of regis- ters. The pseudo register is put in whichever class gets the most ``votes''. The constraint letters `g' and `r' also vote: they vote in favor of a general register. The machine description says which registers are considered general. Of course, on some machines all registers are equivalent, and no register classes are defined. Then none of this complexity is relevant. 1.6.4. Constraint Modifier Characters `=' Means that this operand is write-only for this in- struction: the previous value is discarded and re- placed by output data. `+' Means that this operand is both read and written by the instruction. When the compiler fixes up the operands to satisfy the constraints, it needs to know which operands are inputs to the instruction and which are out- puts from it. `=' identifies an output; `+' iden- tifies an operand that is both input and output; all other operands are assumed to be input only. `&' Means (in a particular alternative) that this operand is written before the instruction is fin- ished using the input operands. Therefore, this operand may not lie in a register that is used as an input operand or as part of any memory address. `&' applies only to the alternative in which it is written. In constraints with multiple alterna- tives, sometimes one alternative requires `&' while others do not. See, for example, the `movdf' insn of the 68000. `&' does not obviate the need to write `='. `%' Declares the instruction to be commutative for this operand and the following operand. This means that the compiler may interchange the two operands if that is the cheapest way to make all operands fit the constraints. This is often used in patterns for addition instructions that really have only two operands: the result must go in one of the arguments. Here for example, is how the 68000 halfword-add instruction is defined: (define_insn "addhi3" [(set (match_operand:HI 0 "general_operand" "=m,r") (plus:HI (match_operand:HI 1 "general_operand" "%0,0") (match_operand:HI 2 "general_operand" "di,g")))] ...) `#' Says that all following characters, up to the next comma, are to be ignored as a constraint. They are significant only for choosing regis- ter preferences. `*' Says that the following character should be ignored when choosing register preferences. `*' has no effect on the meaning of the con- straint as a constraint, and no effect on re- loading. Here is an example: the 68000 has an instruc- tion to sign-extend a halfword in a data re- gister, and can also sign-extend a value by copying it into an address register. While either kind of register is acceptable, the constraints on an address-register destination are less strict, so it is best if register al- location makes an address register its goal. Therefore, `*' is used so that the `d' con- straint letter (for data register) is ignored when computing register preferences. (define_insn "extendhisi2" [(set (match_operand:SI 0 "general_operand" "=*d,a") (sign_extend:SI (match_operand:HI 1 "general_operand" "0,g")))] ...) 1.6.5. Not Using Constraints Some machines are so clean that operand constraints are not required. For example, on the Vax, an operand valid in one context is valid in any other context. On such a machine, every operand constraint would be `g', excepting only operands of ``load address'' instructions which are written as if they referred to a memory location's contents but actual refer to its address. They would have constraint `p'. For such machines, instead of writing `g' and `p' for all the constraints, you can choose to write a description with empty constraints. Then you write `""' for the con- straint in every match_operand. Address operands are iden- tified by writing an address expression around the match_operand, not by their constraints. When the machine description has just empty con- straints, certain parts of compilation are skipped, making the compiler faster. However, few machines actually do not need constraints; all machine descriptions now in existence use constraints. 1.7. Standard Names for Patterns Used in Generation Here is a table of the instruction names that are mean- ingful in the RTL generation pass of the compiler. Giving one of these names to an instruction pattern tells the RTL generation pass that it can use the pattern in to accomplish a certain task. `movm' Here m stands for a two-letter machine mode name, in lower case. This instruction pattern moves data with that machine mode from operand 1 to operand 0. For example, `movsi' moves full-word data. If operand 0 is a subreg with mode m of a register whose own mode is wider than m, the effect of this instruction is to store the specified value in the part of the register that corresponds to mode m. The effect on the rest of the register is unde- fined. This class of patterns is special in several ways. First of all, each of these names must be defined, because there is no other way to copy a datum from one place to another. Second, these patterns are not used solely in the RTL generation pass. Even the reload pass can generate move insns to copy values from stack slots into temporary registers. When it does so, one of the operands is a hard register and the other is an operand that can need to be reloaded into a register. Therefore, when given such a pair of operands, the pattern must generate RTL which needs no reloading and needs no temporary registers---no registers other than the operands. For example, if you sup- port the pattern with a define_expand, then in such a case the define_expand mustn't call force_reg or any other such function which might generate new pseudo registers. This requirement exists even for subword modes on a RISC machine where fetching those modes from memory normally requires several insns and some temporary registers. Look in `spur.md' to see how the requirement can be satisfied. During reload a memory reference with an invalid address may be passed as an operand. Such an ad- dress will be replaced with a valid address later in the reload pass. In this case, nothing may be done with the address except to use it as it stands. If it is copied, it will not be replaced with a valid address. No attempt should be made to make such an address into a valid address and no routine (such as change_address) that will do so may be called. Note that general_operand will fail when applied to such an address. The global variable reload_in_progress (which must be explicitly declared if required) can be used to determine whether such special handling is re- quired. The variety of operands that have reloads depends on the rest of the machine description, but typi- cally on a RISC machine these can only be pseudo registers that did not get hard registers, while on other machines explicit memory references will get optional reloads. If a scratch register is required to move an ob- ject to or from memory, it can be allocated using gen_reg_rtx prior to reload. But this is impossi- ble during and after reload. If there are cases needing scratch registers after reload, you must define SECONDARY_INPUT_RELOAD_CLASS and/or SECONDARY_OUTPUT_RELOAD_CLASS to detect them, and provide patterns `reload_inm' or `reload_outm' to handle them. See section Register Classes. The constraints on a `movem' must permit moving any hard register to any other hard register pro- vided that HARD_REGNO_MODE_OK permits mode m in both registers and REGISTER_MOVE_COST applied to their classes returns a value of 2. It is obligatory to support floating point `movem' instructions into and out of any registers that can hold fixed point values, because unions and structures (which have modes SImode or DImode) can be in those registers and they may have floating point members. There may also be a need to support fixed point `movem' instructions in and out of floating point registers. Unfortunately, I have forgotten why this was so, and I don't know whether it is still true. If HARD_REGNO_MODE_OK rejects fixed point values in floating point registers, then the con- straints of the fixed point `movem' instructions must be designed to avoid ever trying to reload into a floating point register. `reload_inm' `reload_outm' Like `movm', but used when a scratch register is required to move between operand 0 and operand 1. Operand 2 describes the scratch register. See the discussion of the SECONDARY_RELOAD_CLASS macro in see section Register Classes. `movstrictm' Like `movm' except that if operand 0 is a subreg with mode m of a register whose natural mode is wider, the `movstrictm' instruction is guaranteed not to alter any of the register except the part which belongs to mode m. `addm3' Add operand 2 and operand 1, storing the result in operand 0. All operands must have mode m. This can be used even on two-address machines, by means of constraints requiring operands 1 and 0 to be the same location. `subm3', `mulm3' `divm3', `udivm3', `modm3', `umodm3' `sminm3', `smaxm3', `uminm3', `umaxm3' `andm3', `iorm3', `xorm3' Similar, for other arithmetic operations. `mulhisi3' Multiply operands 1 and 2, which have mode HImode, and store a SImode product in operand 0. `mulqihi3', `mulsidi3' Similar widening-multiplication instructions of other widths. `umulqihi3', `umulhisi3', `umulsidi3' Similar widening-multiplication instructions that do unsigned multiplication. `divmodm4' Signed division that produces both a quotient and a remainder. Operand 1 is divided by operand 2 to produce a quotient stored in operand 0 and a remainder stored in operand 3. For machines with an instruction that produces both a quotient and a remainder, provide a pattern for `divmodm4' but do not provide patterns for `divm3' and `modm3'. This allows optimization in the relatively common case when both the quotient and remainder are computed. If an instruction that just produces a quotient or just a remainder exists and is more efficient than the instruction that produces both, write the out- put routine of `divmodm4' to call find_reg_note and look for a REG_UNUSED note on the quotient or remainder and generate the appropriate instruc- tion. `udivmodm4' Similar, but does unsigned division. `ashlm3' Arithmetic-shift operand 1 left by a number of bits specified by operand 2, and store the result in operand 0. Operand 2 has mode SImode, not mode m. `ashrm3', `lshlm3', `lshrm3', `rotlm3', `rotrm3' Other shift and rotate instructions. Logical and arithmetic left shift are the same. Machines that do not allow negative shift counts often have only one instruction for shifting left. On such machines, you should define a pattern named `ashlm3' and leave `lshlm3' undefined. `negm2' Negate operand 1 and store the result in operand 0. `absm2' Store the absolute value of operand 1 into operand 0. `sqrtm2' Store the square root of operand 1 into operand 0. `ffsm2' Store into operand 0 one plus the index of the least significant 1-bit of operand 1. If operand 1 is zero, store zero. m is the mode of operand 0; operand 1's mode is specified by the instruc- tion pattern, and the compiler will convert the operand to that mode before generating the in- struction. `one_cmplm2' Store the bitwise-complement of operand 1 into operand 0. `cmpm' Compare operand 0 and operand 1, and set the con- dition codes. The RTL pattern should look like this: (set (cc0) (compare (match_operand:m 0 ...) (match_operand:m 1 ...))) `tstm' Compare operand 0 against zero, and set the condition codes. The RTL pattern should look like this: (set (cc0) (match_operand:m 0 ...)) `tstm' patterns should not be defined for machines that do not use (cc0). Doing so would confuse the optimizer since it would no longer be clear which set operations were com- parisons. The `cmpm' patterns should be used instead. `movstrm' Block move instruction. The addresses of the destination and source strings are the first two operands, and both are in mode Pmode. The number of bytes to move is the third operand, in mode m. The fourth operand is the known shared align- ment of the source and destination, in the form of a const_int rtx. Thus, if the com- piler knows that both source and destination are word-aligned, it may provide the value 4 for this operand. These patterns need not give special con- sideration to the possibility that the source and destination strings might overlap. `cmpstrm' Block compare instruction, with five operands. Operand 0 is the output; it has mode m. The remaining four operands are like the operands of `movstrm'. The two memory blocks specified are compared byte by byte in lexicographic order. The effect of the instruction is to store a value in operand 0 whose sign indi- cates the result of the comparison. `floatmn2' Convert signed integer operand 1 (valid for fixed point mode m) to floating point mode n and store in operand 0 (which has mode n). `floatunsmn2' Convert unsigned integer operand 1 (valid for fixed point mode m) to floating point mode n and store in operand 0 (which has mode n). `fixmn2' Convert operand 1 (valid for floating point mode m) to fixed point mode n as a signed number and store in operand 0 (which has mode n). This instruction's result is defined only when the value of operand 1 is an integer. `fixunsmn2' Convert operand 1 (valid for floating point mode m) to fixed point mode n as an unsigned number and store in operand 0 (which has mode n). This instruction's result is defined only when the value of operand 1 is an integer. `ftruncm2' Convert operand 1 (valid for floating point mode m) to an integer value, still represented in floating point mode m, and store it in operand 0 (valid for floating point mode m). `fix_truncmn2' Like `fixmn2' but works for any floating point value of mode m by converting the value to an integer. `fixuns_truncmn2' Like `fixunsmn2' but works for any floating point value of mode m by converting the value to an integer. `truncmn' Truncate operand 1 (valid for mode m) to mode n and store in operand 0 (which has mode n). Both modes must be fixed point or both float- ing point. `extendmn' Sign-extend operand 1 (valid for mode m) to mode n and store in operand 0 (which has mode n). Both modes must be fixed point or both floating point. `zero_extendmn' Zero-extend operand 1 (valid for mode m) to mode n and store in operand 0 (which has mode n). Both modes must be fixed point. `extv' Extract a bit field from operand 1 (a register or memory operand), where operand 2 specifies the width in bits and operand 3 the starting bit, and store it in operand 0. Operand 0 must have mode word_mode. Operand 1 may have mode byte_mode or word_mode; often word_mode is allowed only for registers. Operands 2 and 3 must be valid for word_mode. The RTL generation pass generates this in- struction only with constants for operands 2 and 3. The bit-field value is sign-extended to a full word integer before it is stored in operand 0. `extzv' Like `extv' except that the bit-field value is zero-extended. `insv' Store operand 3 (which must be valid for word_mode) into a bit field in operand 0, where operand 1 specifies the width in bits and operand 2 the starting bit. Operand 0 may have mode byte_mode or word_mode; often word_mode is allowed only for registers. Operands 1 and 2 must be valid for word_mode. The RTL generation pass generates this in- struction only with constants for operands 1 and 2. `scond' Store zero or nonzero in the operand according to the condition codes. Value stored is nonzero iff the condition cond is true. cond is the name of a comparison operation expres- sion code, such as eq, lt or leu. You specify the mode that the operand must have when you write the match_operand expres- sion. The compiler automatically sees which mode you have used and supplies an operand of that mode. The value stored for a true condition must have 1 as its low bit, or else must be nega- tive. Otherwise the instruction is not suit- able and you should omit it from the machine description. You describe to the compiler ex- actly which value is stored by defining the macro STORE_FLAG_VALUE (see section Misc). If a description cannot be found that can be used for all the `scond' patterns, you should omit those operations from the machine description. These operations may fail, but should do so only in relatively uncommon cases; if they would fail for common cases involving integer comparisons, it is best to omit these pat- terns. If these operations are omitted, the compiler will usually generate code that copies the constant one to the target and branches around an assignment of zero to the target. If this code is more efficient than the potential in- structions used for the `scond' pattern fol- lowed by those required to convert the result into a 1 or a zero in SImode, you should omit the `scond' operations from the machine description. `bcond' Conditional branch instruction. Operand 0 is a label_ref that refers to the label to jump to. Jump if the condition codes meet condi- tion cond. Some machines do not follow the model assumed here where a comparison instruction is fol- lowed by a conditional branch instruction. In that case, the `cmpm' (and `tstm') patterns should simply store the operands away and gen- erate all the required insns in a define_expand (see section Expander Defini- tions) for the conditional branch operations. All calls to expand `vcond' patterns are im- mediately preceded by calls to expand either a `cmpm' pattern or a `tstm' pattern. Machines that use a pseudo register for the condition code value, or where the mode used for the comparison depends on the condition being tested, should also use the above mechanism. See section Jump Patterns The above discussion also applies to `scond' patterns. `call' Subroutine call instruction returning no value. Operand 0 is the function to call; operand 1 is the number of bytes of arguments pushed (in mode SImode, except it is normally a const_int); operand 2 is the number of re- gisters used as operands. On most machines, operand 2 is not actually stored into the RTL pattern. It is supplied for the sake of some RISC machines which need to put this information into the assembler code; they can put it in the RTL instead of operand 1. Operand 0 should be a mem RTX whose address is the address of the function. Note, however, that this address can be a symbol_ref expres- sion even if it would not be a legitimate memory address on the target machine. If it is also not a valid argument for a call in- struction, the pattern for this operation should be a define_expand (see section Ex- pander Definitions) that places the address into a register and uses that register in the call instruction. `call_value' Subroutine call instruction returning a value. Operand 0 is the hard register in which the value is returned. There are three more operands, the same as the three operands of the `call' instruction (but with numbers in- creased by one). Subroutines that return BLKmode objects use the `call' insn. `call_pop', `call_value_pop' Similar to `call' and `call_value', except used if defined and if RETURN_POPS_ARGS is non-zero. They should emit a parallel that contains both the function call and a set to indicate the adjustment made to the frame pointer. For machines where RETURN_POPS_ARGS can be non-zero, the use of these patterns increases the number of functions for which the frame pointer can be eliminated, if desired. `return' Subroutine return instruction. This instruc- tion pattern name should be defined only if a single instruction can do all the work of re- turning from a function. Like the `movm' patterns, this pattern is also used after the RTL generation phase. In this case it is to support machines where multiple instructions are usually needed to return from a function, but some class of functions only requires one instruction to implement a re- turn. Normally, the applicable functions are those which do not need to save any registers or allocate stack space. For such machines, the condition specified in this pattern should only be true when reload_completed is non-zero and the function's epilogue would only be a single in- struction. For machines with register win- dows, the routine leaf_function_p may be used to determine if a register window push is re- quired. Machines that have conditional return instruc- tions should define patterns such as (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(cc0) (const_int 0)]) (return) (pc)))] "condition" "...") where condition would normally be the same condition specified on the named `return' pat- tern. `nop' No-op instruction. This instruction pattern name should always be defined to output a no- op in assembler code. (const_int 0) will do as an RTL pattern. `indirect_jump' An instruction to jump to an address which is operand zero. This pattern name is mandatory on all machines. `casesi' Instruction to jump through a dispatch table, including bounds checking. This instruction takes five operands: 1. The index to dispatch on, which has mode SImode. 2. The lower bound for indices in the table, an integer constant. 3. The total range of indices in the table---the largest index minus the smallest one (both inclusive). 4. A label that precedes the table itself. 5. A label to jump to if the index has a value outside the bounds. (If the machine- description macro CASE_DROPS_THROUGH is de- fined, then an out-of-bounds index drops through to the code following the jump table instead of jumping to this label. In that case, this label is not actually used by the `casesi' instruction, but it is always pro- vided as an operand.) The table is a addr_vec or addr_diff_vec inside of a jump_insn. The number of elements in the table is one plus the difference between the upper bound and the lower bound. `tablejump' Instruction to jump to a variable address. This is a low-level capability which can be used to im- plement a dispatch table when there is no `casesi' pattern. This pattern requires two operands: the address or offset, and a label which should immediately pre- cede the jump table. If the macro CASE_VECTOR_PC_RELATIVE is defined then the first operand is an offset which counts from the address of the table; otherwise, it is an absolute address to jump to. The `tablejump' insn is always the last insn be- fore the jump table it uses. Its assembler code normally has no need to use the second operand, but you should incorporate it in the RTL pattern so that the jump optimizer will not delete the table as unreachable code. 1.8. When the Order of Patterns Matters Sometimes an insn can match more than one instruction pattern. Then the pattern that appears first in the machine description is the one used. Therefore, more specific pat- terns (patterns that will match fewer things) and faster instructions (those that will produce better code when they do match) should usually go first in the description. In some cases the effect of ordering the patterns can be used to hide a pattern when it is not valid. For exam- ple, the 68000 has an instruction for converting a fullword to floating point and another for converting a byte to floating point. An instruction converting an integer to floating point could match either one. We put the pattern to convert the fullword first to make sure that one will be used rather than the other. (Otherwise a large integer might be generated as a single-byte immediate quantity, which would not work.) Instead of using this pattern order- ing it would be possible to make the pattern for convert-a- byte smart enough to deal properly with any constant value. 1.9. Interdependence of Patterns Every machine description must have a named pattern for each of the conditional branch names `bcond'. The recogni- tion template must always have the form (set (pc) (if_then_else (cond (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc))) In addition, every machine description must have an anonymous pattern for each of the possible reverse- conditional branches. Their templates look like (set (pc) (if_then_else (cond (cc0) (const_int 0)) (pc) (label_ref (match_operand 0 "" "")))) They are necessary because jump optimization can turn direct-conditional branches into reverse-conditional branches. It is often convenient to use the match_operator con- struct to reduce the number of patterns that must be speci- fied for branches. For example, (define_insn "" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(cc0) (const_int 0)]) (pc) (label_ref (match_operand 1 "" ""))))] "condition" "...") In some cases machines support instructions identical except for the machine mode of one or more operands. For example, there may be ``sign-extend halfword'' and ``sign- extend byte'' instructions whose patterns are (set (match_operand:SI 0 ...) (extend:SI (match_operand:HI 1 ...))) (set (match_operand:SI 0 ...) (extend:SI (match_operand:QI 1 ...))) Constant integers do not specify a machine mode, so an instruction to extend a constant value could match either pattern. The pattern it actually will match is the one that appears first in the file. For correct results, this must be the one for the widest possible mode (HImode, here). If the pattern matches the QImode instruction, the results will be incorrect if the constant value does not actually fit that mode. Such instructions to extend constants are rarely gen- erated because they are optimized away, but they do occa- sionally happen in nonoptimized compilations. If a constraint in a pattern allows a constant, the reload pass may replace a register with a constant permitted by the constraint in some cases. Similarly for memory references. You must ensure that the predicate permits all objects allowed by the constraints to prevent the compiler from crashing. Because of this substitution, you should not provide separate patterns for increment and decrement instructions. Instead, they should be generated from the same pattern that supports register-register add insns by examining the operands and generating the appropriate machine instruction. 1.10. Defining Jump Instruction Patterns For most machines, GNU CC assumes that the machine has a condition code. A comparison insn sets the condition code, recording the results of both signed and unsigned com- parison of the given operands. A separate branch insn tests the condition code and branches or not according its value. The branch insns come in distinct signed and unsigned fla- vors. Many common machines, such as the Vax, the 68000 and the 32000, work this way. Some machines have distinct signed and unsigned compare instructions, and only one set of conditional branch instructions. The easiest way to handle these machines is to treat them just like the others until the final stage where assembly code is written. At this time, when output- ting code for the compare instruction, peek ahead at the following branch using next_cc0_user (insn). (The variable insn refers to the insn being output, in the output-writing code in an instruction pattern.) If the RTL says that is an unsigned branch, output an unsigned compare; otherwise out- put a signed compare. When the branch itself is output, you can treat signed and unsigned branches identically. The reason you can do this is that GNU CC always gen- erates a pair of consecutive RTL insns, possibly separated by note insns, one to set the condition code and one to test it, and keeps the pair inviolate until the end. To go with this technique, you must define the machine-description macro NOTICE_UPDATE_CC to do CC_STATUS_INIT; in other words, no compare instruction is superfluous. Some machines have compare-and-branch instructions and no condition code. A similar technique works for them. When it is time to ``output'' a compare instruction, record its operands in two static variables. When outputting the branch-on-condition-code instruction that follows, actually output a compare-and-branch instruction that uses the remem- bered operands. It also works to define patterns for compare-and-branch instructions. In optimizing compilation, the pair of com- pare and branch instructions will be combined according to these patterns. But this does not happen if optimization is not requested. So you must use one of the solutions above in addition to any special patterns you define. In many RISC machines, most instructions do not affect the condition code and there may not even be a separate con- dition code register. On these machines, the restriction that the definition and use of the condition code be adja- cent insns is not necessary and can prevent important optim- izations. For example, on the IBM RS/6000, there is a delay for taken branches unless the condition code register is set three instructions earlier than the conditional branch. The instruction scheduler cannot perform this optimization if it is not permitted to separate the definition and use of the condition code register. On these machines, do not use (cc0), but instead use a register to represent the condition code. If there is a specific condition code register in the machine, use a hard register. If the condition code or comparison result can be placed in any general register, or if there are multiple condition registers, use a pseudo register. On some machines, the type of branch instruction gen- erated may depend on the way the condition code was pro- duced; for example, on the 68k and Sparc, setting the condi- tion code directly from an add or subtract instruction does not clear the overflow bit the way that a test instruction does, so a different branch instruction must be used for some conditional branches. For machines that use (cc0), the set and use of the condition code must be adjacent (separated only by note insns) allowing flags in cc_status to be used. (See section Condition Code.) Also, the com- parison and branch insns can be located from each other by using the functions prev_cc0_setter and next_cc0_user. However, this is not true on machines that do not use (cc0). On those machines, no assumptions can be made about the adjacency of the compare and branch insns and the above methods cannot be used. Instead, we use the machine mode of the condition code register to record different formats of the condition code register. Registers used to store the condition code value should have a mode that is in class MODE_CC. Normally, it will be CCmode. If additional modes are required (as for the add example mentioned above in the Sparc), define the macro EXTRA_CC_MODES to list the additional modes required (see section Condition Code). Also define EXTRA_CC_NAMES to list the names of those modes and SELECT_CC_MODE to choose a mode given an operand of a compare. If it is known during RTL generation that a different mode will be required (for example, if the machine has separate compare instructions for signed and unsigned quan- tities, like most IBM processors), they can be specified at that time. If the cases that require different modes would be made by instruction combination, the macro SELECT_CC_MODE deter- mines which machine mode should be used for the comparison result. The patterns should be written using that mode. To support the case of the add on the Sparc discussed above, we have the pattern (define_insn "" [(set (reg:CC_NOOV 0) (compare:CC_NOOV (plus:SI (match_operand:SI 0 "register_operand" "%r") (match_operand:SI 1 "arith_operand" "rI")) (const_int 0)))] "" "...") The SELECT_CC_MODE macro on the Sparc returns CC_NOOVmode for comparisons whose argument is a plus. 1.11. Canonicalization of Instructions There are often cases where multiple RTL expressions could represent an operation peformed by a single machine instruction. This situation is most commonly encountered with logical, branch, and multiply-accumulate instructions. In such cases, the compiler attempts to convert these multi- ple RTL expressions into a single canonical form to reduce the number of insn patterns required. In addition to algebraic simplifications, following canonicalizations are performed: o+ For commutative and comparison operators, a con- stant is always made the second operand. If a machine only supports a constant as the second operand, only patterns that match a constant in the second operand need be supplied. For these operators, if only one operand is a neg, not, mult, plus, or minus expression, it will be the first operand. o+ For the compare operator, a constant is always the second operand on machines where cc0 is used (see section Jump Patterns). On other machines, there are rare cases where the compiler might want to construct a compare with a constant as the first operand. However, these cases are not common enough for it to be worthwhile to provide a pat- tern matching a constant as the first operand un- less the machine actually has such an instruction. An operand of neg, not, mult, plus, or minus is made the first operand under the same conditions as above. o+ (minus x (const_int n)) is converted to (plus x (const_int -n)). o+ Within address computations (i.e., inside mem), a left shift is converted into the appropriate mul- tiplication by a power of two. De`Morgan's Law is used to move bitwise negation inside a bitwise logical-and or logical-or opera- tion. If this results in only one operand being a not expression, it will be the first one. A machine that has an instruction that performs a bitwise logical-and of one operand with the bit- wise negation of the other should specify the pat- tern for that instruction as (define_insn "" [(set (match_operand:m 0 ...) (and:m (not:m (match_operand:m 1 ...)) (match_operand:m 2 ...)))] "..." "...") Similarly, a pattern for a ``NAND'' instruction should be written (define_insn "" [(set (match_operand:m 0 ...) (ior:m (not:m (match_operand:m 1 ...)) (not:m (match_operand:m 2 ...))))] "..." "...") In both cases, it is not necessary to include patterns for the many logically equivalent RTL expressions. o+ The only possible RTL expressions involving both bitwise exclusive-or and bitwise negation are (xor:m x) y) and (not:m (xor:m x y)). o+ The sum of three items, one of which is a con- stant, will only appear in the form (plus:m (plus:m x y) constant) o+ On machines that do not use cc0, (compare x (const_int 0)) will be converted to x. o+ Equality comparisons of a group of bits (usu- ally a single bit) with zero will be written using zero_extract rather than the equivalent and or sign_extract operations. 1.12. Defining Machine-Specific Peephole Optimizers In addition to instruction patterns the `md' file may contain definitions of machine-specific peephole optimiza- tions. The combiner does not notice certain peephole optimiza- tions when the data flow in the program does not suggest that it should try them. For example, sometimes two con- secutive insns related in purpose can be combined even though the second one does not appear to use a register com- puted in the first one. A machine-specific peephole optim- izer can detect such opportunities. A definition looks like this: (define_peephole [insn-pattern-1 insn-pattern-2 ...] "condition" "template" "optional insn-attributes") The last string operand may be omitted if you are not using any machine-specific information in this machine descrip- tion. If present, it must obey the same rules as in a define_insn. In this skeleton, insn-pattern-1 and so on are patterns to match consecutive insns. The optimization applies to a sequence of insns when insn-pattern-1 matches the first one, insn-pattern-2 matches the next, and so on. Each of the insns matched by a peephole must also match a define_insn. Peepholes are checked only at the last stage just before code generation, and only optionally. There- fore, any insn which would match a peephole but no define_insn will cause a crash in code generation in an unoptimized compilation, or at various optimization stages. The operands of the insns are matched with match_operands, match_operator, and match_dup, as usual. What is not usual is that the operand numbers apply to all the insn patterns in the definition. So, you can check for identical operands in two insns by using match_operand in one insn and match_dup in the other. The operand constraints used in match_operand patterns do not have any direct effect on the applicability of the peephole, but they will be validated afterward, so make sure your constraints are general enough to apply whenever the peephole matches. If the peephole matches but the con- straints are not satisfied, the compiler will crash. It is safe to omit constraints in all the operands of the peephole; or you can write constraints which serve as a double-check on the criteria previously tested. Once a sequence of insns matches the patterns, the con- dition is checked. This is a C expression which makes the final decision whether to perform the optimization (we do so if the expression is nonzero). If condition is omitted (in other words, the string is empty) then the optimization is applied to every sequence of insns that matches the pat- terns. The defined peephole optimizations are applied after register allocation is complete. Therefore, the peephole definition can check which operands have ended up in which kinds of registers, just by looking at the operands. The way to refer to the operands in condition is to write operands[i] for operand number i (as matched by (match_operand i ...)). Use the variable insn to refer to the last of the insns being matched; use prev_nonnote_insn to find the preceding insns. When optimizing computations with intermediate results, you can use condition to match only when the intermediate results are not used elsewhere. Use the C expression dead_or_set_p (insn, op), where insn is the insn in which you expect the value to be used for the last time (from the value of insn, together with use of prev_nonnote_insn), and op is the intermediate value (from operands[i]). Applying the optimization means replacing the sequence of insns with one new insn. The template controls ultimate output of assembler code for this combined insn. It works exactly like the template of a define_insn. Operand numbers in this template are the same ones used in matching the ori- ginal sequence of insns. The result of a defined peephole optimizer does not need to match any of the insn patterns in the machine description; it does not even have an opportunity to match them. The peephole optimizer definition itself serves as the insn pattern to control how the insn is output. Defined peephole optimizers are run as assembler code is being output, so the insns they produce are never com- bined or rearranged in any way. Here is an example, taken from the 68000 machine description: (define_peephole [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) (set (match_operand:DF 0 "register_operand" "f") (match_operand:DF 1 "register_operand" "ad"))] "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" "* { rtx xoperands[2]; xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); #ifdef MOTOROLA output_asm_insn (\"move.l %1,(sp)\", xoperands); output_asm_insn (\"move.l %1,-(sp)\", operands); return \"fmove.d (sp)+,%0\"; #else output_asm_insn (\"movel %1,sp@\", xoperands); output_asm_insn (\"movel %1,sp@-\", operands); return \"fmoved sp@+,%0\"; #endif } ") The effect of this optimization is to change jbsr _foobar addql #4,sp movel d1,sp@- movel d0,sp@- fmoved sp@+,fp0 into jbsr _foobar movel d1,sp@ movel d0,sp@- fmoved sp@+,fp0 insn-pattern-1 and so on look almost like the second operand of define_insn. There is one important difference: the second operand of define_insn consists of one or more RTX's enclosed in square brackets. Usually, there is only one: then the same action can be written as an element of a define_peephole. But when there are multiple actions in a define_insn, they are implicitly enclosed in a parallel. Then you must explicitly write the parallel, and the square brackets within it, in the define_peephole. Thus, if an insn pattern looks like this, (define_insn "divmodsi4" [(set (match_operand:SI 0 "general_operand" "=d") (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dmsK"))) (set (match_operand:SI 3 "general_operand" "=d") (mod:SI (match_dup 1) (match_dup 2)))] "TARGET_68020" "divsl%.l %2,%3:%0") then the way to mention this insn in a peephole is as fol- lows: (define_peephole [... (parallel [(set (match_operand:SI 0 "general_operand" "=d") (div:SI (match_operand:SI 1 "general_operand" "0") (match_operand:SI 2 "general_operand" "dmsK"))) (set (match_operand:SI 3 "general_operand" "=d") (mod:SI (match_dup 1) (match_dup 2)))]) ...] ...) 1.13. Defining RTL Sequences for Code Generation On some target machines, some standard pattern names for RTL generation cannot be handled with single insn, but a sequence of RTL insns can represent them. For these target machines, you can write a define_expand to specify how to generate the sequence of RTL. A define_expand is an RTL expression that looks almost like a define_insn; but, unlike the latter, a define_expand is used only for RTL generation and it can produce more than one RTL insn. A define_expand RTX has four operands: o+ The name. Each define_expand must have a name, since the only use for it is to refer to it by name. o+ The RTL template. This is just like the RTL tem- plate for a define_peephole in that it is a vector of RTL expressions each being one insn. o+ The condition, a string containing a C expression. This expression is used to express how the availa- bility of this pattern depends on subclasses of target machine, selected by command-line options when GNU CC is run. This is just like the condi- tion of a define_insn that has a standard name. o+ The preparation statements, a string containing zero or more C statements which are to be executed before RTL code is generated from the RTL tem- plate. Usually these statements prepare temporary regis- ters for use as internal operands in the RTL tem- plate, but they can also generate RTL insns directly by calling routines such as emit_insn, etc. Any such insns precede the ones that come from the RTL template. Every RTL insn emitted by a define_expand must match some define_insn in the machine description. Otherwise, the compiler will crash when trying to generate code for the insn or trying to optimize it. The RTL template, in addition to controlling generation of RTL insns, also describes the operands that need to be specified when this pattern is used. In particular, it gives a predicate for each operand. A true operand, which needs to be specified in order to generate RTL from the pattern, should be described with a match_operand in its first occurrence in the RTL template. This enters information on the operand's predicate into the tables that record such things. GNU CC uses the information to preload the operand into a register if that is required for valid RTL code. If the operand is referred to more than once, subsequent references should use match_dup. The RTL template may also refer to internal ``operands'' which are temporary registers or labels used only within the sequence made by the define_expand. Inter- nal operands are substituted into the RTL template with match_dup, never with match_operand. The values of the internal operands are not passed in as arguments by the compiler when it requests use of this pattern. Instead, they are computed within the pattern, in the preparation statements. These statements compute the values and store them into the appropriate elements of operands so that match_dup can find them. There are two special macros defined for use in the preparation statements: DONE and FAIL. Use them with a fol- lowing semicolon, as a statement. DONE Use the DONE macro to end RTL generation for the pattern. The only RTL insns resulting from the pattern on this occasion will be those already em- itted by explicit calls to emit_insn within the preparation statements; the RTL template will not be generated. FAIL Make the pattern fail on this occasion. When a pattern fails, it means that the pattern was not truly available. The calling routines in the com- piler will try other strategies for code genera- tion using other patterns. Failure is currently supported only for binary (addition, multiplication, shifting, etc.) and bitfield (extv, extzv, and insv) operations. Here is an example, the definition of left-shift for the SPUR chip: (define_expand "ashlsi3" [(set (match_operand:SI 0 "register_operand" "") (ashift:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "nonmemory_operand" "")))] "" " { if (GET_CODE (operands[2]) != CONST_INT || (unsigned) INTVAL (operands[2]) > 3) FAIL; }") This example uses define_expand so that it can generate an RTL insn for shifting when the shift-count is in the sup- ported range of 0 to 3 but fail in other cases where machine insns aren't available. When it fails, the compiler tries another strategy using different patterns (such as, a library call). If the compiler were able to handle nontrivial condition-strings in patterns with names, then it would be possible to use a define_insn in that case. Here is another case (zero-extension on the 68000) which makes more use of the power of define_expand: (define_expand "zero_extendhisi2" [(set (match_operand:SI 0 "general_operand" "") (const_int 0)) (set (strict_low_part (subreg:HI (match_dup 0) 0)) (match_operand:HI 1 "general_operand" ""))] "" "operands[1] = make_safe_from (operands[1], operands[0]);") Here two RTL insns are generated, one to clear the entire output operand and the other to copy the input operand into its low half. This sequence is incorrect if the input operand refers to [the old value of] the output operand, so the preparation statement makes sure this isn't so. The function make_safe_from copies the operands[1] into a tem- porary register if it refers to operands[0]. It does this by emitting another RTL insn. Finally, a third example shows the use of an internal operand. Zero-extension on the SPUR chip is done by and-ing the result against a halfword mask. But this mask cannot be represented by a const_int because the constant value is too large to be legitimate on this machine. So it must be copied into a register with force_reg and then the register used in the and. (define_expand "zero_extendhisi2" [(set (match_operand:SI 0 "register_operand" "") (and:SI (subreg:SI (match_operand:HI 1 "register_operand" "") 0) (match_dup 2)))] "" "operands[2] = force_reg (SImode, gen_rtx (CONST_INT, VOIDmode, 65535)); ") Note: If the define_expand is used to serve a standard binary or unary arithmetic operation or a bitfield opera- tion, then the last insn it generates must not be a code_label, barrier or note. It must be an insn, jump_insn or call_insn. If you don't need a real insn at the end, emit an insn to copy the result of the operation into itself. Such an insn will generate no code, but it can avoid problems in the compiler. 1.14. Splitting Instructions into Multiple Instructions On machines that have instructions requiring delay slots (see section Delay Slots) or that have instructions whose output is not available for multiple cycles (see sec- tion Function Units), the compiler phases that optimize these cases need to be able to move insns into one-cycle delay slots. However, some insns may generate more than one machine instruction. These insns would be unable to be placed into a delay slot. It is often possible to write the single insn as a list of individual insns, each corresponding to one machine instruction. The disadvantage of doing so is that it will cause the compilation to be slower and require more space. If the resulting insns are too complex, it may also suppress some optimizations. The define_split definition tells the compiler how to split a complex insn into several simpler insns. This spil- ling will be performed if there is a reason to believe that it might improve instruction or delay slot scheduling. The definition looks like this: (define_split [insn-pattern] "condition" [new-insn-pattern-1 new-insn-pattern-2 ...] "preparation statements") insn-pattern is a pattern that needs to be split and condition is the final condition to be tested, as in a define_insn. Any insn matched by a define_split must also be matched by a define_insn in case it does not need to be split. When an insn matching insn-pattern and satisfying con- dition is found, it is replaced in the insn list with the insns given by new-insn-pattern-1, new-insn-pattern-2, etc. The preparation statements are similar to those speci- fied for define_expand (see section Expander Definitions) and are executed before the new RTL is generated to prepare for the generated code or emit some insns whose pattern is not fixed. As a simple case, consider the following example from the AMD 29000 machine description, which splits a sign_extend from HImode to SImode into a pair of shift insns: (define_split [(set (match_operand:SI 0 "gen_reg_operand" "") (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] "" [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 16))) (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 16)))] " { operands[1] = gen_lowpart (SImode, operands[1]); }") 1.15. Instruction Attributes In addition to describing the instruction supported by the target machine, the `md' file also defines a group of attributes and a set of values for each. Every generated insn is assigned a value for each attribute. One possible attribute would be the effect that the insn has on the machine's condition code. This attribute can then be used by NOTICE_UPDATE_CC to track the condition codes. 1.15.1. Defining Attributes and their Values The define_attr expression is used to define each attribute required by the target machine. It looks like: (define_attr name list-of-values default) name is a string specifying the name of the attribute being defined. list-of-values is either a string that specifies a comma-separated list of values that can be assigned to the attribute, or a null string to indicate that the attribute takes numeric values. default is an attribute expression that gives the value of this attribute for insns that match patterns whose defin- ition does not include an explicit value for this attribute. See section Attr Example, for more information on the han- dling of defaults. For each defined attribute, a number of definitions are written to the `insn-attr.h' file. For cases where an explicit set of values is specified for an attribute, the following are defined: o+ A `#define' is written for the symbol `HAVE_ATTR_name'. o+ An enumeral class is defined for `attr_name' with elements of the form `upper-name_upper-value' where the attribute name and value are first con- verted to upper case. o+ A function `get_attr_name' is defined that is passed an insn and returns the attribute value for that insn. For example, if the following is present in the `md' file: (define_attr "type" "branch,fp,load,store,arith" ...) the following lines will be written to the file `insn- attr.h'. #define HAVE_ATTR_type enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH}; extern enum attr_type get_attr_type (); If the attribute takes numeric values, no enum type will be defined and the function to obtain the attribute's value will return int. 1.15.2. Attribute Expressions RTL expressions used to define attributes use the codes described above plus a few specific to attribute definitions, to be discussed below. Attribute value expres- sions must have one of the following forms: (const_int i) The integer i specifies the value of a numeric at- tribute. i must be non-negative. The value of a numeric attribute can be specified either with a const_int or as an integer represented as a string in const_string, eq_attr (see below), and set_attr (see section Tagging Insns) expressions. (const_string value) The string value specifies a constant attribute value. If value is specified as `"*"', it means that the default value of the attribute is to be used for the insn containing this expression. `"*"' obviously cannot be used in the default ex- pression of a define_attr. If the attribute whose value is being specified is numeric, value must be a string containing a non- negative integer (normally const_int would be used in this case). Otherwise, it must contain one of the valid values for the attribute. (if_then_else test true-value false-value) test specifies an attribute test, whose format is defined below. The value of this expression is true-value if test is true, otherwise it is false-value. (cond [test1 value1 ...] default) The first operand of this expression is a vector containing an even number of expressions and con- sisting of pairs of test and value expressions. The value of the cond expression is that of the value corresponding to the first true test expres- sion. If none of the test expressions are true, the value of the cond expression is that of the default expression. test expressions can have one of the following forms: (const_int i) This test is true if i is non-zero and false oth- erwise. (not test) (ior test1 test2) (and test1 test2) These tests are true if the indicated logical function is true. (match_operand:m n pred constraints) This test is true if operand n of the insn whose attribute value is being determined has mode m (this part of the test is ignored if m is VOID- mode) and the function specified by the string pred returns a non-zero value when passed operand n and mode m (this part of the test is ignored if pred is the null string). The constraints operand is ignored and should be the null string. (le arith1 arith2) (leu arith1 arith2) (lt arith1 arith2) (ltu arith1 arith2) (gt arith1 arith2) (gtu arith1 arith2) (ge arith1 arith2) (geu arith1 arith2) (ne arith1 arith2) (eq arith1 arith2) These tests are true if the indicated comparison of the two arithmetic expressions is true. Arith- metic expressions are formed with plus, minus, mult, div, mod, abs, neg, and, ior, xor, not, lshift, ashift, lshiftrt, and ashiftrt expres- sions. const_int and symbol_ref are always valid terms (see section Insn Lengths,for additional forms). symbol_ref is a string denoting a C expression that yields an int when evaluated by the `get_attr_...' routine. It should normally be a global variable. (eq_attr name value) name is a string specifying the name of an attri- bute. value is a string that is either a valid value for attribute name, a comma-separated list of values, or `!' followed by a value or list. If value does not begin with a `!', this test is true if the value of the name attribute of the current insn is in the list specified by value. If value begins with a `!', this test is true if the attribute's value is not in the specified list. For example, (eq_attr "type" "load,store") is equivalent to (ior (eq_attr "type" "load") (eq_attr "type" "store")) If name specifies an attribute of `alterna- tive', it refers to the value of the compiler variable which_alternative (see section Out- put Statement) and the values must be small integers. For example, (eq_attr "alternative" "2,3") is equivalent to (ior (eq (symbol_ref "which_alternative") (const_int 2)) (eq (symbol_ref "which_alternative") (const_int 3))) Note that, for most attributes, an eq_attr test is simplified in cases where the value of the attribute being tested is known for all insns matching a particular pattern. This is by far the most common case. 1.15.3. Assigning Attribute Values to Insns The value assigned to an attribute of an insn is pri- marily determined by which pattern is matched by that insn (or which define_peephole generated it). Every define_insn and define_peephole can have an optional last argument to specify the values of attributes for matching insns. The value of any attribute not specified in a particular insn is set to the default value for that attribute, as specified in its define_attr. Extensive use of default values for attri- butes permits the specification of the values for only one or two attributes in the definition of most insn patterns, as seen in the example in the next section. The optional last argument of define_insn and define_peephole is a vector of expressions, each of which defines the value for a single attribute. The most general way of assigning an attribute's value is to use a set expression whose first operand is an attr expression giving the name of the attribute being set. The second operand of the set is an attribute expression (see section Expres- sions) giving the value of the attribute. When the attribute value depends on the `alternative' attribute (i.e., which is the applicable alternative in the constraint of the insn), the set_attr_alternative expression can can be used. It allows the specification of a vector of attribute expressions, one for each alternative. When the generality of arbitrary attribute expressions is not required, the simpler set_attr expression can be used, which allows specifying a string giving either a sin- gle attribute value or a list of attribute values, one for each alternative. The form of each of the above specifications is shown below. In each case, name is a string specifying the attri- bute to be set. (set_attr name value-string) value-string is either a string giving the desired attribute value, or a string containing a comma- separated list giving the values for succeeding alternatives. The number of elements must match the number of alternatives in the constraint of the insn pattern. Note that it may be useful to specify `*' for some alternative, in which case the attribute will as- sume its default value for insns matching that al- ternative. (set_attr_alternative name [value1 value2 ...]) Depending on the alternative of the insn, the value will be one of the specified values. This is a shorthand for using a cond with tests on the `alternative' attribute. (set (attr name) value) The first operand of this set must be the special RTL expression attr, whose sole operand is a string giving the name of the attribute being set. value is the value of the attribute. The following shows three different ways of represent- ing the same attribute value specification: (set_attr "type" "load,store,arith") (set_attr_alternative "type" [(const_string "load") (const_string "store") (const_string "arith")]) (set (attr "type") (cond [(eq_attr "alternative" "1") (const_string "load") (eq_attr "alternative" "2") (const_string "store")] (const_string "arith"))) The define_asm_attributes expression provides a mechan- ism to specify the attributes assigned to insns produced from an asm statement. It has the form: (define_asm_attributes [attr-sets]) where attr-sets is specified the same as for define_insn and define_peephole expressions. These values will typically be the ``worst case'' attribute values. For example, they might indicate that the condition code will be clobbered. A specification for a length attribute is handled spe- cially. To compute the length of an asm insn, the length specified in the define_asm_attributes expression is multi- plied by the number of machine instructions specified in the asm statement, determined by counting the number of semi- colons and newlines in the string. Therefore, the value of the length attribute specified in a define_asm_attributes should be the maximum possible length of a single machine instruction. 1.15.4. Example of Attribute Specifications The judicious use of defaulting is important in the efficient use of insn attributes. Typically, insns are divided into types and an attribute, customarily called type, is used to represent this value. This attribute is normally used only to define the default value for other attributes. An example will clarify this usage. Assume we have a RISC machine with a condition code and in which only full-word operations are performed in regis- ters. Let us assume that we can divide all insns into loads, stores, (integer) arithmetic operations, floating point operations, and branches. Here we will concern ourselves with determining the effect of an insn on the condition code and will limit our- selves to the following possible effects: The condition code can be set unpredictably (clobbered), not be changed, be set to agree with the results of the operation, or only changed if the item previously set into the condition code has been modified. Here is part of a sample `md' file for such a machine: (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) (define_attr "cc" "clobber,unchanged,set,change0" (cond [(eq_attr "type" "load") (const_string "change0") (eq_attr "type" "store,branch") (const_string "unchanged") (eq_attr "type" "arith") (if_then_else (match_operand:SI 0 "" "") (const_string "set") (const_string "clobber"))] (const_string "clobber"))) (define_insn "" [(set (match_operand:SI 0 "general_operand" "=r,r,m") (match_operand:SI 1 "general_operand" "r,m,r"))] "" "@ move %0,%1 load %0,%1 store %0,%1" [(set_attr "type" "arith,load,store")]) Note that we assume in the above example that arith- metic operations performed on quantities smaller than a machine word clobber the condition code since they will set the condition code to a value corresponding to the full-word result. 1.15.5. Computing the Length of an Insn For many machines, multiple types of branch instruc- tions are provided, each for different length branch dis- placements. In most cases, the assembler will choose the correct instruction to use. However, when the assembler cannot do so, GCC can when a special attribute, the `length' attribute, is defined. This attribute must be defined to have numeric values by specifying a null string in its define_attr. In the case of the `length' attribute, two additional forms of arithmetic terms are allowed in test expressions: (match_dup n) This refers to the address of operand n of the current insn, which must be a label_ref. (pc) This refers to the address of the current insn. It might have been more consistent with other usage to make this the address of the next insn but this would be confusing because the length of the current insn is to be computed. For normal insns, the length will be determined by value of the `length' attribute. In the case of addr_vec and addr_diff_vec insn patterns, the length will be computed as the number of vectors multiplied by the size of each vec- tor. The following macros can be used to refine the length computation: FIRST_INSN_ADDRESS When the length insn attribute is used, this macro specifies the value to be assigned to the address of the first insn in a function. If not speci- fied, 0 is used. ADJUST_INSN_LENGTH (insn, length) If defined, modifies the length assigned to in- struction insn as a function of the context in which it is used. length is an lvalue that con- tains the initially computed length of the insn and should be updated with the correct length of the insn. If updating is required, insn must not be a varying-length insn. This macro will normally not be required. A case in which it is required is the ROMP. On this machine, the size of an addr_vec insn must be in- creased by two to compensate for the fact that alignment may be required. The routine that returns the value of the length attri- bute, get_attr_value, can be used by the output routine to determine the form of the branch instruction to be written, as the example below illustrates. As an example of the specification of variable-length branches, consider the IBM 360. If we adopt the convention that a register will be set to the starting address of a function, we can jump to labels within 4K of the start using a four-byte instruction. Otherwise, we need a six-byte sequence to load the address from memory and then branch to it. On such a machine, a pattern for a branch instruction might be specified as follows: (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" "* { return (get_attr_length (insn) == 4 ? \"b %l0\" : \"l r15,=a(%l0); br r15\"); }" [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096)) (const_int 4) (const_int 6)))]) 1.15.6. Delay Slot Scheduling The insn attribute mechanism can be used to specify the requirements for delay slots, if any, on a target machine. An instruction is said to require a delay slot if some instructions that are physically after the instruction are executed as if they were located before it. Classic exam- ples are branch and call instructions, which often execute the following instruction before the branch or call is per- formed. On some machines, conditional branch instructions can optionally annul instructions in the delay slot. This means that the instruction will not be executed for certain branch outcomes. Both instructions that annul if the branch is true and instructions that annul if the branch is false are supported. Delay slot scheduling differs from instruction scheduling in that determining whether an instruction needs a delay slot is dependent only on the type of instruction being gen- erated, not on data flow between the instructions. See the next section for a discussion of data-dependent instruction scheduling. The requirement of an insn needing one or more delay slots is indicated via the define_delay expression. It has the following form: (define_delay test [delay-1 annul-true-1 annul-false-1 delay-2 annul-true-2 annul-false-2 ...]) test is an attribute test that indicates whether this define_delay applies to a particular insn. If so, the number of required delay slots is determined by the length of the vector specified as the second argument. An insn placed in delay slot n must satisfy attribute test delay-n. annul-true-n is an attribute test that specifies which insns may be annulled if the branch is true. Similarly, annul- false-n specifies which insns in the delay slot may be annulled if the branch is false. If annulling is not sup- ported for that delay slot, (nil) should be coded. For example, in the common case where branch and call insns require a single delay slot, which may contain any insn other than a branch or call, the following would be placed in the `md' file: (define_delay (eq_attr "type" "branch,call") [(eq_attr "type" "!branch,call") (nil) (nil)]) Multiple define_delay expressions may be specified. In this case, each such expression specifies different delay slot requirements and there must be no insn for which tests in two define_delay expressions are both true. For example, if we have a machine that requires one delay slot for branches but two for calls, no delay slot can contain a branch or call insn, and any valid insn in the delay slot for the branch can be annulled if the branch is true, we might represent this as follows: (define_delay (eq_attr "type" "branch") [(eq_attr "type" "!branch,call") (eq_attr "type" "!branch,call") (nil)]) (define_delay (eq_attr "type" "call") [(eq_attr "type" "!branch,call") (nil) (nil) (eq_attr "type" "!branch,call") (nil) (nil)]) 1.15.7. Specifying Function Units On most RISC machines, there are instructions whose results are not available for a specific number of cycles. Common cases are instructions that load data from memory. On many machines, a pipeline stall will result if the data is referenced too soon after the load instruction. In addition, many newer microprocessors have multiple function units, usually one for integer and one for floating point, and often will incur pipeline stalls when a result that is needed is not yet ready. The descriptions in this section allow the specifica- tion of how much time must elapse between the execution of an instruction and the time when its result is used. It also allows specification of when the execution of an instruction will delay execution of similar instructions due to function unit conflicts. For the purposes of the specifications in this section, a machine is divided into function units, each of which exe- cute a specific class of instructions. Function units that accept one instruction each cycle and allow a result to be used in the succeeding instruction (usually via forwarding) need not be specified. Classic RISC microprocessors will normally have a single function unit, which we can call `memory'. The newer ``superscalar'' processors will often have function units for floating point operations, usually at least a floating point adder and multiplier. Each usage of a function units by a class of insns is specified with a define_function_unit expression, which looks like this: (define_function_unit name multiplicity simultaneity test ready-delay busy-delay [conflict-list]) name is a string giving the name of the function unit. multiplicity is an integer specifying the number of identical units in the processor. If more than one unit is specified, they will be scheduled independently. Only truly independent units should be counted; a pipelined unit should be specified as a single unit. (The only common example of a machine that has multiple function units for a single instruction class that are truly independent and not pipe- lined are the two multiply and two increment units of the CDC 6600.) simultaneity specifies the maximum number of insns that can be executing in each instance of the function unit simultaneously or zero if the unit is pipelined and has no limit. All define_function_unit definitions referring to func- tion unit name must have the same name and values for multi- plicity and simultaneity. test is an attribute test that selects the insns we are describing in this definition. Note that an insn may use more than one function unit and a function unit may be specified in more than one define_function_unit. ready-delay is an integer that specifies the number of cycles after which the result of the instruction can be used without introducing any stalls. busy-delay is an integer that represents the default cost if an insn is scheduled for this unit while the unit is active with another insn. If simultaneity is zero, this specification is ignored. Otherwise, a zero value indicates that these insns execute on name in a fully pipelined fashion, even if simultaneity is non-zero. A non-zero value indicates that scheduling a new insn on this unit while another is active will incur a cost. A cost of two indi- cates a single cycle delay. For a normal non-pipelined function unit, busy-delay will be twice ready-delay. conflict-list is an optional list giving detailed con- flict costs for this unit. If specified, it is a list of condition test expressions which are applied to insns already executing in name. For each insn that is in the list, busy-delay will be used for the conflict cost, while a value of zero will be used for insns not in the list. Typical uses of this vector are where a floating point function unit can pipeline either single- or double- precision operations, but not both, or where a memory unit can pipeline loads, but not stores, etc. As an example, consider a classic RISC machine where the result of a load instruction is not available for two cycles (a single ``delay'' instruction is required) and where only one load instruction can be executed simultane- ously. This would be specified as: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 4) For the case of a floating point function unit that can pipeline either single or double precision, but not both, the following could be specified: (define_function_unit "fp" 1 1 (eq_attr "type" "sp_fp") 4 8 (eq_attr "type" "dp_fp")] (define_function_unit "fp" 1 1 (eq_attr "type" "dp_fp") 4 8 (eq_attr "type" "sp_fp")] Note: No code currently exists to avoid function unit conflicts, only data conflicts. Hence multiplicity, simul- taneity, busy-cost, and conflict-list are currently ignored. When such code is written, it is possible that the specifi- cations for these values may be changed. It has recently come to our attention that these specifications may not allow modeling of some of the newer ``superscalar'' proces- sors that have insns using multiple pipelined units. These insns will cause a potential conflict for the second unit used during their execution and there is no way of representing that conflict. We welcome any examples of how function unit conflicts work in such processors and sugges- tions for their representation.