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LE_APX_B.TXT
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1994-01-31
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133 lines
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APPENDIX B - EXAMPLE CIRCUIT
============================
Circuit file PHASER.LIN is a model of a voice-band audio phase shift
network for a Single Sideband Transmitter Exciter. Designed by Peter
Martinez, G3PLX, it appeared in the English magazine, RADIO COMMUNICATION,
December 1973, p. 852, in the Technical Topics column hosted by Pat Hawker,
G3VA. The circuit is intended to provide four outputs, each having 90
degree phase shift from one another. With each output fed into one of four
mixers, each mixer also fed with an R.F. carrier of appropriate phase,
combinations of mixer outputs should be able to generate either an upper
sideband, suppressed carrier signal or a lower sideband, suppressed carrier
signal. Amount of rejection of the unwanted sideband is inversely
proportional to the accuracy of the 90 degree phase differential.
Several attempts were made to "draw" this circuit using ASCII characters.
None seemed satisfactory, but the following may show it. Individual
numbers are nodes. Resistor strings in order R1x-R2x-R3x-R4x-R5x-R6x
connected horizontally in each row, the 'x' denoting row A, B, C, or D.
All resistors are 5.6 K. Capacitors are on the diagonal. Zero-phase input
signal is at nodes 1 and 8, 180-degree phase input signal is at nodes 15
and 22. Relative 90-degree outputs are at nodes 7, 14, 21, and 28. Each
input node has a 300 Ohm resistor to ground, each output node has a 10
Megohm resistor to ground.
1 2 3 4 5 6 7 - A row
\ \ \ \ \ \
C1 C2 C3 C4 C5 C6 - capacitor "AB" group
\ \ \ \ \ \
I 8 9 10 11 12 13 14 - B row
n \ \ \ \ \ \
p C1 C2 C3 C4 C5 C6 - capacitor "BC" group
u \ \ \ \ \ \
t 15 16 17 18 19 20 21 - C row
\ \ \ \ \ \
C1 C2 C3 C4 C5 C6 - capacitor "CD" group
\ \ \ \ \ \
22 23 24 25 26 27 28 - D row
\ \ \ \ \ \
C1 C2 C3 C4 C5 C6 - capacitor "DA" group
\| \| \| \| \| \|
(completed connections on row A)
This circuit is very calculation-intensive due to all the diagonal
connections. Using the Standard (non-coprocessor) version of LENA and
a 20 MHz 386SX computer, 140 frequencies took about 117 seconds for each
output node. With the Numeric coprocessor version, 140 frequencies were
solved in only 21 seconds! The solution at Node 7 is included as file
PHASER7.LNA in the program set. Comparing solutions at nodes 14, 21, and
28 shows that adjacent output phase is within quadrature by 2 degrees from
500 Hz to 5 KHz.
LENA Appendix B - Page 1 of 2
This is a special case for analysis-solution where _phase_ is the
important criterion. There is no easy way to output phase error between
nodes, other than by a tabulation or graphical equivalent at each node. It
is possible to add to the circuit, using transconductance-specified
dependent current sources, to see differences. Adding the following
branches to PHASER.CIR:
61 GMS 29 0 1.0000 mho Dep.Br.# 15, R7
62 GMS 29 0 1.0000 mho Dep.Br.# 22, R8
63 R-SUM1 29 0 1.0000 Ohm
64 GMS 30 0 1.0000 mho Dep.Br.# 29, R9
65 GMS 30 0 1.0000 mho Dep.Br.# 36, R10
66 R-SUM2 30 0 1.0000 Ohm
...creates a new Node 29 which has a "45 degree" phase (vector sum of
voltages at Nodes 7 and 14), and a new Node 30 which has a "225 degree"
phase (vector sum of voltages at Nodes 21 and 28). Two more GMSs and
another summing resistor, a new node (31), GMSs dependent on the
above-listed summing resistors, will show the vector addition of the "45"
and "225" phases...or vector subtraction if the node ordering is reversed
or transconductance made negative in the second added GMS.
There are many combinations of measurement-observation additions possible.
Dependent current sources allow a variety of no-disturbance monitoring.
Note: These "polyphase" networks have appeared in several papers
in the IEEE Circuits and Systems Transactions of the late seventies
and early eighties.
It is possible to re-arrange the node ordering versus connection points in
the circuit to slightly reduce solution time, but this is difficult with
more complex circuit arrangements. It is usually better to translate a
schematic to circuit list as it appears; this permits better understanding
of the written (versus schematic) versions of the same circuit at a later
time.
LENA Appendix B - Page 2 of 2
.1/31/94