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4waytraf.pds
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1987-08-26
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6KB
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175 lines
Title Traffic Light Controller
Pattern 4waytraf.pds
Revision 1A
Author Nick Schmitz
Company Monolithic Memories Inc.
Date OCT 9, 1986
Chip Traffic_Ctl PMS14R21
;1 2 3 4 5 6 7 8 9 10 11 12
CLK DCLK EWD WLD ELD NLD SLD NSD CO NC SDI GND
OE SDO REL REF RWL RWF RNL RNF RSL RSF MOD VCC
; Output Signal Names - Red, Yellow, Green Lights
;OE SDO REL REF RWL RWF RNL RNF RSL RSF MOD VCC
;OE SDO YEL YEF YWL YWF YNL YNF YSL YSF MOD VCC
;OE SDO GEL GEF GWL GWF GNL GNF GSL GSF MOD VCC
STATE MOORE_MACHINE
; STATE MEALY_MACHINE
POWER_UP := VCC -> ALL_REDS
; POWER_UP.OUTF := REL * REF * RWL * RWF * RNL * RNF * RSL * RSF
ALL_REDS := VCC -> S_NFG_SFG
; North & South Forward Signals
S_NFG_SFG := c_NSH -> S_NFY_SFY +-> S_NFG_SFG
S_NFY_SFY := c_ELO -> S_ELG_EFG + c_WLO -> S_WLG_WFG
+ c_EWL -> S_ELG_WLG +-> S_EFG_WFG
; East Left Turn Signals
S_ELG_EFG := c_ELC -> S_ELY_EFG +-> S_ELG_EFG
S_ELY_EFG := VCC -> S_EFG_WFG
; West Left Turn Signals
S_WLG_WFG := c_WLC -> S_WLY_WFG +-> S_WLG_WFG
S_WLY_WFG := VCC -> S_EFG_WFG
; East & West Left Turn Signals
S_ELG_WLG := c_ELO -> S_ELG_WLY + c_WLO -> S_ELY_WLG
+ c_EWC -> S_ELG_WLG +-> S_ELY_WLY
; West Left Turn Ends Early
S_ELG_WLY := VCC -> S_ELG_EFG
T_ELG_EFG := c_WLC -> S_ELY_EFG +-> S_ELG_EFG
T_ELY_EFG := VCC -> S_EFG_WFG
; East Left Turn Ends Early
S_ELY_WLG := VCC -> S_WLG_WFG
T_WLG_WFG := c_ELC -> S_WLY_WFG +-> S_WLG_WFG
T_WLY_WFG := VCC -> S_EFG_WFG
; Time out or No More Left Turns
S_ELY_WLY := VCC -> S_EFG_WFG
; East & West Forward Signals
S_EFG_WFG := c_EWH -> S_EFY_WFY +-> S_EFG_WFG
S_EFY_WFY := c_NLO -> S_NLG_NFG + c_SLO -> S_SLG_SFG
+ c_NSL -> S_NLG_SLG +-> S_NFG_SFG
; North Left Turn Signals
S_NLG_NFG := c_NLC -> S_NLY_NFG +-> S_NLG_NFG
S_NLY_NFG := VCC -> S_NFG_SFG
; South Left Turn Signals
S_SLG_SFG := c_SLC -> S_SLY_SFG +-> S_SLG_SFG
S_SLY_SFG := VCC -> S_NFG_SFG
; North & South Left Turn Signals
S_NLG_SLG := c_NLO -> S_NLG_SLY + c_SLO -> S_NLY_SLG
+ c_NSC -> S_NLG_SLG +-> S_NLY_SLY
; South Left Turn Ends Early
S_NLG_SLY := VCC -> S_NLG_NFG
T_NLG_NFG := c_SLC -> S_NLY_NFG +-> S_NLG_NFG
T_NLY_NFG := VCC -> S_NFG_SFG
; North Left Turn Ends Early
S_NLY_SLG := VCC -> S_SLG_SFG
T_SLG_SFG := c_NLC -> S_SLY_SFG +-> S_SLG_SFG
T_SLY_SFG := VCC -> S_NFG_SFG
; Time out or No More Left Turns
S_NLY_SLY := VCC -> S_NFG_SFG
; OUTPUT SIGNALS
ALL_REDS.OUTF := REL * REF * RWL * RWF * RNL * RNF * RSL * RSF
; North & South Forward Signals
S_NFG_SFG.OUTF := REL * REF * RWL * RWF * RNL * /RNF * RSL * /RSF
S_NFY_SFY.OUTF := REL * REF * RWL * RWF * RNL * /RNF * RSL * /RSF
; East Left Turn Signals
S_ELG_EFG.OUTF := /REL * /REF * RWL * RWF * RNL * RNF * RSL * RSF
S_ELY_EFG.OUTF := /REL * /REF * RWL * RWF * RNL * RNF * RSL * RSF
; West Left Turn Signals
S_WLG_WFG.OUTF := REL * REF * /RWL * /RWF * RNL * RNF * RSL * RSF
S_WLY_WFG.OUTF := REL * REF * /RWL * /RWF * RNL * RNF * RSL * RSF
; East & West Left Turn Signals
S_ELG_WLG.OUTF := /REL * REF * /RWL * RWF * RNL * RNF * RSL * RSF
; West Left Turn Ends Early
S_ELG_WLY.OUTF := /REL * REF * /RWL * RWF * RNL * RNF * RSL * RSF
T_ELG_EFG.OUTF := /REL * /REF * RWL * RWF * RNL * RNF * RSL * RSF
T_ELY_EFG.OUTF := /REL * /REF * RWL * RWF * RNL * RNF * RSL * RSF
; East Left Turn Ends Early
S_ELY_WLG.OUTF := /REL * REF * /RWL * RWF * RNL * RNF * RSL * RSF
T_WLG_WFG.OUTF := REL * REF * /RWL * /RWF * RNL * RNF * RSL * RSF
T_WLY_WFG.OUTF := REL * REF * /RWL * /RWF * RNL * RNF * RSL * RSF
; Time out or No More Left Turns
S_ELY_WLY.OUTF := /REL * REF * /RWL * RWF * RNL * RNF * RSL * RSF
; East & West Forward Signals
S_EFG_WFG.OUTF := REL * /REF * RWL * /RWF * RNL * RNF * RSL * RSF
S_EFY_WFY.OUTF := REL * /REF * RWL * /RWF * RNL * RNF * RSL * RSF
; North Left Turn Signals
S_NLG_NFG.OUTF := REL * REF * RWL * RWF * /RNL * /RNF * RSL * RSF
S_NLY_NFG.OUTF := REL * REF * RWL * RWF * /RNL * /RNF * RSL * RSF
; South Left Turn Signals
S_SLG_SFG.OUTF := REL * REF * RWL * RWF * RNL * RNF * /RSL * /RSF
S_SLY_SFG.OUTF := REL * REF * RWL * RWF * RNL * RNF * /RSL * /RSF
; North & South Left Turn Signals
S_NLG_SLG.OUTF := REL * REF * RWL * RWF * /RNL * RNF * /RSL * RSF
; South Left Turn Ends Early
S_NLG_SLY.OUTF := REL * REF * RWL * RWF * /RNL * RNF * /RSL * RSF
T_NLG_NFG.OUTF := REL * REF * RWL * RWF * /RNL * /RNF * RSL * RSF
T_NLY_NFG.OUTF := REL * REF * RWL * RWF * /RNL * /RNF * RSL * RSF
; North Left Turn Ends Early
S_NLY_SLG.OUTF := REL * REF * RWL * RWF * /RNL * RNF * /RSL * RSF
T_SLG_SFG.OUTF := REL * REF * RWL * RWF * RNL * RNF * /RSL * /RSF
T_SLY_SFG.OUTF := REL * REF * RWL * RWF * RNL * RNF * /RSL * /RSF
; Time out or No More Left Turns
S_NLY_SLY.OUTF := REL * REF * RWL * RWF * /RNL * RNF * /RSL * RSF
CONDITIONS
; East West Conditions
c_EWH = NSD * CO
c_ELO = ELD * /WLD
c_WLO = /ELD * WLD
c_EWL = ELD * WLD
c_ELC = /ELD + CO
c_WLC = /WLD + CO
c_EWC = ELD * WLD ;+ /CO
; North South Conditions
c_NSH = EWD * CO
c_NLO = NLD * /SLD
c_SLO = /NLD * SLD
c_NSL = NLD * SLD
c_NLC = /NLD + CO
c_SLC = /SLD + CO
c_NSC = NLD * SLD ;+ /CO
Equations
Simulation
trace_on
setf ewd
trace_off