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1987-08-26
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5KB
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239 lines
TITLE SYNC_PAL
PATTERN T1 FRAME SYNC PAL FOR T1 INTERFACE
REVISION P1.05
AUTHOR STEVE PATTERSON AND THERESA SHAFER
COMPANY
DATE 12/4/86
; This PAL decides whether the T1 Interface is in Frame Sync,
; provisional Sync, or Out of Sync. It controls the Frame Sync
; process.
CHIP SYNC PAL20R4
;PINS
;1 2 3 4 5 6 7 8
T1_CKB RSTB NO_T1CB DATA FPD1B FPD2B BC2 BC1
;9 10 11 12
BC0 SOF NC GND
;13 14 15 16 17 18 19 20
OEB NC NO_FRM SUNK LDB Q0 Q1 Q2
;21 22 23 24
BYT_CK BIT NC VCC
;INPUTS:T1_CKB ACTIVE LOW EXTERNAL T1 CLOCK
; RSTB ACTIVE LOW MASTER RESET
; NO_T1CB NO T1 SIGNAL ACTIVE LOW INPUT
; FPD(1-2)B ACTIVE LOW FRAME PATTERN DETECT INPUTS
; BC(2-0) 193 COUNTER 3 LSBs INPUTS USED FOR BYT_CK
; SOF LAST KNOWN START OF FRAME
; DATA INPUT DATA STREAM
; OEB ACTIVE LOW OUTPUT ENABLE INPUT
;OUTPUTS:BIT NEXT T1 BIT STREAM
; LDB ACTIVE LOW LOAD COUNTER SIGNAL
; SUNK IN SYNC STATE AND NO FRAME BIT ERROR
; NO_FRM FRAME LOST, IN SEARCH STATE
; Q(2-0) STATE VARIABLES
; BYT_CK 8-BIT CHANNEL SAMPLE CLOCK
EQUATIONS
;STATE MACHINE OUTPUTS AND STATE VARIABLES
/BIT = DATA * /Q2 * /Q1 * Q0 * FPD1B * SOF
+ DATA * /Q2 * /Q1 * Q0 * FPD2B * SOF
+ /DATA * /SOF
+ /DATA * /FPD1B * /FPD2B
+ /DATA * Q2
+ /DATA * Q1
+ /DATA * /Q0
/LDB := Q2 * Q1 * Q0 * /FPD1B * /FPD2B + SOF
/SUNK = /Q2 * /Q1 * /Q0 + Q1 * Q0 ; IN FRAME SYNC
/NO_FRM = /Q2 + /Q1 + /Q0 ; SEARCHING FOR FRAME SYNC
; USING THE FOLLOWING STATE ASSIGNMENTS
; A = 001 IN SYNC STATE
; B = 010 SINGLE FRAME BIT ERROR STATE
; C = 110
; D = 100
; E = 101
; F = 111 SEARCHING STATE
; G = 011 SEARCHING STATE
; H = 000 UNUSED STATE - GOES TO F
/Q2 := /FPD2B * /FPD1B * Q1 * Q0 * RSTB * NO_T1CB
+ /Q2 * Q1 * /SOF * RSTB * NO_T1CB
+ /Q2 * /Q1 * Q0 * RSTB * NO_T1CB
+ /FPD2B * /FPD1B * Q0 * SOF * RSTB * NO_T1CB
/Q1 := /Q1 * Q0 * /SOF * RSTB * NO_T1CB
+ Q2 * /Q1 * /SOF * RSTB * NO_T1CB
+ /FPD2B * /FPD1B * Q2 * /Q0 * SOF * RSTB * NO_T1CB
+ /FPD2B * /FPD1B * Q2 * /Q1 * RSTB * NO_T1CB
+ /FPD2B * /FPD1B * /Q2 * Q0 * SOF * RSTB * NO_T1CB
/Q0 := Q1 * /Q0 * /SOF * RSTB * NO_T1CB
+ Q2 * /Q0 * /SOF * RSTB * NO_T1CB
+ FPD1B * /Q2 * /Q1 * Q0 * SOF * RSTB * NO_T1CB
+ FPD2B * /Q2 * /Q1 * Q0 * SOF * RSTB * NO_T1CB
+ /FPD2B * /FPD1B * Q1 * /Q0 * RSTB * NO_T1CB
; BYTE CLOCK
/BYT_CK = BC2 + BC1 + BC0
; ............................................................
; ............................................................
SIMULATION
TRACE_ON T1_CKB RSTB NO_T1CB DATA FPD1B FPD2B SOF
Q2 Q1 Q0 BIT LDB SUNK NO_FRM
BYT_CK BC2 BC1 BC0
SETF /OEB ; ENABLE OUTPUT
/RSTB /NO_T1CB ; RESET REGISTERS
CLOCKF T1_CKB
SETF RSTB NO_T1CB ; RESET REGISTERS
DATA
/BC2 /BC1 /BC0
FPD1B FPD2B SOF
CLOCKF T1_CKB
SETF FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B FPD2B SOF
CLOCKF T1_CKB
SETF FPD1B /FPD2B /SOF
CLOCKF T1_CKB
SETF /FPD1B FPD2B /SOF
CLOCKF T1_CKB
SETF FPD1B FPD2B /SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF FPD1B FPD2B SOF
/BC2 /BC1 BC0
CLOCKF T1_CKB
SETF /FPD1B /FPD2B
/BC2 BC1 /BC0
CLOCKF T1_CKB
SETF /SOF
/BC2 BC1 BC0
CLOCKF T1_CKB
SETF FPD1B /FPD2B SOF
BC2 /BC1 /BC0
CLOCKF T1_CKB
SETF /FPD1B /FPD2B /SOF
BC2 /BC1 BC0
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
BC2 BC1 /BC0
CLOCKF T1_CKB
SETF /SOF
BC2 BC1 BC0
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
/BC2 /BC1 /BC0
CLOCKF T1_CKB
SETF /FPD1B FPD2B SOF
CLOCKF T1_CKB
SETF FPD1B FPD2B /SOF
/BC2 /BC1 BC0
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B /SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
FOR I:=1 TO 1 DO BEGIN
CLOCKF T1_CKB
END
SETF FPD1B SOF
CLOCKF
SETF /FPD1B /FPD2B /SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
FOR I:=1 TO 2 DO BEGIN
CLOCKF T1_CKB
END
SETF FPD1B /SOF
CLOCKF
SETF FPD1B SOF
CLOCKF
SETF /FPD1B /FPD2B /SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
FOR I:=1 TO 3 DO BEGIN
CLOCKF T1_CKB
END
SETF FPD1B SOF
CLOCKF
SETF /DATA ; INVERT DATA
SETF /FPD1B /FPD2B /SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B FPD2B SOF
CLOCKF T1_CKB
SETF /FPD1B /FPD2B SOF
FOR I:=1 TO 4 DO BEGIN
CLOCKF T1_CKB
END
SETF FPD1B SOF
CLOCKF
TRACE_OFF