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1987-08-26
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6KB
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156 lines
TITLE MANCHESTER ENCODER.
PATTERN 04.
REVISION 01.
AUTHOR CHRIS JAY.
COMPANY MMI SANTA CLARA, CA.
DATE 17 JULY 1986.
;
;THE PAL22CV10 HAS BEEN DESIGNED TO FUNCTION AS A MANCHESTER
;ENCODER CIRCUIT. THE BINARY DATA INPUT WILL DETERMINE WHETHER
;THE TRANSMISSION SIGNAL SHOULD BE IN PHASE WITH A CLOCK
;REFERENCE OR SHIFTED BY 180 DEGREES FROM THAT REFERENCE.
;THE CHARACTERSTIC OF A MANCHESTER ENCODED SIGNAL IS A
;CHANGE OF PHASE FOR EACH TRANSITION OF THE DATA INPUT.
;ASSUMING THAT 'X' IS THE PHASE OF THE CARRIER THAT ENCODES
;A LOGIC LOW INPUT, WHEN THE INPUT DATA TRANSITIONS
;TO A LOGIC HIGH THE PHASE OF THE CARRIER WILL BE SHIFTED
;TO 'X + 180'. IT WILL CHANGE BACK TO 'X' ONLY WHEN THE
;DATA INPUT TRANSITIONS FROM A LOGIC HIGH TO A LOGIC LOW.
;THE KEY FEATURES OF THE ENCODED SIGNAL ARE;
;
; 1. DATA AND CLOCK FREQUENCY INFORMATION IS
; CONTAINED IN THE ENCODED SIGNAL. CLOCK
; INFORMATION MAY BE EXTRACTED BY USING A
; PHASE LOCKED LOOP IN THE RECEIVER.
; 2. NO D.C. COMPONENT IS CONTAINED IN THE
; PHASE ENCODED SIGNAL.
;
;THE APPLICATIONS OF A PHASE ENCODED SIGNALS CAN BE IN SHORT
;COMMUNICATIONS LINKS; SUCH AS ETHERNET,OR INFRA RED TRANS-
;-MISSIONS OR IN STORAGE ON SOME MAGNETIC MEDIA.
;
;THERE ARE EIGHT DATA INPUTS D0 TO D7, DATA PRESENT ON THESE
;PINS WILL BE ENCODED INTO A BI-PHASE SIGNAL AT THE OUTPUT
;QX, WHEN THE SER(SERIAL) INPUT DATA PIN IS CONFIGURED
;TO A LOGIC ZERO. TO CONVERT A SERIAL DATA STREAM OF LOGIC
;ONE'S AND ZERO'S INTO A PHASE ENCODED SIGNAL THE SER INPUT
;INPUT IS TIED HIGH, AND THE DATA IS APPLIED TO THE D0 INPUT
;OF THE PAL DEVICE. A CLOCK INPUT OF 16 TIMES THE DATA RATE
;IS REQUIRED FOR THE PARALLEL OR SERIAL ENCODING OF THAT
;DATA, SO THE DESIGN MAY BE USED WITH MANY POPULAR UART LSI
;CIRCUITS. THERE IS ONE HANDSHAKE OUTPUT FROM THE DEVICE,
;RDY, THIS SIGNAL GOES HIGH WHEN THE NEXT DATA BYTE, OR BIT
;IS REQUIRED TO BE SET UP AT THE INPUT.
;
CHIP BIPHASE PAL22V10
;
;PIN 1 2 3 4 5 6
CLK /RST D0 D1 D2 D3
;PIN 7 8 9 10 11 12
D4 D5 D6 D7 NC GND
;PIN 13 14 15 16 17 18
SER RDY /DTST RC RB RX
;PIN 19 20 21 22 23 23
RA R3 R2 R1 R0 VCC
GLOBAL ;GLOBAL TERM
;ENABLES RESET.
;STRING DECLARATIONS.
STRING S0 '/RA*/RB*/RC' ;ENCODE STATE 0
STRING S1 'RA*/RB*/RC' ;ENCODE STATE 1
STRING S2 '/RA*RB*/RC' ;ENCODE STATE 2
STRING S3 'RA*RB*/RC' ;ENCODE STATE 3
STRING S4 '/RA*/RB*RC' ;ENCODE STATE 4
STRING S5 'RA*/RB*RC' ;ENCODE STATE 5
STRING S6 '/RA*RB*RC' ;ENCODE STATE 6
STRING S7 'RA*RB*RC' ;ENCODE STATE 7
;FOR PARALLEL INPUT
EQUATIONS ;S0 SELECTS D0 INPUT
;S1 SELECTS D1 INPUT
GLOBAL.SETF = RST ;ETC. SET INITIAL
;CONDITIONS, RESET.
/R0 := R0 ;R0 - R3, R0 DIVIDES
;THE CLOCK INPUT BY 2.
/R1 := R1*R0 ;R1 DIVIDES THE CLOCK
+ /R1*/R0 ;BY 4.
;
/R2 := R2*R1*R0 ;R2 DIVIDES THE CLOCK
+ /R2*/R1 ;BY 8.
+ /R2*/R0 ;
;
/R3 := R3*R2*R1*R0 ;R3 DIVIDES THE CLOCK
+ /R3*/R2 ;BY 16.
+ /R3*/R1 ;
+ /R3*/R0 ;
;RDY OUTPUT PERFORMS
RDY := RA*RB*RC*R3*R2*R1*R0*/SER ;A HANDSHAKE OPERATION
+ R3*R2*R1*R0*SER ;WHEN HIGH, NEW DATA
;MAY BE APPLIED.
/RA := R0*R1*R2*R3*RA*/SER ;COUNTER RA,RB,RC
+ /R0*/RA*/SER ;COUNTS THE NUMBER
+ /R1*/RA*/SER ;OF BITS TRANSMITTED
+ /R2*/RA*/SER ;WHEN A BYTE IS
+ /R3*/RA*/SER ;APPLIED TO THE
+ SER ;D0 - D7 DATA INPUTS
;THE LOGIC CONDITION
/RB := R0*R1*R2*R3*RA*RB*/SER ;OF THE SELECTED
+ /R0*/RB*/SER ;INPUT IS MULTIPLEXED
+ /R1*/RB*/SER ;TO THE RX REGISTERED
+ /R2*/RB*/SER ;OUTPUT BY THE 'ONE OF
+ /R3*/RB*/SER ;EIGHT' STATE SELECTOR,
+ /RA*/RB*/SER ;IN THE DIVIDE BY EIGHT
+ SER ;COUNTER RA, RB AND RC.
;FOR SERIAL TX /RA*/RB*/RC
/RC := R0*R1*R2*R3*RA*RB*RC*/SER ;SELECTS D0, RA*/RB*/RC
+ /R0*/RC*/SER ;SELECTS DATA INPUT D1
+ /R1*/RC*/SER ;ETC, WHILE /SER SELECTS
+ /R2*/RC*/SER ;PARALLEL OPERATION. IF
+ /R3*/RC*/SER ;/SEL IS ACTIVE SERIAL
+ /RA*/RC*/SER ;ENCODING IS SELECTED
+ /RB*/RC*/SER ;THE SERIAL DATA APPLIED
+ SER ;TO THE D0 INPUT IS
;ENCODED. D1 - D7 INPUTS
;ARE DESELECTED.
/DTST := S0*D0 ;D0 - D7 IS SERIALASED
+ S1*D1*/SER ;FOR PARALLEL TX.
+ S2*D2*/SER ;FOR SERIAL TX, D0 ONLY
+ S3*D3*/SER ;IS CLOCKED THROUGH TO
+ S4*D4*/SER ;THE DTST OUPUT.
+ S5*D5*/SER ;/DTST OUTPUT IS THE
+ S6*D6*/SER ;SERIALISED ENCODING
+ S7*D7*/SER ;OF THE DATA INPUT
;D0 - D7, OR D0.
/RX := S0*/R3*D0 + S0*R3*/D0 ;THE RX OUTPUT PROVIDES
+ S1*/R3*D1*/SER + S1*R3*/D1*/SER ;THE MANCHESTER ENCODED
+ S2*/R3*D2*/SER + S2*R3*/D2*/SER ;OUTPUT OF THE REFERENCE
+ S3*/R3*D3*/SER + S3*R3*/D3*/SER ;FREQUENCY, WHICH OCCURS AT
+ S4*/R3*D4*/SER + S4*R3*/D4*/SER ;THE R3 OUTPUT. THE PHASE
+ S5*/R3*D5*/SER + S5*R3*/D5*/SER ;AT R3 IS SHIFTED AT THE
+ S6*/R3*D6*/SER + S6*R3*/D6*/SER ;RX OUTPUT IF THE SELECTED
+ S7*/R3*D7*/SER + S7*R3*/D7*/SER ;DATA INPUT POLARITY CHANGES.
;IF /SER IS INACTIVE D0 - D7
;INPUTS ARE SELECTED. IF
;/SER IS ACTIVE ONLY THE
;SERIAL INPUT APPLIED TO
;D0 IS SELECTED.
SIMULATION ;
TRACE_ON CLK R0 R1 R2 R3 RA RB RC RX ;
/DTST RDY D0 D1 D2 D4 D5 D6 D7 ;
SER RST ;SET INITIAL CONDITIONS
SETF /CLK RST D0 D1 /D2 D3 D4 /D5 ;FOR DATA, AND CONTROL
/D6 /D7 /SER ;INPUTS.
SETF RST ;PARALLEL MODE SET. RESET
CLOCKF CLK ;ACTIVE TO INITALISE THE
SETF /RST ;REGISTERS. SET FOR THE
FOR I := 1 TO 128 DO ;PARALLEL INPUT MODE CLOCK
BEGIN CLOCKF CLK ;8 DATA BITS THROUGH TO
END ;R3 AND RX OUTPUTS. SET
SETF SER D0 ;THE SERIAL MODE VIA
FOR I := 1 TO 32 DO ;SERIAL INPUT CONTROL
BEGIN CLOCKF CLK ;PIN. CLOCK SYSTEM TO
END ;SELECT SERIAL OPERATION.
TRACE_OFF ;