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7492.chp
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1987-06-09
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1KB
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72 lines
06/10/87
This is a divide-by-12 counter. It contains a divide-by-2
and a divide-by-6 counter in the same package. Putting them together
makes a divide-by-12 counter.
14
BC Input
NC
NC
NC
Vcc (+)
Ro (1)
Ro (2)
Output D
Output C
Gnd (-)
Output B
Output A
NC
Input A
27
Power dissipation:
130 mW.
Count Frequency:
Up to 20 MHz.
------------------
Supply: 5.25 volts.
Temp: 0-70 c.
------------------
Outputs for the
divide-by-12:
Count D C B A
-----|| | | | |
0 ||0|0|0|0|
1 ||0|0|0|1|
2 ||0|0|1|0|
3 ||0|0|1|1|
4 ||0|1|0|0|
5 ||0|1|0|1|
6 ||1|0|0|0|
7 ||1|0|0|1|
8 ||1|0|1|0|
9 ||1|0|1|1|
10 ||1|1|0|0|
11 ||1|1|0|1|
-----------------
done
14
This is tied to the clock input of FF 2 and 3.
NC
NC
NC
Vcc (+5 volts.)
Input a of NAND gate, which is tied to the clear.
Input b of NAND gate, ' ' ' ' ' ' '
Output D
Output C
Ground (-)
Output B
Output A
NC
Input A, Tied into 1st FF. Clock input for counting sequence.