HAM Radio 1/HamRadio.cdr/circuit/gatesim/lights.sim

Text File | 1988-12-23 | 4KB | 122 lines

$
$ You may stop and continue the simulator demo at any time by pressing the
$ space bar.  Type any other key to interrupt.
$
$ The delay commands are here to allow you to read the comments.
DLay 3000
$
$ GateSim is a gate-level simulator.  It is an event driven simulator that
$ allows for arbitrary gate delays, both low-going and high-going.  The
$ simulator supports four states: 0, 1, X (unknown), and Z (undriven).
$
$ Simulator commands may come from the keyboard for interactive simulation.
$ For repeated simulations, commands may be stored in a file and replayed.
$ For this demo, commands are being read from the file lights.sim.
$
$ The circuit being simulated is a traffic light controller.  The schematic
$ was entered using OrCAD SDT III, using vendor independent cells from our
$ schematic library, SchemLib.  The OrCAD netlist output (EDIF) was converted
$ to simulator input by NetTran using timing from the National Semiconductor
$ gate array mapping library, NSC15GAMap.  Now we read in the netlist file
$ lights.net.
$
NEtfile LIGHTS
$
DLay 5000
$
$ Simulations run faster if the output is not displayed on the screen but
$ for this demo, we wish to see the output so we turn on the display.
MOnitor ON
DLay 3000
$
$ Signals that drive the external pins of the circuit are defined in a
$ vector file.  This file may contain 0s and 1s in .PATT statements or
$ specifications for repeated waveforms using .CLK statements.  For this
$ demo, the inputs consist of a 10MHz clock and a reset line that starts
$ low, goes high after 50nsec and stays high the rest of the simulation.
$
$ At this point, we define the name of the input vector pattern file.  The
$ file is not actually read in until simulation begins.  Default extension is
$ .VEC.
PAttfile LIGHTS
DLay 3000
$
$ When the simulation begins, the display will show the output signals.  We
$ wish to intersperse into the simulation display the input vectors as read
$ from the pattern file, along with any comments in the pattern file.
$ Show the input vectors in the simulator output marked with > character.
VIewvector ON
DLay 3000
$
$ The simulator can display the signal values as 0s and 1s or can show the
$ value of four nodes as a hex digit.  We define TOP to be the top nibble of
$ the 8 bit counter in the traffic controller state machine.
.HEX TOP = RED_EW TOP6 TOP5 TOP4
DLay 3000
$
$ Shift the decimal point so that the time is expressed in nanoseconds
$ because library times are in 1/10ths of nanoseconds.
DP 1 1 1
DLay 3000
$
$ The table statement defines what nodes are to be displayed during the
$ simulation.  Note that the ';' puts a space between lines in the output.
.tab RESET* ; CLOCK ; WALK_NS DONT_NS GREEN_NS YELLOW_NS RED_NS ;
+ WALK_EW DONT_EW GREEN_EW YELLOW_EW RED_EW
DLay 3000
$
$ Simulate from 0 to 5.0000 us.
DLay 3000
SImulate 0 50000
$
$ Woops!  We forgot to include the nibble TOP in the .TAB statement.  We can
$ change the list of nodes we are watching right now in the middle of a
$ simulation.  The '+' signifies adding nodes to the existing list.
.tab + ; TOP
DLay 3000
$
$ Simulate some more.
DLay 3000
SImulate +
$
$ Turn on horizontal scrolling.
HOrizontal ON
DLay 3000
$ Simulate some more.
DLay 3000
SImulate +
$
$ Turn on the waveform output.
WAveform ON
DLay 3000
$ Simulate some more.
DLay 3000
SImulate +
$
$ So far we have been viewing simulator output for every event with times
$ in between compressed.  Now we switch to sampled display with the STEP
$ specification.  Timing is displayed evenly but we may not see glitches.
$
DLay 10000
SImulate 200000 382500 STEP 500
$
$ Decrease the sampling time step to catch the glitch again.
DLay 3000
SImulate 382900 384310 STEP 10
$
FOrcenode Vdd T    $Power nodes do not need to be tested.
FOrcenode Gnd T
DLay 3000
$
$ Now do a fault simulation.  Default extension is .CMP.
DLay 3000
FSim 0 140000 -c lights
$
$ Find the paths and delays between the TEST POINT and DONT_NS.
DLay 3000
NDelay TEST_POINT DONT_NS -c100
$
$ Quit.
DLay 3000
QUit