Internet Standards/CD2.mdf/ccitt/1992/g/g811.asc

Text File | 1993-08-15 | 11KB | 590 lines

3.    Recommendation G.811



TIMING REQUIREMENTS AT THE OUTPUTS OF PRIMARY REF-
ERENCE CLOCKS SUITABLE FOR PLESIOCHRONOUS OPERA-
TION OF INTERNATIONAL DIGITAL LINKS



1.    General



1.1    International connections and network synchronization considerations



    National digital networks, which may have a variety of internal synchro-
nization arrangements, will usually be connected by international links
which operate plesiochronously. International switching centres (ISCs)
will be interconnected directly or indirectly via one or more intermediate
ISCs, as indicated in the hypothetical reference connection (HRX) shown
in Figure1/G.801.



    International connections terminate on synchronous network nodes that
may or may not be co-located with a primary reference clock. Such net-
work nodes may include slave clocks. Therefore, synchronous network
node clock specifications are essential to ensure satisfactory operation of
plesiochronous international digital links.



    Figure 1/G.811 illustrates the two alternative international connections
described above.



1.2    Purpose of this Recommendation



    The purpose of this Recommendation is to specify requirements for pri-
mary reference clocks, promote understanding of associated timing
requirements for plesiochronous operation of international digital links,
and to clarify the relationship of the requirements for synchronous net-
work nodes, constituent clocks and the use of satellite systems.



    Administrations may apply this Recommendation, at their own discre-
tion, to primary reference clocks other than those used in connection with
international traffic.



1.3  Interaction between plesiochronous and synchronous international
operation



    It is important that the Recommendations for plesiochronous operation
should not preclude the possibility of the later introduction of interna-
tional synchronization.



    When plesiochronous and synchronous operations coexist within the
international network, the nodes will be required to provide for both
types of operation. It is therefore important that the synchronization con-
trols do not cause short-term frequency departures of the clocks which
are unacceptable for plesiochronous operation. The magnitudes of the
short-term frequency departures should satisfy the specifications in º 2.2.































a)    Case 1: Synchronous network node including primary reference clock



































b)    Case 2: Synchronous network node including slave clock





Note 1 - PRC  Primary reference clock

    SC   Slave clock

    DE   Digital equipment such as digital exchange or digital muldex

    IDL  International digital link



Note 2 - Other cases are for further study.







FIGURE 1/G.811



International connections terminating on synchronous network nodes





1.4    Maximum time interval error and relationship with frequency depar-
ture



    Maximum time interval error (MTIE) is the maximum peak-to-peak vari-
ation in the time delay of a given timing signal with respect to an ideal
timing signal within a particular time period (Figure 2/G.811), i.e.
MTIE(S)=maxx(t)-min x(t) for all t within S.



































FIGURE 2/G.811



Definition of maximum time interval error





    Long-term frequency departure (_f/f) is determined by the MTIE divided
by the observation interval S, as S increases.



Note 1 - The rigorous definition and measurement of long-term fre-
quency departure for clocks is a subject for further study.



2.    Long-term frequency departure and phase stability of primary reference
clocks



    A primary reference clock controls the synchronization performance of
the overall network. It is necessary to specify the long-term frequency
departure and phase stability of a primary reference clock, and to provide
guidance concerning issues associated with degradation and unavailabil-
ity performance. The definition of a primary reference clock is given in
RecommendationG.81y.



Long-term frequency departure



    A primary reference clock should be designed for a long-term frequency
departure of not greater than 1 x 10-11. The long-term frequency depar-
ture of  1x10-11 is about two orders of magnitude larger than the uncer-
tainty of Coordinated Universal Time (UTC). Therefore UTC should be
the reference for long-term frequency departure (see CCIR Report898).



    The theoretical long-term mean rate of occurrence of controlled frame or
octet slips (i.e. the design rate of slips based on ideally undisturbed con-
ditions) in any 64kbit/s channel is consequently not greater than one in
70days per digital international link (see Recommendation G.822).





Note 1 - Some administrations support a primary reference clock long-
term frequency departure of not greater than 7 x 10-12 based upon cur-
rent primary reference clock technology.



Note 2 - Caesium-beam technology is suitable for primary reference
clocks complying with the above specification.



2.2    Phase stability



    The phase stability of a clock can be described by its phase variations,
which in turn can be separated into a number of components:



    -    phase discontinuities due to transient disturbances;



    -    long-term phase variations (wander and integrated frequency depar-
ture);



    -    short-term phase variations (jitter).



    A phase stability model for primary reference clocks is described in the
annex to this Recommendation.



2.2.1    Phase discontinuities



    Primary reference clocks need a very high reliability and are likely to
include replication of the equipment in order to ensure the continuity of
output. However, any phase discontinuity, due to internal operations
within the clock or network node, should only result in a lengthening or
shortening of the timing signal interval and must not cause a phase dis-
continuity in excess of 1/8 of a unit interval at the clock output. (This
refers to output signals at 1544kbit/s or 2048kHz, of º4. Specification
of other interfaces is under study.)



2.2.2    Long-term phase variations



    The maximum permissible long-term phase variation of a primary refer-
ence clock (whether sinusoidal or pulse) is expressed in MTIE.



    The MTIE over a period of S seconds shall not exceed the following lim-
its:



    a)    100S ns     for the interval 0.05 < S < 5



    b)    (5S+500) ns for the interval 5 < S < 500



    c)    (.01S+X) ns for values of S > 500.



    The asymptote designated 10-11 refers to the long-term frequency depar-
ture specified in Section 2.1.



    The value of X is under study. It is provisionally recommended that
X=3000ns. Certain administrations support a value of 1000 ns.





Note 1 - For measurement of long-term phase variations, the use of 10Hz
low-pass filter is suggested.



Note 2 - The MTIE Recommendation requires further study.



Note 3 - The overall specification is illustrated in Figure 3/G.811.



2.2.3    Short-term phase variations



    Clock implementations exist today which may have some high-frequency
phase instability components. The specification of maximum permissible
short- term phase variation of a primary reference clock due to jitter is
under study.



3.    Degradation of the performance of a primary reference clock



    To achieve the required high reliability a primary reference clock
includes redundancy, i.e. by incorporating several (caesium beam) oscil-
lators, the output of only one of these being used at any given time. If a
clock frequency departs significantly from its nominal value, this should
be detected and switching to an undegraded oscillator should then be
effected. This switching should be accomplished before the MTIE speci-
fication is exceeded.



    With current technology, the performance of a primary reference clock is
statistically well below the MTIE specification of Figure 3/G.811.



4.    Interfaces



    The preferred interface for the timing output is in accordance with Rec-
ommendation G.703, 10, i.e. an interface at 2048 kHz. By agreement
between operators or manufacturers of equipment, the timing signal may
also be delivered at various other physical interfaces (e.g., 1544kbit/s
primary rate signal, 1MHz, 5MHz, or 10MHz).









































































FIGURE 3/G.811



Permissible maximum time interval error (MTIE)

due to long-term phase variation as a function of

observation period S for a primary reference clock





5.    Use of satellite systems in an international plesiochronous digital net-
work



    It is recommended that the link be operated in a plesiochronous mode
using high accuracy (1 x 10-11) source for the satellite TDMA timing.
The international satellite links will be terminated on network nodes
whose timing is in accordance with Recommendations G.823 and G.824.



6.    Guidelines concerning the measurement of jitter and wander



    Verification of compliance with jitter and wander specifications requires
standardized measurement methodologies to eliminate ambiguities in the
measurements and in interpretation and comparison of measurement
results. Guidelines concerning the measurement of jitter and wander are
contained in Supplement No. 3.8 (O-Series) and Supplement No. 35.



ANNEX A



(to Recommendation G.811)



Characterization of primary reference clock phase stability





    The following phase stability model may be employed to characterize
primary reference clocks. Let x(t) represent the time interval error of a
clock synchronized at t = 0, and free-running against UTC thereafter. x(t)
may be defined as:



x(t) = y0t + (D/2)t2 + e(t)



where:



    D    is the normalized linear frequency drift per unit time (ageing),



    y0    is the initial frequency departure with respect to UTC, and



    e(t)    is the random error component.



    The estimate of the standard deviation of x(t) may be obtained, and used
for characterization of phase instability.

                                                                           sx(t) = (D/2)t2 + t _sy2 +
sy2 (t = t)

O

where:



    sy2     is the two-sample variance of the initial frequency depar-
ture,                 and



    sy2(t) is the two-sample Allan variance describing the random frequency
instability of the clock.