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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                           Motorola                           |
  5. |                                                              |
  6. |         666      88888      000      99999    EEEEEEE        |
  7. |        6        8     8    0   0    9     9   E              |
  8. |       6         8     8   0   0 0   9     9   E              |
  9. |       666666     88888    0  0  0    999999   EEEEE          |
  10. |       6     6   8     8   0 0   0         9   E              |
  11. |       6     6   8     8    0   0         9    E              |
  12. |        66666     88888      000      9999     EEEEEEE        |
  13. |                                                              |
  14. |        6809E MICROPROCESSOR Instruction Set Summary          |
  15. |                                                              |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
  19. |                                                              |
  20. |                    _________    _________                    |
  21. |                  _|         \__/         |_  ____            |
  22. |             Vss |_|1                   40|_| Halt <--        |
  23. |             ___  _|                      |_                  |
  24. |         --> NMI |_|2                   39|_| TSC <--         |
  25. |             ___  _|                      |_                  |
  26. |         --> IRQ |_|3                   38|_| LIC -->         |
  27. |            ____  _|                      |_  _____           |
  28. |        --> FIRQ |_|4                   37|_| Reset <--       |
  29. |                  _|                      |_                  |
  30. |          <-- BS |_|5                   36|_| AVMA -->        |
  31. |                  _|                      |_                  |
  32. |          <-- BA |_|6                   35|_| Q <--           |
  33. |                  _|                      |_                  |
  34. |             Vcc |_|7                   34|_| E <--           |
  35. |                  _|                      |_                  |
  36. |          <-- A0 |_|8                   33|_| Busy -->        |
  37. |                  _|                      |_    _             |
  38. |          <-- A1 |_|9                   32|_| R/W -->         |
  39. |                  _|                      |_                  |
  40. |          <-- A2 |_|10      6809E       31|_| D0 <-->         |
  41. |                  _|                      |_                  |
  42. |          <-- A3 |_|11                  30|_| D1 <-->         |
  43. |                  _|                      |_                  |
  44. |          <-- A4 |_|12                  29|_| D2 <-->         |
  45. |                  _|                      |_                  |
  46. |          <-- A5 |_|13                  28|_| D3 <-->         |
  47. |                  _|                      |_                  |
  48. |          <-- A6 |_|14                  27|_| D4 <-->         |
  49. |                  _|                      |_                  |
  50. |          <-- A7 |_|15                  26|_| D5 <-->         |
  51. |                  _|                      |_                  |
  52. |          <-- A8 |_|16                  25|_| D6 <-->         |
  53. |                  _|                      |_                  |
  54. |          <-- A9 |_|17                  24|_| D7 <-->         |
  55. |                  _|                      |_                  |
  56. |         <-- A10 |_|18                  23|_| A15 -->         |
  57. |                  _|                      |_                  |
  58. |         <-- A11 |_|19                  22|_| A14 -->         |
  59. |                  _|                      |_                  |
  60. |         <-- A12 |_|20                  21|_| A13 -->         |
  61. |                   |______________________|                   |
  62. |                                                              |
  63. |                                                              |
  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        November 1984                                  |
  78. |Updated        April 1985                                     |
  79. |Issue          1.1                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemon.|Op|IHNZVC|IEXD#R|~|Description           |Notes       |
  83. |-------+--+------+------+-+----------------------+------------|
  84. |ABX    |3A|------|X     |3|Add to Index Register |X=X+B       |
  85. |ADCa  s|B9|-*****| XXXXX|5|Add with Carry        |a=a+s+C     |
  86. |ADDa  s|BB|-*****| XXXXX|5|Add                   |a=a+s       |
  87. |ADDD  s|F3|-*****| XXX*X|7|Add to Double acc.    |D=D+s       |
  88. |ANDa  s|B4|--**0-| XXXXX|5|Logical AND           |a=a&s       |
  89. |ANDCC s|1C|?????1|    X |3|Logical AND with CCR  |CC=CC&s     |
  90. |ASL   d|78|--****| XXX X|7|Arithmetic Shift Left |d=d*2       |
  91. |ASLa   |48|--****|X     |2|Arithmetic Shift Left |a=a*2       |
  92. |ASR   d|77|--****| XXX X|7|Arithmetic Shift Right|d=d/2       |
  93. |ASRa   |47|--****|X     |2|Arithmetic Shift Right|a=a/2       |
  94. |BCC   m|24|------|     x|3|Branch if Carry Clear |If C=0      |
  95. |BCS   m|25|------|     x|3|Branch if Carry Set   |If C=1      |
  96. |BEQ   m|27|------|     x|3|Branch if Equal       |If Z=1      |
  97. |BGE   m|2C|------|     x|3|Branch if Great/Equal |If NxV=0    |
  98. |BGT   m|2E|------|     x|3|Branch if Greater Than|If Zv{NxV}=0|
  99. |BHI   m|22|------|     x|3|Branch if Higher      |If CvZ=0    |
  100. |BHS   m|24|------|     x|3|Branch if Higher/Same |If C=0      |
  101. |BITa  s|B5|--**0-| XXXXX|5|Bit Test accumulator  |a&s         |
  102. |BLE   m|2F|------|     x|3|Branch if Less/Equal  |If Zv{NxV}=1|
  103. |BLO   m|25|------|     x|3|Branch if Lower       |If C=1      |
  104. |BLS   m|23|------|     x|3|Branch if Lower/Same  |If CvZ=1    |
  105. |BLT   m|2D|------|     x|3|Branch if Less Than   |If NxV=1    |
  106. |BMI   m|2B|------|     x|3|Branch if Minus       |If N=1      |
  107. |BNE   m|26|------|     x|3|Branch if Not Equal   |If Z=0      |
  108. |BPL   m|2A|------|     x|3|Branch if Plus        |If N=0      |
  109. |BRA   m|20|------|     x|3|Branch Always         |PC=m        |
  110. |BRN   m|21|------|     x|3|Branch Never          |NOP         |
  111. |BSR   m|8D|------|     x|7|Branch to Subroutine  |-[S]=PC,BRA |
  112. |BVC   m|28|------|     x|3|Branch if Overflow Clr|If V=0      |
  113. |BVS   m|29|------|     x|3|Branch if Overflow Set|If V=1      |
  114. |CLR   d|7F|--0100| XXX X|7|Clear                 |d=0         |
  115. |CLRa   |4F|--0100|X     |2|Clear accumulator     |a=0         |
  116. |CMPa  s|B1|--****| XXXXX|5|Compare               |a-s         |
  117. |CMPD  s|B3|--****| XXX*X|8|Compare Double acc.   |D-s    (10H)|
  118. |CMPS  s|BC|--****| XXX*X|8|Compare Stack pointer |S-s    (11H)|
  119. |CMPU  s|B3|--****| XXX*X|8|Compare User stack ptr|U-s    (11H)|
  120. |CMPi  s|BC|--****| XXX*X|7|Compare               |i-s (Y ~s=8)|
  121. |COM   d|73|--**01| XXX X|2|Complement            |d=~d        |
  122. |COMa   |43|--**01|X     |7|Complement accumulator|a=~a        |
  123. |CWAI  n|3C|E?????|    X |K|AND CCR, Wait for int.|CC=CC&n,E=1,|
  124. |DAA    |19|--****|X     |2|Decimal Adjust Acc.   |A=BCD format|
  125. |DEC   d|7A|--***-| XXX X|7|Decrement             |d=d-1       |
  126. |DECa   |4A|--***-|X     |2|Decrement accumulator |a=a-1       |
  127. |EORa  s|B8|--**0-| XXXXX|5|Logical Exclusive OR  |a=axs       |
  128. |EXG r,r|1E|------|X     |8|Exchange (r1 size=r2) |r1<->r2     |
  129. |INC   d|7C|--***-| XXX X|7|Increment             |d=d+1       |
  130. |INCa   |4C|--***-|X     |2|Increment accumulator |a=a+1       |
  131. |JMP   s|7E|------| XXX X|4|Jump                  |PC=EAs      |
  132. |JSR   s|BD|------| XXX X|8|Jump to Subroutine    |-[S]=PC,JMP |
  133. |LBcc nn|10|------|     x|5|Long cond. Branch(~=6)|If cc LBRA  |
  134. |LBRA nn|16|------|     x|5|Long Branch Always    |PC=nn       |
  135. |LBSR nn|17|------|     x|9|Long Branch Subroutine|-[S]=PC,LBRA|
  136. |LDa   s|B6|--**0-| XXXXX|5|Load accumulator      |a=s         |
  137. |LDD   s|FC|--**0-| XXX*X|6|Load Double acc.      |D=s         |
  138. |LDS   s|FE|--**0-| XXX*X|7|Load Stack pointer    |S=s    (10H)|
  139. |LDU   s|FE|--**0-| XXX*X|6|Load User stack ptr   |U=s         |
  140. |LDi   s|BE|--**0-| XXX*X|6|Load index register   |i=s (Y ~s=7)|
  141. |LEAp  s|3X|---i--| xX  X|4|Load Effective Address|p=EAs(X=0-3)|
  142. |LSL   d|78|--0***| XXX X|7|Logical Shift Left    |d={C,d,0}<- |
  143. |LSLa   |48|--0***|X     |2|Logical Shift Left    |a={C,a,0}<- |
  144. |LSR   d|74|--0***| XXX X|7|Logical Shift Right   |d=->{C,d,0} |
  145. |LSRa   |44|--0***|X     |2|Logical Shift Right   |d=->{C,d,0} |
  146. |MUL    |3D|---*-*|X     |B|Multiply              |D=A*B       |
  147. |NEG   d|70|-?****| XXX X|7|Negate                |d=-d        |
  148. |NEGa   |40|-?****|X     |2|Negate accumulator    |a=-a        |
  149. |NOP    |12|------|X     |2|No Operation          |            |
  150. |ORa   s|BA|--**0-| XXXXX|5|Logical inclusive OR  |a=avs       |
  151. |ORCC  n|1A|??????|    X |3|Inclusive OR CCR      |CC=CCvn     |
  152. |PSHS  r|34|------|X     |2|Push reg(s) (not S)   |-[S]={r,...}|
  153. |PSHU  r|36|------|X     |2|Push reg(s) (not U)   |-[U]={r,...}|
  154. |PULS  r|35|??????|X     |2|Pull reg(s) (not S)   |{r,...}=[S]+|
  155. |PULU  r|37|??????|X     |2|Pull reg(s) (not U)   |{r,...}=[U]+|
  156. |ROL   d|79|--****| XXX X|7|Rotate Left           |d={C,d}<-   |
  157. |ROLa   |49|--****|X     |2|Rotate Left acc.      |a={C,a}<-   |
  158. |ROR   d|76|--****| XXX X|7|Rotate Right          |d=->{C,d}   |
  159. |RORa   |46|--****|X     |2|Rotate Right acc.     |a=->{C,a}   |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemon.|Op|IHNZVC|IEXD#R|~|Description           |Notes       |
  163. |-------+--+------+------+-+----------------------+------------|
  164. |RTI    |3B|-*****|X     |6|Return from Interrupt |{regs}=[S]+ |
  165. |RTS    |39|------|X     |5|Return from Subroutine|PC=[S]+     |
  166. |SBCa  s|B2|--****| XXXXX|5|Subtract with Carry   |a=a-s-C     |
  167. |SEX    |1D|--**--|X     |2|Sign Extend           |D=B         |
  168. |STa   d|B7|--**0-| XXX X|5|Store accumultor      |d=a         |
  169. |STD   d|FD|--**0-| XXX X|6|Store Double acc.     |D=a         |
  170. |STS   d|FF|--**0-| XXX X|7|Store Stack pointer   |S=a    (10H)|
  171. |STU   d|FF|--**0-| XXX X|6|Store User stack ptr  |U=a         |
  172. |STi   d|BF|--**0-| XXX X|6|Store index register  |i=a (Y ~s=7)|
  173. |SUBa  s|B0|--****| XXXXX|5|Subtract              |a=a-s       |
  174. |SUBD  s|B3|--****| XXX*X|7|Subtract Double acc.  |D=D-s       |
  175. |SWI    |3F|1-----|X     |J|Software Interrupt 1  |-[S]={regs} |
  176. |SWI2   |3F|E-----|X     |K|Software Interrupt 2  |SWI    (10H)|
  177. |SWI3   |3F|E-----|X     |K|Software Interrupt 3  |SWI    (11H)|
  178. |SYNC   |13|------|X     |2|Sync. to interrupt    |  (min ~s=2)|
  179. |TFR r,r|1F|------|X     |6|Transfer (r1 size<=r2)|r2=r1       |
  180. |TST   s|7D|--**0-| XXX X|7|Test                  |s           |
  181. |TSTa   |4D|--**0-|X     |2|Test accumulator      |a           |
  182. |----------+------+------+-+-----------------------------------|
  183. | CCR      |-*01? |      | |Unaffect/affected/reset/set/unknown|
  184. | E        |E     |      | |Entire flag (Bit 7, if set RTI~s=F)|
  185. | F  I     |I     |      | |FIRQ/IRQ interrupt mask (Bit 6/4)  |
  186. | H        | H    |      | |Half carry (Bit 5)                 |
  187. | N        |  N   |      | |Negative (Bit 3)                   |
  188. | Z        |   Z  |      | |Zero (Bit 2)                       |
  189. | V        |    V |      | |Overflow (Bit 1)                   |
  190. | C        |     C|      | |Carry/borrow (Bit 0)               |
  191. |-----------------+------+-------------------------------------|
  192. | a               |I     | |Inherent (a=A,Op=4XH, a=B,Op=5XH)  |
  193. | nn,E            | E    | |Extended (Op=E, ~s=e)              |
  194. | [nn]            | x    | |Extended indirect                  |
  195. | xx,p!           |  X   | |Indexed (Op=E-10H, ~s=e-1)         |
  196. | [xx,p!]         |  X   | |Indexed indirect (p!=p++,--p only) |
  197. | n,D             |   D  | |Direct (Op=E-20H, ~s=e-1)          |
  198. | #n              |    # | |Immediate (8-bit, Op=E-30H, ~s=e-3)|
  199. | #nn             |    * | |Immediate (16-bit)                 |
  200. | m               |     x| |Relative (PC=PC+2+offset)          |
  201. | [m]             |     R| |Relative indirect (ditto)          |
  202. |--------------------------+-----------------------------------|
  203. |DIRECT                    |Direct addressing mode             |
  204. |EXTEND                    |Extended addressing mode           |
  205. |FCB      n                |Form Constant Byte                 |
  206. |FCC      'string'         |Form Constant Characters           |
  207. |FDB      nn               |Form Double Byte                   |
  208. |RMB      nn               |Reserve Memory Bytes               |
  209. |--------------------------+-----------------------------------|
  210. | A  B                     |Accumulators (8-bit)               |
  211. | CC                       |Condition Code register (8-bit)    |
  212. | D                        |A and B (16-bit, A high, B low)    |
  213. | DP                       |Direct Page register (8-bit)       |
  214. | PC                       |Program Counter (16-bit)           |
  215. | S  U                     |Hardware/User stack pointer(16-bit)|
  216. | X  Y                     |Index registers (16-bit)           |
  217. |--------------------------+-----------------------------------|
  218. | a                        |Acc A or B (a=A,Op=BXH, a=B,Op=FXH)|
  219. | d  s  EA                 |Destination/source/effective addr. |
  220. | i  p  r                  |Regs X,Y/regs X,Y,S,U/any register |
  221. | m                        |Relative address (-126 to +129)    |
  222. | n  nn                    |8/16-bit expression(0 to 255/65535)|
  223. | xx  p!                   |A,B,D,nn/p+,-p,p++,--p (indexed)   |
  224. | +  -  *  /               |Add/subtract/multiply/divide       |
  225. | &  ~  v  x               |AND/NOT/inclusive OR/exclusive OR  |
  226. | <-  ->  <->              |Rotate left/rotate right/exchange  |
  227. | [ ]  [ ]+  -[ ]          |Indirect address/increment/decr.   |
  228. | { }                      |Combination of operands            |
  229. | {regs}                   |If E {PC,U/S,Y,X,DP,B,A,CC}/{PC,CC}|
  230. | (10H)  (11H)             |Hex opcode to precede main opcode  |
  231. |--------------------------+-----------------------------------|
  232. | FFF0H to FFF1H           |Reserved by Motorola               |
  233. | FFF2H to FFF3H           |SWI3 instruction interrupt vector  |
  234. | FFF4H to FFF5H           |SWI2 instruction interrupt vector  |
  235. | FFF6H to FFF7H           |Fast hardware int. vector (FIRQ)   |
  236. | FFF8H to FFF9H           |Hardware interrupt vector (IRQ)    |
  237. | FFFAH to FFFBH           |SWI instruction interrupt vector   |
  238. | FFFCH to FFFDH           |Non-maskable interrupt vector (NMI)|
  239. | FFFEH to FFFFH           |Reset vector                       |
  240. ----------------------------------------------------------------
  241.