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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                           Motorola                           |
  5. |                                                              |
  6. |              666      88888      000      88888              |
  7. |             6        8     8    0   0    8     8             |
  8. |            6         8     8   0   0 0   8     8             |
  9. |            666666     88888    0  0  0    88888              |
  10. |            6     6   8     8   0 0   0   8     8             |
  11. |            6     6   8     8    0   0    8     8             |
  12. |             66666     88888      000      88888              |
  13. |                                                              |
  14. |         6808 MICROPROCESSOR Instruction Set Summary          |
  15. |                                                              |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
  19. |                                                              |
  20. |                    _________    _________                    |
  21. |                  _|         \__/         |_  _____           |
  22. |             Vss |_|1                   40|_| Reset <--       |
  23. |            ____  _|                      |_                  |
  24. |        --> Halt |_|2                   39|_| XTAL <--        |
  25. |                  _|                      |_                  |
  26. |          --> MR |_|3                   38|_| EXTAL <--       |
  27. |             ___  _|                      |_                  |
  28. |         --> IRQ |_|4                   37|_| E -->           |
  29. |                  _|                      |_                  |
  30. |         <-- VMA |_|5                   36|_| Vss             |
  31. |             ___  _|                      |_                  |
  32. |         --> NMI |_|6                   35|_| N/C             |
  33. |                  _|                      |_    _             |
  34. |          <-- BA |_|7                   34|_| R/W -->         |
  35. |                  _|                      |_                  |
  36. |             Vcc |_|8                   33|_| D0 <-->         |
  37. |                  _|                      |_                  |
  38. |          <-- A0 |_|9                   32|_| D1 <-->         |
  39. |                  _|                      |_                  |
  40. |          <-- A1 |_|10       6808       31|_| D2 <-->         |
  41. |                  _|                      |_                  |
  42. |          <-- A2 |_|11                  30|_| D3 <-->         |
  43. |                  _|                      |_                  |
  44. |          <-- A3 |_|12                  29|_| D4 <-->         |
  45. |                  _|                      |_                  |
  46. |          <-- A4 |_|13                  28|_| D5 <-->         |
  47. |                  _|                      |_                  |
  48. |          <-- A5 |_|14                  27|_| D6 <-->         |
  49. |                  _|                      |_                  |
  50. |          <-- A6 |_|15                  26|_| D7 <-->         |
  51. |                  _|                      |_                  |
  52. |          <-- A7 |_|16                  25|_| A15 -->         |
  53. |                  _|                      |_                  |
  54. |          <-- A8 |_|17                  24|_| A14 -->         |
  55. |                  _|                      |_                  |
  56. |          <-- A9 |_|18                  23|_| A13 -->         |
  57. |                  _|                      |_                  |
  58. |         <-- A10 |_|19                  22|_| A12 -->         |
  59. |                  _|                      |_                  |
  60. |         <-- A11 |_|20                  21|_| Vss             |
  61. |                   |______________________|                   |
  62. |                                                              |
  63. |                                                              |
  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        June 1982                                      |
  78. |Updated        April 1985                                     |
  79. |Issue          1.1                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnem. |Op|HINZVC|IEXD#R|~|Description            |Notes       |
  83. |------+--+------+------+-+-----------------------+------------|
  84. |ABA   |1B|*-****|X     |2|Add accumulators       |A=A+B       |
  85. |ADCA s|B9|*-****| XXXX |4|Add with Carry         |A=A+s+C     |
  86. |ADCB s|F9|*-****| XXXX |4|Add with Carry         |B=B+s+C     |
  87. |ADDA s|BB|*-****| XXXX |4|Add                    |A=A+s       |
  88. |ADDB s|FB|*-****| XXXX |4|Add                    |B=B+s       |
  89. |ANDA s|B4|--**0-| XXXX |4|Logical AND            |A=A&s       |
  90. |ANDB s|F4|--**0-| XXXX |4|Logical AND            |B=B&s       |
  91. |ASL  d|78|--****| XX   |6|Arithmetic Shift Left  |d=d*2       |
  92. |ASLA  |48|--****|X     |2|Arithmetic Shift Left  |A=A*2       |
  93. |ASLB  |58|--****|X     |2|Arithmetic Shift Left  |B=B*2       |
  94. |ASR  d|77|--****| XX   |6|Arithmetic Shift Right |d=d/2       |
  95. |ASRA  |47|--****|X     |2|Arithmetic Shift Right |A=A/2       |
  96. |ASRB  |57|--****|X     |2|Arithmetic Shift Right |B=B/2       |
  97. |BCC  a|24|------|     X|4|Branch if Carry Clear  |If C=0      |
  98. |BCS  a|25|------|     X|4|Branch if Carry Set    |If C=1      |
  99. |BEQ  a|27|------|     X|4|Branch if Equal        |If Z=1      |
  100. |BGE  a|2C|------|     X|4|Branch if Greater or Eq|If NxV=0    |
  101. |BGT  a|2E|------|     X|4|Branch if Greater Than |If Zv{NxV}=0|
  102. |BHI  a|22|------|     X|4|Branch if Higher       |If CvZ=0    |
  103. |BITA s|B5|--**0-| XXXX |4|Bit Test               |A&s         |
  104. |BITB s|F5|--**0-| XXXX |4|Bit Test               |B&s         |
  105. |BLE  a|2F|------|     X|4|Branch if Less or Equal|If Zv{NxV}=0|
  106. |BLS  a|23|------|     X|4|Branch if Lower or Same|If CvZ=1    |
  107. |BLT  a|2D|------|     X|4|Branch if Less Than    |If NxV=1    |
  108. |BMI  a|2B|------|     X|4|Branch if Minus        |If N=1      |
  109. |BNE  a|26|------|     X|4|Branch if Not Equal    |If Z=0      |
  110. |BPL  a|2A|------|     X|4|Branch if Plus         |If N=0      |
  111. |BRA  a|20|------|     X|4|Branch Always          |PC=a        |
  112. |BSR  a|8D|------|     X|8|Branch to Subroutine   |-[S]=PC,PC,a|
  113. |BVC  a|28|------|     X|4|Branch if Overflow Clr |If V=0      |
  114. |BVS  a|29|------|     X|4|Branch if Overflow Set |If V=1      |
  115. |CBA   |11|--****|X     |2|Compare accumulators   |A-B         |
  116. |CLC   |0C|-----0|X     |2|Clear Carry            |C=0         |
  117. |CLI   |0E|-0----|X     |2|Clear Interrupt Mask   |I=0         |
  118. |CLR  d|7F|--0100| XX   |6|Clear                  |d=0         |
  119. |CLRA  |4F|--0100|X     |2|Clear accumulator      |A=0         |
  120. |CLRB  |5F|--0100|X     |2|Clear accumulator      |B=0         |
  121. |CLV   |0A|----0-|X     |2|Clear Overflow         |V=0         |
  122. |CMPA s|B1|--****| XXXX |4|Compare                |A-s         |
  123. |CMPB s|F1|--****| XXXX |4|Compare                |B-s         |
  124. |COM  d|63|--**01| XX   |7|Complement             |d=~d        |
  125. |COMA  |43|--**01|X     |2|Complement accumulator |A=~A        |
  126. |COMB  |53|--**01|X     |2|Complement accumulator |B=~B        |
  127. |CPX  s|BC|--****| XXX* |5|Compare Index Register |X-s         |
  128. |DAA   |19|--****|X     |2|Decimal Adjust Acc.    |A=BCD format|
  129. |DEC  d|7A|--**?-| XX   |6|Decrement              |d=d-1       |
  130. |DECA  |4A|--**?-|X     |2|Decrement accumulator  |A=A-1       |
  131. |DECB  |5A|--**?-|X     |2|Decrement accumulator  |B=B-1       |
  132. |DES   |34|------|X     |4|Decrement Stack Pointer|S=S-1       |
  133. |DEX   |09|---*--|X     |4|Decrement Index Reg    |X=X-1       |
  134. |EORA s|B8|--**0-| XXXX |4|Logical Exclusive OR   |A=Axs       |
  135. |EORB s|F8|--**0-| XXXX |4|Logical Exclusive OR   |B=Bxs       |
  136. |INC  d|7C|--**?-| XX   |6|Increment              |d=d+1       |
  137. |INCA  |4C|--**?-|X     |2|Increment accumulator  |A=A+1       |
  138. |INCB  |5C|--**?-|X     |2|Increment accumulator  |B=B+1       |
  139. |INS   |31|------|X     |4|Increment Stack Pointer|S=S+1       |
  140. |INX   |08|---*--|X     |4|Increment Index Reg    |X=X+1       |
  141. |JMP  d|7E|------| XX   |3|Jump                   |PC=d        |
  142. |JSR  d|BD|------| XX   |9|Jump to Subroutine     |-[S]=PC,PC=d|
  143. |LDAA s|B6|--**0-| XXXX |4|Load Accumulator       |A=s         |
  144. |LDAB s|F6|--**0-| XXXX |4|Load Accumulator       |B=s         |
  145. |LDS  s|BE|--**0-| XXX* |5|Load Stack Pointer     |S=s         |
  146. |LDX  s|FE|--**0-| XXX* |5|Load Index Register    |X=s         |
  147. |LSR  d|74|--0***| XX   |6|Logical Shift Right    |d=->{0,d,C} |
  148. |LSRA  |44|--0***|X     |2|Logical Shift Right    |A=->{0,A,C} |
  149. |LSRB  |54|--0***|X     |2|Logical Shift Right    |B=->{0,B,C} |
  150. |NEG  d|70|--****| XX   |6|Negate                 |d=-d        |
  151. |NEGA  |40|--****|X     |2|Negate accumulator     |A=-A        |
  152. |NEGB  |50|--****|X     |2|Negate accumulator     |B=-B        |
  153. |NOP   |01|------|X     |2|No Operation           |            |
  154. |ORAA s|BA|--**0-| XXXX |4|Logical inclusive OR   |A=Avs       |
  155. |ORAB s|FA|--**0-| XXXX |4|Logical inclusive OR   |B=Bvs       |
  156. |PSHA  |36|------|X     |4|Push                   |-[S]=A      |
  157. |PSHB  |37|------|X     |4|Push                   |-[S]=B      |
  158. |PULA  |32|------|X     |4|Pull                   |A=[S]+      |
  159. |PULB  |33|------|X     |4|Pull                   |B=[S]+      |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnem. |Op|HINZVC|IEXD#R|~|Description            |Notes       |
  163. |------+--+------+------+-+-----------------------+------------|
  164. |ROL  d|79|--**?*| XX   |6|Rotate Left            |d={C,d}<-   |
  165. |ROLA  |49|--**?*|X     |2|Rotate Left accumulator|A={C,A}<-   |
  166. |ROLB  |59|--**?*|X     |2|Rotate Left accumulator|B={C,B}<-   |
  167. |ROR  d|76|--**?*| XX   |6|Rotate Right           |d=->{C,d}   |
  168. |RORA  |46|--**?*|X     |2|Rotate Right acc.      |A=->{C,A}   |
  169. |RORB  |56|--**?*|X     |2|Rotate Right acc.      |B=->{C,B}   |
  170. |RTI   |3B|??????|X     |A|Return from Interrupt  |{regs}=[S]+ |
  171. |RTS   |39|------|X     |5|Return from Subroutine |PC=[S]+     |
  172. |SBA   |10|--****|X     |2|Subtract accumulators  |A=A-B       |
  173. |SBCA s|B2|--****| XXXX |4|Subtract with Carry    |A=A-s-C     |
  174. |SBCB s|F2|--****| XXXX |4|Subtract with Carry    |B=B-s-C     |
  175. |SEC   |0D|-----1|X     |2|Set Carry              |C=1         |
  176. |SEI   |0F|-1----|X     |2|Set Interrupt Mask     |I=1         |
  177. |SEV   |0B|----1-|X     |2|Set Overflow           |V=1         |
  178. |STAA d|B7|--**0-| XXX  |5|Store Accumulator      |d=A         |
  179. |STAB d|F7|--**0-| XXX  |5|Store Accumulator      |d=B         |
  180. |STS  d|BF|--**0-| XXX  |6|Store Stack Pointer    |d=S         |
  181. |STX  d|FF|--**0-| XXX  |6|Store Index Register   |d=X         |
  182. |SUBA s|B0|--****| XXXX |4|Subtract               |A=A-s       |
  183. |SUBB s|F0|--****| XXXX |4|Subtract               |B=B-s       |
  184. |SWI   |3F|-1----|X     |C|Software Interrupt     |-[S]={regs} |
  185. |TAB   |17|--**0-|X     |2|Transfer accumulators  |B=A         |
  186. |TAP   |06|******|X     |2|Transfer to CCR        |P=A         |
  187. |TBA   |17|--**0-|X     |2|Transfer accumulators  |A=B         |
  188. |TPA   |07|------|X     |2|Transfer from CCR      |A=P         |
  189. |TST  s|7D|--**00| XX   |6|Test                   |s           |
  190. |TSTA  |4D|--**00|X     |2|Test accumulator       |A           |
  191. |TSTB  |5D|--**00|X     |2|Test accumulator       |B           |
  192. |TSX   |30|------|X     |4|Transfer Stack Pointer |X=S         |
  193. |TXS   |35|------|X     |4|Transfer Index Register|S=X         |
  194. |WAI   |3E|-*----|X     |9|Wait for Interrupt     |-[S]={regs} |
  195. |---------+------+------+-+------------------------------------|
  196. | CCR     |-*01? |      | |Unaffect/affected/reset/set/unknown |
  197. | H       |H     |      | |Half carry (Bit 5)                  |
  198. | I       | I    |      | |Interrupt mask (Bit 4)              |
  199. | N       |  N   |      | |Negative (Bit 3)                    |
  200. | Z       |   Z  |      | |Zero (Bit 2)                        |
  201. | V       |    V |      | |Overflow (Bit 1)                    |
  202. | C       |     C|      | |Carry (Bit 0)                       |
  203. |----------------+------+-+------------------------------------|
  204. |                |I     | |Inherent                            |
  205. | nn,E           | E    | |Extended (Op=E, ~s=e)               |
  206. | nn,X           |  X   | |Index (Op=E-10H, ~s=e+1, JSR ~s=e-1)|
  207. | n,D            |   D  | |Direct (Op=E-20H, ~s=e-1)           |
  208. | #n             |    # | |Immediate (8-bit, Op=E-30H, ~s=e-2) |
  209. | #nn            |    * | |Immediate (16-bit, Op=E-30H, ~s=e-2)|
  210. | a              |     R| |Relative (PC=PC+2+offset)           |
  211. |-------------------------+------------------------------------|
  212. |DIRECT                   |Direct addressing mode              |
  213. |EXTEND                   |Extended addressing mode            |
  214. |FCB      n               |Form Constant Byte                  |
  215. |FCC      'string'        |Form Constant Characters            |
  216. |FDB      nn              |Form Double Byte                    |
  217. |RMB      nn              |Reserve Memory Bytes                |
  218. |-------------------------+------------------------------------|
  219. | A  B                    |Accumulators (8-bit)                |
  220. | P                       |Condition Code Register (CCR, 8-bit)|
  221. | PC                      |Program Counter (16-bit)            |
  222. | S                       |Stack Pointer (16-bit)              |
  223. | X                       |Index Register (16-bit)             |
  224. |-------------------------+------------------------------------|
  225. | a                       |Relative address (-125 to +129)     |
  226. | d  s                    |Destination/source                  |
  227. | n  nn                   |8/16-bit expression (0 to 255/65535)|
  228. | +  -                    |Add/subtract                        |
  229. | *  /                    |Multiply/divide                     |
  230. | &  ~                    |Logical AND/NOT                     |
  231. | v  x                    |Logical inclusive/exclusive OR      |
  232. | <-  ->                  |Rotate left/right                   |
  233. | [ ]  [ ]+  -[ ]         |Indirect address/increment/decrement|
  234. | { } {regs}              |Combined operands/{PC,X,A,B,P}      |
  235. |-------------------------+------------------------------------|
  236. | FFF8H to FFF9H          |Hardware interrupt vector           |
  237. | FFFAH to FFFBH          |SWI instruction interrupt vector    |
  238. | FFFCH to FFFDH          |Non-maskable interrupt vector       |
  239. | FFFEH to FFFFH          |Reset vector                        |
  240. ----------------------------------------------------------------
  241.