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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                           Motorola                           |
  5. |                                                              |
  6. |         666      88888      000       000      88888         |
  7. |        6        8     8    0   0     0   0    8     8        |
  8. |       6         8     8   0   0 0   0   0 0   8     8        |
  9. |       666666     88888    0  0  0   0  0  0    88888         |
  10. |       6     6   8     8   0 0   0   0 0   0   8     8        |
  11. |       6     6   8     8    0   0     0   0    8     8        |
  12. |        66666     88888      000       000      88888         |
  13. |                                                              |
  14. |        68008 MICROPROCESSOR Instruction Set Summary          |
  15. |                                                              |
  16. |                    _________    _________                    |
  17. |                  _|         \__/         |_                  |
  18. |          <-- A3 |_|1                   48|_| A2 -->          |
  19. |                  _|                      |_                  |
  20. |          <-- A4 |_|2                   47|_| A1 -->          |
  21. |                  _|                      |_                  |
  22. |          <-- A5 |_|3                   46|_| A0 -->          |
  23. |                  _|                      |_                  |
  24. |          <-- A6 |_|4                   45|_| FC0 -->         |
  25. |                  _|                      |_                  |
  26. |          <-- A7 |_|5                   44|_| FC1 -->         |
  27. |                  _|                      |_                  |
  28. |          <-- A8 |_|6                   43|_| FC2 -->         |
  29. |                  _|                      |_  ____ _          |
  30. |          <-- A9 |_|7                   42|_| IPL2/0 <--      |
  31. |                  _|                      |_  ____            |
  32. |         <-- A10 |_|8                   41|_| IPL1 <--        |
  33. |                  _|                      |_  ____            |
  34. |         <-- A11 |_|9                   40|_| BERR <--        |
  35. |                  _|                      |_  ___             |
  36. |         <-- A12 |_|10                  39|_| VPA <--         |
  37. |                  _|                      |_                  |
  38. |         <-- A13 |_|11                  38|_| E -->           |
  39. |                  _|                      |_  _____           |
  40. |         <-- A14 |_|12      68008       37|_| RESET <-->      |
  41. |                  _|                      |_  ____            |
  42. |             Vcc |_|13                  36|_| HALT <-->       |
  43. |                  _|                      |_                  |
  44. |         <-- A15 |_|14                  35|_| GND             |
  45. |                  _|                      |_                  |
  46. |             GND |_|15                  34|_| CLK <--         |
  47. |                  _|                      |_  __              |
  48. |         <-- A16 |_|16                  33|_| BR <--          |
  49. |                  _|                      |_  __              |
  50. |         <-- A17 |_|17                  32|_| BG -->          |
  51. |                  _|                      |_  _____           |
  52. |         <-- A18 |_|18                  31|_| DTACK -->       |
  53. |                  _|                      |_    _             |
  54. |         <-- A19 |_|19                  30|_| R/W -->         |
  55. |                  _|                      |_  __              |
  56. |         <--> D7 |_|20                  29|_| DS -->          |
  57. |                  _|                      |_  __              |
  58. |         <--> D6 |_|21                  28|_| AS -->          |
  59. |                  _|                      |_                  |
  60. |         <--> D5 |_|22                  27|_| D0 <-->         |
  61. |                  _|                      |_                  |
  62. |         <--> D4 |_|23                  26|_| D1 <-->         |
  63. |                  _|                      |_                  |
  64. |         <--> D3 |_|24                  25|_| D2 <-->         |
  65. |                   |______________________|                   |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        November 1984                                  |
  78. |Updated        April 1985                                     |
  79. |Issue          1.1                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemonic   |XNZVC|BWL|Description           |Notes            |
  83. |-----------+-----+---+----------------------+-----------------|
  84. |ABCD  s,d  |*?*?*|X  |Add BCD format        |d=BCD{d+s+X}     |
  85. |ADD   s,d  |*****|XXX|Add binary            |d=d+s            |
  86. |ADDA  s,An |-----| XX|Add Address           |An=An+s          |
  87. |ADDI  #e,d |*****|XXX|Add Immediate         |d=d+e            |
  88. |ADDQ  #q,d |*****|XXX|Add Quick             |d=d+q            |
  89. |ADDX  s,d  |*****|XXX|Add Extended          |d=d+s+X          |
  90. |AND   s,d  |-**00|XXX|Logical AND           |d=d&s            |
  91. |ANDI  #e,d |-**00|XXX|Logical AND Immediate |d=d&e            |
  92. |ASlr  d    |*****|XXX|Arithmetic Shift      |d=d*2 or d=d/2   |
  93. |Bcc   l    |-----|XX |Branch conditionally  |If cc BRA        |
  94. |BCHG  s,d  |--*--| XX|Bit test and Change   |BTST,d<s>=Z      |
  95. |BCLR  d    |--*--| XX|Bit test and Clear    |BTST,d<s>=0      |
  96. |BRA   l    |-----|XX |Branch Always         |PC=l             |
  97. |BSET  d    |--*--| XX|Bit test and Set      |BTST,d<s>=1      |
  98. |BSR   l    |-----|XX |Branch to Subroutine  |-[SP]=PC,PC=l    |
  99. |BTST  d    |--*--| XX|Bit Test              |Z=~d<s>          |
  100. |CHK   s,Dn |-*???| X |Check register        |If 0>Dn>s $[18H] |
  101. |CLR   d    |-0100|XXX|Clear operand         |d=0              |
  102. |CMP   s,Dn |-****|XXX|Compare               |Dn-s             |
  103. |CMPA  s,An |-****|XXX|Compare Address       |An-s             |
  104. |CMPI  #e,d |-****|XXX|Compare Immediate     |d-e              |
  105. |CMPM  s,d  |-****|XXX|Compare Memory        |d-s              |
  106. |DBcc  Dn,l |-----|   |Decrement and Branch  |If~cc&Dn-1~-1 BRA|
  107. |DIVS  s,Dn |-***0| X |Signed Division       |Dn={Dn%s,Dn/s}   |
  108. |DIVU  s,Dn |-***0| X |Unsigned Division     |Dn={Dn%s,Dn/s}   |
  109. |EOR   Dn,d |-**00|XXX|Exclusive OR          |d=dxDn           |
  110. |EORI  #e,d |-**00|XXX|Exclusive OR Immediate|d=dxe            |
  111. |EXG   r,r  |-----|  X|Exchange registers    |r<->r            |
  112. |EXT   Dn   |-**00| XX|Extend sign           |Dn<hi>=Dn<7or15> |
  113. |JMP   d    |-----|   |Jump                  |PC=d             |
  114. |JSR   d    |-----|   |Jump to Subroutine    |-[SP]=PC,PC=d    |
  115. |LEA   s,An |-----|  X|Load Effective Address|An=EA{s}         |
  116. |LINK An,#nn|-----|   |Link and allocate     |-[SP]=An=SP=SP+nn|
  117. |LSlr  d    |***0*|XXX|Logical Shift         |d=->{C,d,0}<-    |
  118. |MOVE  s,d  |-**00|XXX|Move data             |d=s              |
  119. |MOVE  s,CCR|*****| X |Move to CCR           |CCR=s            |
  120. |MOVE  s,SR |*****| X |Move to SR            |SR=s             |
  121. |MOVE  SR,d |-----| X |Move from SR          |d=SR             |
  122. |MOVE USP,An|-----|  X|Move User SP          |USP=An or An=USP |
  123. |MOVEA s,An |-----| XX|Move Address          |An=s             |
  124. |MOVEM s,d  |-----| XX|Move Multiple register|rr=s or d=rr     |
  125. |MOVEP s,d  |-----| XX|Move Peripheral data  |d=Dn or Dn=s     |
  126. |MOVEQ #q,d |-**00|  X|Move Quick            |d=q              |
  127. |MULS  s,Dn |-**00| X |Signed Multiply       |Dn<0:31>=Dn*s    |
  128. |MULU  s,Dn |-**00| X |Unsigned Multiply     |Dn<0:31>=Dn*s    |
  129. |NBCD  d    |*?*?*|X  |Negate BCD format     |d=BCD{-d-X}      |
  130. |NEG   d    |*****|XXX|Negate                |d=-d             |
  131. |NEGX  d    |*****|XXX|Negate with Extend    |d=-d-X           |
  132. |NOP        |-----|   |No Operation          |                 |
  133. |NOT   d    |-**00|XXX|Logical NOT           |d=~d             |
  134. |OR    s,d  |-**00|XXX|Inclusive OR          |d=dvs            |
  135. |ORI   #e,d |-**00|XXX|Inclusive OR Immediate|d=dve            |
  136. |PEA   s    |-----|  X|Push Effective Address|-[SP]=EA{s}      |
  137. |RESET      |-----|   |Reset external devices|Reset line=0     |
  138. |ROlr  d    |-**0*|XXX|Rotate                |d=->{d}<-        |
  139. |ROXlr d    |***0*|XXX|Rotate with Extend    |d=->{d}<-,X=C    |
  140. |RTE        |*****|   |Return from Exception |SR=[SSP]+,RTS    |
  141. |RTR        |*****|   |Return and Restore    |SR<0:4>=[SP]+,RTS|
  142. |RTS        |-----|   |Return from Subroutine|PC=[SP]+         |
  143. |SBCD  s,d  |*?*?*|X  |Subtract BCD format   |d=BCD{d-s-X}     |
  144. |Scc   d    |-----|X  |Set conditionally     |d=0 or d=-1      |
  145. |STOP  #nn  |*****|   |Load status and Stop  |SR=nn, wait      |
  146. |SUB   s,d  |*****|XXX|Subtract binary       |d=d-s            |
  147. |SUBA  s,An |-----| XX|Subtract Address      |An=An-s          |
  148. |SUBI  #e,d |*****|XXX|Subtract Immediate    |d=d-e            |
  149. |SUBQ  #q,d |*****|XXX|Subtract Quick        |d=d-q            |
  150. |SUBX  s,d  |*****|XXX|Subtract with Extend  |d=d-s-X          |
  151. |SWAP  Dn   |-**00| X |Swap register halves  |Dn<hi><->Dn<lo>  |
  152. |TAS   d    |-**00|X  |Test And Set          |d<7>=1           |
  153. |TRAP  #n   |-----|   |Trap          (n=0-15)|$[80H+4*n]       |
  154. |TRAPV      |-----|   |Trap on Overflow      |If V=1 $[1CH]    |
  155. |TST   d    |-**00|XXX|Test                  |d                |
  156. |UNLK  An   |-----|   |Unlink                |SP=An,An=[SP]+   |
  157. |-----------------+---+----------------------------------------|
  158. |DC e(,...)       |XXX|Define Constant                         |
  159. |DS e             |XXX|Define Storage                          |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemonic   |XNZVC|BWL|Description                             |
  163. |-----------+-----+---+----------------------------------------|
  164. | CCR       |-*01?|   |Unaffected/affected/reset/set/unknown   |
  165. | T         |     |   |Trace mode flag (Bit 15)                |
  166. | S         |     |   |Supervisor/user mode select (Bit 13)    |
  167. | In        |     |   |Interrupt mask flag #n (Bits 8-10,n=0-2)|
  168. | X         |X    |   |Extend flag (Bit 4)                     |
  169. | N         | N   |   |Negative flag (Bit 3)                   |
  170. | Z         |  Z  |   |Zero flag (Bit 2)                       |
  171. | V         |   V |   |Overflow flag (Bit 1)                   |
  172. | C         |    C|   |Carry flag (Bit 0)                      |
  173. |-----------------+---+----------------------------------------|
  174. | .B              |X  |Byte attribute (8-bit, .S for branch)   |
  175. | .W              | X |Word attribute (16-bit)                 |
  176. | .L              |  X|Long word attribute (32-bit)            |
  177. |---------------------+----------------------------------------|
  178. | Dn                  |Data register direct addressing         |
  179. | An                  |Address register direct addressing      |
  180. | [An]                |Register indirect addressing            |
  181. | [An]+               |Post-increment register indirect addr.  |
  182. | -[An]               |Pre-decrement register indirect addr.   |
  183. | n[An]               |Offset register indirect addressing     |
  184. | n[An,r]             |Index register indirect addressing      |
  185. | nn                  |Short absolute data addressing          |
  186. | nnnn                |Long absolute data addressing           |
  187. | nn                  |Program counter relative addressing     |
  188. | nn[r]               |Program counter with index addressing   |
  189. | #e                  |Immediate data addressing               |
  190. |---------------------+----------------------------------------|
  191. | An                  |Address register (16/32-bit, n=0-7)     |
  192. | CCR                 |Condition Code Register (8-bit, low SR) |
  193. | Dn                  |Data register (8/16/32-bit, n=0-7)      |
  194. | PC                  |Program Counter (24-bit)                |
  195. | SP                  |Active Stack Pointer (equivalent to A7) |
  196. | SR                  |Status Register (16-bit)                |
  197. | SSP                 |Supervisor Stack Pointer (32-bit)       |
  198. | USP                 |User Stack Pointer (32-bit)             |
  199. |---------------------+----------------------------------------|
  200. | BCD{ }              |Binary Coded Decimal value of operand   |
  201. | EA{ }               |Effective Address of operand            |
  202. | cc                  |Condition = (T/F/HI/LS/CC/CS/NE/EQ/     |
  203. |                     |           VC/VS/PL/MI/GE/LT/GT/LE)     |
  204. | d  s                |Destination/source                      |
  205. | e  n  nn  nnnn      |Any/8-bit/16-bit/32-bit expression      |
  206. | l                   |Branch displacement label (8/16-bit)    |
  207. | lr                  |Left/right direction = (L/R)            |
  208. | q                   |Quick expression (1-8)                  |
  209. | r                   |Any register An or Dn                   |
  210. | rr                  |Multiple registers (-=range,/=separator)|
  211. | +  -  *  /  %       |Add/subtract/multiply/divide/remainder  |
  212. | &  ~  v  x          |AND/NOT/inclusive OR/exclusive OR       |
  213. | ->{ }<-             |Rotate operand(s) left or right         |
  214. | <->                 |Exchange operands                       |
  215. | [ ]                 |Indirect addressing                     |
  216. | -[ ]  [ ]+          |Autoincrement/decrement indirect address|
  217. | < >   < : >         |Bit number/bit range                    |
  218. | <hi>  <lo>          |High half/low half of value             |
  219. | { }   { , }         |Combination of operands                 |
  220. | $                   |Software trap -[SP]=PC,-[SP]=SR,PC=...  |
  221. |---------------------+----------------------------------------|
  222. | 0000H to 0007H      |Reset vector (initial SSP and PC)  (0-1)|
  223. | 0008H to 000BH      |Bus error vector                     (2)|
  224. | 000CH to 000FH      |Address error vector                 (3)|
  225. | 0010H to 0013H      |Illegal instruction vector           (4)|
  226. | 0014H to 0017H      |Zero divide vector                   (5)|
  227. | 0018H to 001BH      |CHK instruction vector               (6)|
  228. | 001CH to 001FH      |TRAPV instruction vector             (7)|
  229. | 0020H to 0023H      |Privilege violation vector           (8)|
  230. | 0024H to 0027H      |Trace vector                         (9)|
  231. | 0028H to 002FH      |Line 1010/1111 emulator vectors  (10-11)|
  232. | 0030H to 003BH      |Unassigned (reserved)            (12-14)|
  233. | 003CH to 003FH      |Uninitialised interrupt vector      (15)|
  234. | 0040H to 005FH      |Unassigned (reserved)            (16-23)|
  235. | 0060H to 0063H      |Spurious interrupt vector           (24)|
  236. | 0064H to 007FH      |Level 1-7 interrupt auto-vectors (25-31)|
  237. | 0080H to 00BFH      |TRAP #0-15 instruction vectors   (32-47)|
  238. | 00C0H to 00FFH      |Unassigned (reserved)            (48-63)|
  239. | 0100H to 03FFH      |User interrupt vectors          (64-255)|
  240. ----------------------------------------------------------------
  241.