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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                           Rockwell                           |
  5. |                                                              |
  6. |              666     5555555     000     X     X             |
  7. |             6        5          0   0     X   X              |
  8. |            6         5         0   0 0     X X               |
  9. |            666666    555555    0  0  0      X                |
  10. |            6     6         5   0 0   0     X X               |
  11. |            6     6         5    0   0     X   X              |
  12. |             66666    555555      000     X     X             |
  13. |                                                              |
  14. |     6501/2/3/4/5 MICROPROCESSOR Instruction Set Summary      |
  15. |                                                              |
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  35. |                 M     M    OOOOO     SSSSS                   |
  36. |                 MM   MM   O     O   S     S                  |
  37. |                 M M M M   O     O   S                        |
  38. |                 M  M  M   O     O    SSSSS                   |
  39. |                 M     M   O     O         S                  |
  40. |                 M     M   O     O   S     S                  |
  41. |                 M     M    OOOOO     SSSSS                   |
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  64. |                                                              |
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  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        September 1981                                 |
  78. |Updated        April 1985                                     |
  79. |Issue          1.3                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnem.|Op|NVBDIZC|A#ZBIRX@|~|Description           |Notes      |
  83. |-----+--+-------+--------+-+----------------------+-----------|
  84. |ADC s|6D|**---**| XxX  X |4|Add with Carry        |A=A+s+C   %|
  85. |AND s|2D|*----*-| XxX  X |4|Logical AND           |A=A&s     %|
  86. |ASL d|0E|*----**|  xx    |6|Arithmetic Shift Left |d={C,d,0}<-|
  87. |ASLA |0A|*----**|X       |2|Arithmetic Shift Left |A={C,d,0}<-|
  88. |BCC a|90|-------|     X  |2|Branch if Carry Clear |If C=0(4~)%|
  89. |BCS a|B0|-------|     X  |2|Branch if Carry Set   |If C=1(4~)%|
  90. |BEQ a|F0|-------|     X  |2|Branch if Equal       |If Z=1(4~)%|
  91. |BIT s|2C|**---*-|  **    |4|Bit Test              |A&s        |
  92. |BMI a|30|-------|     X  |2|Branch if Minus       |If N=1(4~)%|
  93. |BNE a|D0|-------|     X  |2|Branch if Not Equal   |If Z=0(4~)%|
  94. |BPL a|10|-------|     X  |2|Branch if Plus        |If N=0(4~)%|
  95. |BRK  |00|--+-1--|    X   |7|Break  (-[S]={PC+2,P})|PC=[FFFEH] |
  96. |BVC a|50|-------|     X  |2|Branch if Overflow Clr|If V=0(4~)%|
  97. |BVS a|70|-------|     X  |2|Branch if Overflow Set|If V=1(4~)%|
  98. |CLC  |18|------0|    X   |2|Clear Carry flag      |C=0        |
  99. |CLD  |D8|---0---|    X   |2|Clear Decimal mode    |D=0        |
  100. |CLI  |58|----0--|    X   |2|Clear Int. disable    |I=0        |
  101. |CLV  |B8|-0-----|    X   |2|Clear Overflow flag   |V=0        |
  102. |CMP s|CD|*----**| XxX  X |4|Compare               |A-s        |
  103. |CPX s|EC|*----**| X**    |4|Compare index register|X-s        |
  104. |CPY s|CC|*----**| X**    |4|Compare index register|Y-s        |
  105. |DEC d|CE|*----*-|  xx    |6|Decrement             |d=d-1      |
  106. |DEX  |CA|*----*-|    X   |2|Decrement index reg.  |X=X-1      |
  107. |DEY  |88|*----*-|    X   |2|Decrement index reg.  |Y=Y-1      |
  108. |EOR s|4D|*----*-| XxX  X |4|Logical Exclusive OR  |A=Axs     %|
  109. |INC d|EE|*----*-|  xx    |6|Increment             |d=d+1      |
  110. |INX  |E8|*----*-|    X   |2|Increment index reg.  |X=X+1      |
  111. |INY  |C8|*----*-|    X   |2|Increment index reg.  |Y=Y+1      |
  112. |JMP s|4C|-------|   *   X|3|Jump                  |          !|
  113. |JSR s|20|-------|   *    |6|Jump to Subroutine    |-[S]=PC+2,!|
  114. |LDA s|AD|*----*-| XxX  X |4|Load Accumulator      |A=s       %|
  115. |LDX s|AE|*----*-| Xyy    |4|Load index register   |X=s       %|
  116. |LDY s|AC|*----*-| Xxx    |4|Load index register   |Y=s       %|
  117. |LSR d|4E|0----**|  xx    |6|Logical Shift Right   |d=->{0,d,C}|
  118. |LSRA |4A|0----**|X       |2|Logical Shift Right   |A=->{0,A,C}|
  119. |NOP  |EA|-------|    X   |2|No Operation          |           |
  120. |ORA s|0D|*----*-| XxX  X |4|Logical Inclusive OR  |A=Avs      |
  121. |PHA  |48|-------|    X   |3|Push Accumulator      |-[S]=A     |
  122. |PHP  |08|-------|    X   |3|Push status register  |-[S]=P     |
  123. |PLA  |68|-------|    X   |4|Pull Accumulator      |A=[S]+     |
  124. |PLP  |28|*******|    X   |4|Pull Status Register  |P=[S]+     |
  125. |ROL d|2E|*----**|  xx    |6|Rotate Left           |d={C,d}<-  |
  126. |ROLA |2A|*----**|X       |2|Rotate Left Acc.      |A={C,A}<-  |
  127. |ROR d|6E|*----**|  xx    |6|Rotate Right          |d=->{C,d}  |
  128. |RORA |6A|*----**|X       |2|Rotate Right Acc.     |A=->{C,A}  |
  129. |RTI  |40|*******|    X   |6|Return from Interrupt |{PC,P}=[S]+|
  130. |RTS  |60|-------|    X   |6|Return from Subroutine|PC={[S]+}+1|
  131. |SBC s|ED|*----**| XxX  X |4|Subtract with Carry   |A=A-s-C   %|
  132. |SEC  |38|------1|    X   |2|Set Carry flag        |C=1        |
  133. |SED  |F8|---1---|    X   |2|Set Decimal mode      |D=1        |
  134. |SEI  |78|----1--|    X   |2|Set Interrupt disable |I=1        |
  135. |STA d|8D|-------|  xX  X |4|Store Accumulator     |d=A        |
  136. |STX d|8E|-------|  y*    |4|Store index register  |d=X        |
  137. |STY d|8C|-------|  x*    |4|Store index register  |d=Y        |
  138. |TAX  |AA|*----*-|    X   |2|Transfer Accumulator  |X=A        |
  139. |TAY  |A8|*----*-|    X   |2|Transfer Accumulator  |Y=A        |
  140. |TSX  |BA|*----*-|    X   |2|Transfer Stack Pointer|X=S        |
  141. |TXA  |8A|*----*-|    X   |2|Transfer Index Reg.   |A=X        |
  142. |TXS  |9A|-------|    X   |2|Transfer Index Reg.   |S=X        |
  143. |TYA  |98|*----*-|    X   |2|Transfer Index Reg.   |A=Y        |
  144. |-----+--+-------+--------+-+----------------------------------|
  145. |     |XX|       |        |X|Hexadecimal opcode/no. of cycles  |
  146. |--------+-------+--------+-+----------------------------------|
  147. |        |-      |        | |Flag unaffected                   |
  148. |        |*      |        | |Flag affected                     |
  149. |        |0      |        | |Flag reset                        |
  150. |        |1      |        | |Flag set                          |
  151. |        |+      |        | |Flag set on stack                 |
  152. |--------+-------+--------+-+----------------------------------|
  153. | N      |N      |        | |Negative status (Bit 7)           |
  154. | V      | V     |        | |Overflow status (Bit 6)           |
  155. | B      |  B    |        | |Break command indicator (Bit 4)   |
  156. | D      |   D   |        | |Decimal mode control (Bit 3)      |
  157. | I      |    I  |        | |Interrupt disable control (Bit 2) |
  158. | Z      |     Z |        | |Zero status (Bit 1)               |
  159. | C      |      C|        | |Carry status (Bit 0)              |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemonic        |A#ZBIRX@|Description             |Opcode| ~s |
  163. |----------------+--------+------------------------+------+----|
  164. |                |X       |All mode(s) valid       |      |    |
  165. |                |*       |Non-indexed mode valid  |      |    |
  166. |                |x       |X/non-indexed mode valid|      |    |
  167. |                |y       |Y/non-indexed mode valid|      |    |
  168. |----------------+--------+------------------------+------+----|
  169. |                |        |Add XXH to opcode       | +XXH |    |
  170. |                |        |Subtract XXH from opcode| -XXH |    |
  171. |                |        |Add X to no. of cycles  |      | +X |
  172. |                |        |Subtract X from cycles  |      | -X |
  173. |----------------+--------+------------------------+------+----|
  174. | A              |A       |Accumulator             |      |    |
  175. | #n             | #      |Immediate               | -04H | -2 |
  176. | <n             |  *     |Zero page               | -08H | -1 |
  177. | n              |  *     |Zero page (DIRECT mode) | -08H | -1 |
  178. | n,X            |  x     |Zero page indexed (X)   | +08H | +0 |
  179. | n,Y            |  y     |Zero Page indexed (Y)   | +08H | +0 |
  180. | >nn            |   *    |Absolute                | +00H | +0 |
  181. | nn             |   *    |Absolute (EXTEND mode)  | +00H | +0 |
  182. | nn,X           |   x    |Absolute indexed (X)    | +10H | +0 |
  183. | nn,Y           |   y    |Absolute indexed (Y)    | +0CH | +0 |
  184. | LDX nn,Y       |   y    | ditto                  | +10H | +0 |
  185. |                |    I   |Implicit                |      |    |
  186. | a              |     R  |Relative(PC=PC+1+offset)|      | +2 |
  187. | [nn,X]         |      x |Indexed indirect (X)    | -0CH | +2 |
  188. | [nn],Y         |      y |Indirect indexed (Y)    | +04H | +1 |
  189. | [nn]           |       @|Absolute indirect       | +20H | +2 |
  190. |-------------------------+------------------------------------|
  191. |BYTE     n(,...)         |Byte(s) (8-bit)                     |
  192. |BYTE     'string'(,...)  |Byte text string(s)                 |
  193. |DIRECT                   |Zero page addressing mode           |
  194. |EXTEND                   |Absolute addressing mode            |
  195. |RMB      nn(,...)        |Reserve Memory Bytes                |
  196. |WORD     nn(,...)        |Word(s) (16-bit)                    |
  197. |-------------------------+------------------------------------|
  198. | A                       |Accumulator (8-bit)                 |
  199. | P                       |Status Register (8-bit)             |
  200. | PC                      |Program Counter (16-bit)            |
  201. | S                       |Stack Pointer (9-bit, MSB=1)        |
  202. | X  Y                    |Index Registers X and Y (8-bit)     |
  203. |-------------------------+------------------------------------|
  204. | a                       |Relative Address (-128 to +127)     |
  205. | d                       |Destination                         |
  206. | n                       |8-bit expression (0 to 255)         |
  207. | nn                      |16-bit expression (0 to 65535)      |
  208. | s                       |Source                              |
  209. | string                  |String of ASCII characters          |
  210. |-------------------------+------------------------------------|
  211. | +                       |Arithmetic addition                 |
  212. | -                       |Arithmetic subtraction              |
  213. | *                       |Arithmetic multiplication           |
  214. | /                       |Arithmetic division                 |
  215. | &                       |Logical AND                         |
  216. | ~                       |Logical NOT                         |
  217. | v                       |Logical inclusive OR                |
  218. | x                       |Logical exclusive OR                |
  219. | <-                      |Rotate left                         |
  220. | ->                      |Rotate right                        |
  221. | [ ]                     |Indirect addressing                 |
  222. | [ ]+                    |Indirect addressing, auto-increment |
  223. | -[ ]                    |Auto-decrement, indirect addressing |
  224. | { }                     |Combination of operands             |
  225. | $                       |Program counter content             |
  226. | %                       |~s = ~s+1 if crossing page boundary |
  227. | !                       |PC = effective address of source    |
  228. |-------------------------+------------------------------------|
  229. |0000H to 00FFH           |Page 0 (see zero page addressing)   |
  230. |0100H to 01FFH           |Page 1 (stack area, 01FFH = start)  |
  231. |XX00H to XXFFH           |Page n (where n=XXH)                |
  232. |FFFAH to FFFBH           |Non maskable interrupt (NMI) vector |
  233. |FFFCH to FFFDH           |Reset (RES) vector                  |
  234. |FFFEH to FFFFH           |Interrupt Request (IRQ) vector      |
  235. |FFFEH to FFFFH           |Break command vector (see BRK)      |
  236. |-------------------------+------------------------------------|
  237. | 6501/6502               |16 address lines, 65536 bytes max.  |
  238. | 6503/6505               |13 address lines, 8192 bytes max.   |
  239. | 6504                    |12 address lines, 4096 bytes max.   |
  240. ----------------------------------------------------------------
  241.