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  1. ----------------------------------------------------------------
  2. |                                                              |
  3. |                                                              |
  4. |                          Signetics                           |
  5. |                                                              |
  6. |             22222      666     5555555     000               |
  7. |            2     2    6        5          0   0              |
  8. |                 2    6         5         0   0 0             |
  9. |              222     666666    555555    0  0  0             |
  10. |             2        6     6         5   0 0   0             |
  11. |            2         6     6         5    0   0              |
  12. |            2222222    66666    555555      000               |
  13. |                                                              |
  14. |         2650 MICROPROCESSOR Instruction Set Summary          |
  15. |                                                              |
  16. |                                                              |
  17. |                                                              |
  18. |                                                              |
  19. |                                                              |
  20. |                    _________    _________                    |
  21. |                  _|         \__/         |_                  |
  22. |       --> SENSE |_|1                   40|_| FLAG -->        |
  23. |                  _|                      |_                  |
  24. |         <-- A12 |_|2                   39|_| Vcc             |
  25. |                  _|                      |_                  |
  26. |         <-- A11 |_|3                   38|_| CLOCK <--       |
  27. |                  _|                      |_  _____           |
  28. |         <-- A10 |_|4                   37|_| PAUSE <--       |
  29. |                  _|                      |_  _____           |
  30. |          <-- A9 |_|5                   36|_| OPACK <--       |
  31. |                  _|                      |_      ____        |
  32. |          <-- A8 |_|6                   35|_| RUN/WAIT -->    |
  33. |                  _|                      |_                  |
  34. |          <-- A7 |_|7                   34|_| INTACK -->      |
  35. |                  _|                      |_                  |
  36. |          <-- A6 |_|8                   33|_| D0 <-->         |
  37. |                  _|                      |_                  |
  38. |          <-- A5 |_|9                   32|_| D1 <-->         |
  39. |                  _|                      |_                  |
  40. |          <-- A4 |_|10       2650A      31|_| D2 <-->         |
  41. |                  _|                      |_                  |
  42. |          <-- A3 |_|11                  30|_| D3 <-->         |
  43. |                  _|                      |_                  |
  44. |          <-- A2 |_|12                  29|_| D4 <-->         |
  45. |                  _|                      |_                  |
  46. |          <-- A1 |_|13                  28|_| D5 <-->         |
  47. |                  _|                      |_                  |
  48. |          <-- A0 |_|14                  27|_| D6 <-->         |
  49. |           _____  _|                      |_                  |
  50. |       --> ADREN |_|15                  26|_| D7 <-->         |
  51. |                  _|                      |_  ______          |
  52. |       --> RESET |_|16                  25|_| DBUSEN <--      |
  53. |          ______  _|                      |_                  |
  54. |      --> INTREQ |_|17                  24|_| OPREQ -->       |
  55. |               _  _|                      |_  _               |
  56. |     <-- A14-D/C |_|18                  23|_| R/W -->         |
  57. |              __  _|                      |_                  |
  58. |    <-- A13-E/NE |_|19                  22|_| WRP -->         |
  59. |              __  _|                      |_                  |
  60. |        <-- M/IO |_|20                  21|_| GND             |
  61. |                   |______________________|                   |
  62. |                                                              |
  63. |                                                              |
  64. |                                                              |
  65. |                                                              |
  66. |                                                              |
  67. |                                                              |
  68. |Written by     Jonathan Bowen                                 |
  69. |               Programming Research Group                     |
  70. |               Oxford University Computing Laboratory         |
  71. |               8-11 Keble Road                                |
  72. |               Oxford OX1 3QD                                 |
  73. |               England                                        |
  74. |                                                              |
  75. |               Tel +44-865-273840                             |
  76. |                                                              |
  77. |Created        March 1982                                     |
  78. |Updated        April 1985                                     |
  79. |Issue          1.1                Copyright (C) J.P.Bowen 1985|
  80. ----------------------------------------------------------------
  81. ----------------------------------------------------------------
  82. |Mnemonic|Op|cIOC|~|Description                   |Notes       |
  83. |--------+--+----+-+------------------------------+------------|
  84. |ADDA,r a|8C|****|4|Add Absolute                  |r=r+a       |
  85. |ADDI,r i|84|****|2|Add Immediate                 |r=r+i       |
  86. |ADDR,r l|88|****|3|Add Relative                  |r=r+l       |
  87. |ADDZ,r  |80|****|2|Add to register Zero          |R0=R0+r     |
  88. |ANDA,r a|4C|*---|4|Logical AND Absolute          |r=r&a       |
  89. |ANDI,r i|44|*---|2|Logical AND Immediate         |r=r&i       |
  90. |ANDR,r l|48|*---|3|Logical AND Relative          |r=r&l       |
  91. |ANDZ,r  |40|*---|2|Logical AND register Zero     |R0=R0&r     |
  92. |BCFA,d b|9C|----|3|Branch on Cond. False Absolute|If d#c, PC=b|
  93. |BCFR,d l|98|----|3|Branch on Cond. False Relative|If d#c, PC=l|
  94. |BCTA,d b|1C|----|3|Branch on Cond. True Absolute |If d=c, PC=b|
  95. |BCTR,d l|18|----|3|Branch on Cond. True Relative |If d=c, PC=l|
  96. |BDRA,r b|FC|----|3|Branch on Dec. Reg. Absolute  |r=r-1,if r#0|
  97. |BDRR,r l|F8|----|3|Branch on Dec. Reg. Relative  |r=r-1,if r#0|
  98. |BIRA,r b|DC|----|3|Branch on Inc. Reg. Absolute  |r=r+1,if r#0|
  99. |BIRR,r l|D8|----|3|Branch on Inc. Reg. Relative  |r=r+1,if r#0|
  100. |BRNA,r b|5C|----|3|Branch on Reg. Non-zero Abs.  |If r#0, PC=b|
  101. |BRNR,r l|58|----|3|Branch on Reg. Non-zero Rel.  |If r#0, PC=l|
  102. |BSFA,d b|BC|----|3|Branch to Sub. on False Abs.  |If d#c,calla|
  103. |BSFR,d l|B8|----|3|Branch to Sub. on False Rel.  |If d#c,callr|
  104. |BSNA,r b|7C|----|3|Branch to Sub. on Non-zero Abs|If d#c,calla|
  105. |BSNR,r l|78|----|3|Branch to Sub. on Non-zero Rel|If d#c,callr|
  106. |BSTA,d b|3C|----|3|Branch to Sub. on True Abs.   |If d=c,calla|
  107. |BSTR,d l|38|----|3|Branch to Sub. on True Rel.   |If d=c,callr|
  108. |BSXA   b|BF|----|3|Branch to Sub. Extended Addr. |calla       |
  109. |BXA    b|9F|----|3|Branch to Extended Address    |PC=b        |
  110. |COMA,r a|EC|*---|4|Compare Absolute              |r-a         |
  111. |COMI,r i|E4|*---|2|Compare Immediate             |r-i         |
  112. |COMR,r l|E8|*---|3|Compare Relative              |r-l         |
  113. |COMZ,r  |E0|*---|2|Compare with register Zero    |R0-r        |
  114. |CPSL   i|75|----|3|Clear Program Status Lower    |If i=1,PSL=0|
  115. |CPSU   i|74|----|3|Clear Program Status Upper    |PSU=PSU&(~i)|
  116. |DAR,r   |94|----|3|Decimal Adjust Register       |r=BCD format|
  117. |EORA,r a|2C|*---|4|Logical Exclusive OR Absolute |r=rxa       |
  118. |EORI,r i|24|*---|2|Logical Exclusive OR Immediate|r=rxi       |
  119. |EORR,r l|28|*---|3|Logical Exclusive OR Relative |r=rxl       |
  120. |EORZ,r  |20|*---|2|Logical Exclusive OR reg Zero |R0=R0xr     |
  121. |HALT    |40|----|2|Halt                          |Wait state  |
  122. |IORA,r a|6C|*---|4|Logical Inclusive OR Absolute |r=rva       |
  123. |IORI,r i|64|*---|2|Logical Inclusive OR Immediate|r=rvi       |
  124. |IORR,r l|68|*---|3|Logical Inclusive OR Relative |r=rvl       |
  125. |IORZ,r  |60|*---|2|Logical Inclusive OR reg Zero |R0=R0vr     |
  126. |LODA,r a|0C|*---|4|Load Absolute                 |r=a         |
  127. |LODI,r i|04|*---|2|Load Immediate                |r=i         |
  128. |LODR,r l|08|*---|3|Load Relative                 |r=l         |
  129. |LODZ,r  |00|*---|2|Load register Zero            |R0=r        |
  130. |LPSL    |93|----|2|Load Program Status Lower     |PSL=R0      |
  131. |LPSU    |92|----|2|Load Program Status Upper     |PSU=R0      |
  132. |NOP     |C0|----|2|No Operation                  |            |
  133. |PPSL   i|77|----|3|Preset Program Status Lower   |If i=1,PSL=1|
  134. |PPSU   i|76|----|3|Preset Program Status Upper   |If i=1,PSU=1|
  135. |REDC,r  |30|*---|2|Read Control                  |r=statusNE  |
  136. |REDD,r  |70|*---|2|Read Data                     |r=dataNE    |
  137. |REDE,r p|54|*---|3|Read Extended                 |r=p         |
  138. |RETC,d  |14|----|3|Return on Condition           |If d=c,ret  |
  139. |RETE,d  |34|----|3|Return cond, Enable interrupts|ret,II=0    |
  140. |RRL,r   |D0|----|2|Rotate Register Left          |r=->{rr}    |
  141. |RRR,r   |50|----|2|Rotate Register Right         |r={rr}<-    |
  142. |SPSL    |13|----|2|Store Program Status Lower    |R0=PSL      |
  143. |SPSU    |12|----|2|Store Program Status Upper    |R0=PSU      |
  144. |STRA,r a|CC|----|4|Store Absolute                |a=r         |
  145. |STRR,r l|C8|----|3|Store Relative                |l=r         |
  146. |STRZ,r  |C0|----|2|Store register Zero           |r=R0        |
  147. |SUBA,r a|AC|****|4|Subtract Absolute             |r=r-a       |
  148. |SUBI,r i|A4|****|2|Subtract Immediate            |r=r-i       |
  149. |SUBR,r l|A8|****|3|Subtract Relative             |r=r-l       |
  150. |SUBZ,r  |A0|****|2|Subtract from register Zero   |R0=R0-r     |
  151. |TMI,r  i|F4|*---|3|Test under Mask Immediate     |r&i         |
  152. |TPSL,r i|B5|*---|3|Test Program Status Lower     |i-PSL       |
  153. |TPSU,r i|B4|*---|3|Test Program Status Upper     |i-PSU       |
  154. |WRTC,r  |B0|----|2|Write Control                 |statusNE=r  |
  155. |WRTD,r  |F0|----|2|Write Data                    |dataNE=r    |
  156. |WRTE,r p|D4|----|3|Write Extended                |p=r         |
  157. |ZBRR   l|9B|----|3|Zero page Branch              |PC=l        |
  158. |ZBSR   l|BB|----|3|Zero page Branch to Subroutine|callr       |
  159. |        |XX|    |X|8-bit opcode, machine cycles  |Hexadecimal |
  160. ----------------------------------------------------------------
  161. ----------------------------------------------------------------
  162. |Mnemonic   |cIOC|Description                                  |
  163. |-----------+----+---------------------------------------------|
  164. |           |-   |Unaffected                                   |
  165. |           |*   |Affected                                     |
  166. |           |0   |Reset                                        |
  167. |           |1   |Set                                          |
  168. |           |?   |Unknown                                      |
  169. |-----------+----+---------------------------------------------|
  170. | S         |    |Sense (PSU bit 7)                            |
  171. | F         |    |Flag (PSU bit 6)                             |
  172. | II        |    |Interrupt Inhibit (PSU bit 5)                |
  173. | SP2       |    |Stack Pointer two (PSU bit 2)                |
  174. | SP1       |    |Stack Pointer one (PSU bit 1)                |
  175. | SP0       |    |Stack Pointer zero (PSU bit 0)               |
  176. |-----------+----+---------------------------------------------|
  177. | CC1       |c   |Condition Code one (PSL bit 7)               |
  178. | CC0       |c   |Condition Code zero (PSL bit 6)              |
  179. | IDC       | I  |Inter-Digit Carry status (PSL bit 5)         |
  180. | RS        |    |Register bank Select (R1-R3, PSL bit 4)      |
  181. | WC        |    |With/without Carry (PSL bit 3)               |
  182. | OVF       |  O |Overflow status (PSL bit 2)                  |
  183. | COM       |    |Logical/arithmetic Compare (PSL bit 1)       |
  184. | C         |   C|Carry/borrow status (PSL bit 0)              |
  185. |----------------+---------------------------------------------|
  186. | a              |16-bit extended address                      |
  187. | b              |16-bit absolute address                      |
  188. | c              |2-bit condition codes CC1 and CC0            |
  189. | calla          |[SP]+=PC+3,PC=b                              |
  190. | callr          |[SP]+=PC+2,PC=l                              |
  191. | d              |2-bit immediate data unit                    |
  192. | dataNE         |Non-extended data port                       |
  193. | i              |8-bit immediate data unit                    |
  194. | l              |8-bit relative address                       |
  195. | p              |8-bit I/O port number                        |
  196. | r              |Register Rn (n=0-3)                          |
  197. | ret            |If r#0, PC=[SP]-                             |
  198. | statusNE       |Non-extended status port                     |
  199. |----------------+---------------------------------------------|
  200. | PC             |Program Counter                              |
  201. | PSL            |Program Status Lower (8-bit)                 |
  202. | PSU            |Program Status Upper (8-bit)                 |
  203. | R0             |Register zero - accumulator                  |
  204. | Rn             |Register (n=0-3)                             |
  205. | SP             |Stack pointer                                |
  206. |----------------+---------------------------------------------|
  207. | +              |Arithmetic addition                          |
  208. | -              |Arithmetic subtraction                       |
  209. | *              |Arithmetic multiplication                    |
  210. | /              |Arithmetic division                          |
  211. | &              |Logical AND                                  |
  212. | ~              |Logical NOT                                  |
  213. | v              |Logical inclusive OR                         |
  214. | x              |Logical exclusive OR                         |
  215. | =              |Equal or assignment                          |
  216. | #              |Not equal                                    |
  217. | <-             |Rotate left                                  |
  218. | ->             |Rotate right                                 |
  219. | [ ]            |Indirect addressing                          |
  220. | [ ]+           |Indirect addressing, auto-increment          |
  221. | -[ ]           |Auto-decrement, indirect addressing          |
  222. | { }            |Combination of operands                      |
  223. | {rr}           |If WC=1 then {C,r} else {r}                  |
  224. | -->            |Input pin                                    |
  225. | <--            |Output pin                                   |
  226. | <-->           |Input/output pin                             |
  227. |--------------------------------------------------------------|
  228. |                                                              |
  229. |                                                              |
  230. |                                                              |
  231. |                                                              |
  232. |                                                              |
  233. |                                                              |
  234. |                                                              |
  235. |                                                              |
  236. |                                                              |
  237. |                                                              |
  238. |                                                              |
  239. |                                                              |
  240. ----------------------------------------------------------------
  241.