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Text File  |  1994-07-24  |  11KB  |  218 lines
  1. ATA ID Output Descriptions file
  2.  
  3. Drive #
  4. Indicates the physical disk drive number, either 0 or 1.
  5.  
  6. Model Number
  7. Indicates the actuall model number of the drive as recored in the drive indentification header
  8.  
  9. Serial Number
  10. Indicates the actuall serial number of the drive as recored in the drive indentification header
  11.  
  12. Media type
  13. Indicates whether the drive media is magnetic or non magnetic (eg. optical)
  14.  
  15. Drive type
  16. Valid values are removalbe and non removable
  17.  
  18. Sector formatting
  19. Valid values are MFM encoded or not MFM encoded, with soft or hard sectoring
  20.  
  21. Able to do double Word Transfers
  22.  
  23.  
  24. Maximum Data Transfer Rate
  25. rate > 10 Mbs  
  26. rate > 5Mbs but <= 10Mbs 
  27. rate <= 5Mbs   
  28.  
  29. Controller Buffer Type
  30. 0000h    not specified.
  31. 0001h    a single ported single sector buffer which is not capable of simultaneous data transfers to or from the host and the disk.
  32. 0002h    a dual ported multi-sector buffer capable of simultaneous data transfers to or from the host and the disk.
  33. 0003h    a dual ported multi-sector buffer capable of simultaneous transfers with a read caching capability.
  34.  
  35. Controller Cache Buffer Size
  36. Actual size of on board Cache to the nearest 512 bytes.
  37.  
  38. ECC bytes
  39. The number of Error Correction and control bytes available on a long transfer.  If a value
  40. other than 4 is set, it is unable to determine the current number of bytes used.
  41.  
  42. Maximum Number of Sectors per Interrupt.
  43. The number of sectors currently set to transfer on a READ OR WRITE MULTIPLE command
  44. If value =8, then 8 secotrs worth of data would be transferred at a time.
  45.  
  46. Default Translation Mode (recommended by manufacturer)
  47. The number of user-addressable cylinders, heads, sectors in the default translation mode.
  48.  
  49. Current Translation Mode
  50. How the drive is currently set up.
  51.  
  52. Current BIOS Setup
  53. what the BIOS thinks is going on.  should equal curent translation mode.
  54.  
  55. DMA (Direct Memory Access) transfers supported
  56. Yes or No.
  57.  
  58. LBA (Logical Byte Addressing) supported.
  59. Yes or No.
  60.  
  61. PIO Data Trasnfer Timing Mode
  62. The PIO transfer timing for each ATA device falls into categories which have unique 
  63. parametric timing specifications.  
  64. Valid values are 0, 1, 2 and 3.  See the table below for timing differences.
  65.  
  66.  
  67.                               |<------------ t0 ------------------------>| 
  68.                   _____ __________________________________________       |  
  69.  Address Valid *1 _____X                                          \_________
  70.                        |<-t1->|                           ->| t9  |<-      
  71.                        |      |<----------- t2 ------------>|     |<-t8->| 
  72.                        |      |_____________________________|<---t2i---->|__
  73.  DIOR-/DIOW-      ____________/                             \____________/     
  74.                        |      |                             |
  75.                        |      |                    ____________
  76.  Write Data Valid *2------------------------------<____________>------------
  77.                        |      |                    |<--t3-->|  |          
  78.                        |      |                           ->|t4|<-       
  79.                        |      |                     ____________ ____    
  80.  Read Data Valid  *2-------------------------------<____________X____>------
  81.                        |      |                    |<--t5-->|   |    |     
  82.                      ->|t7|<- |                    |      ->|t6 |<-  |     
  83.                        |  | ->| tA |<-             |          ->|t6Z |<-   
  84.                        |  |__________________________________________
  85.  IOCS16-          ________/        |               |                 \______
  86.                                    |             ->|tR|<-
  87.                    ________________|________________________________________
  88.  IORDY            XXXXXXXXXXXXXXXXX___________________/
  89.  
  90. *1 Drive Address consists of signals CS0-, CS1- and DA2-0          
  91. *2 Data consists of DD0-15 (16-bit) or DD0-7 (8-bit)                   
  92.  
  93.  
  94.  
  95.      +----------------------------------------------------------------------+
  96.      | PIO                                      |Mode 0|Mode 1|Mode 2|Mode 3|
  97.      | timing parameters                        | nsec | nsec | nsec | nsec |
  98. +----+------------------------------------------+------+------+------+------+
  99. | t0 | Cycle time                         (min) | 600  | 383  | 240  | 180  |
  100. | t1 | Address valid to DIOR-/DIOW- setup (min) |  70  |  50  |  30  |  30  |
  101. | t2 | DIOR-/DIOW-      16-bit            (min) | 165  | 125  | 100  |  80  |
  102. |    |   Pulse width     8-bit            (min) | 290  | 290  | 290  |  80  |
  103. | t2i| DIOR-/DIOW- recovery time          (min) |      |      |      |  70  |
  104. | t3 | DIOW- data setup                   (min) |  60  |  45  |  30  |  30  |
  105. | t4 | DIOW- data hold                    (min) |  30  |  20  |  15  |  10  |
  106. | t5 | DIOR- data setup                   (min) |  50  |  35  |  20  |  20  |
  107. | t6 | DIOR- data hold                    (min) |   5  |   5  |   5  |   5  |
  108. | t6Z| DIOR- data tristate (2)            (max) |      |      |      |  30  |
  109. | t7 | Addr valid to IOCS16- assertion    (max) |  90  |  50  |  40  |  30  |
  110. | t8 | Addr valid to IOCS16- negation     (max) |  60  |  45  |  30  |  30  |
  111. | t9 | DIOR-/DIOW- to address valid hold  (min) |  20  |  15  |  10  |  10  |
  112. | tR | Read Data Valid to IORDY active    (min) |      |      |      |   0  |
  113. |    |  (if IORDY initially low after tA)       |      |      |      |      |
  114. +---------------------------------------------------------------------------+
  115.  
  116.                        PIO Data Transfer to/from Drive 
  117.  
  118.  
  119. DMA Data Transfer Timing Mode
  120.  
  121.                     |<----------------------- t0 ----------------------->|   
  122.                  ____________                                         _______
  123.  DMARQ       ___/            \_______________________________________/   |   
  124.                     |<- tC ->|                                           |   
  125.                     |______________________________________________      |___
  126.  DMACK-      _______/                                              \_____/   
  127.                     |<--- tI --->|_________________|<----- tJ -----|     |   
  128.  DIOR-/DIOW- ____________________/                 \_________________________
  129.                     |            |                 |                     |   
  130.                     |            |<------ tD ----->|                     |   
  131.  Read               |                      _________________             |   
  132.  DD0-15      -----------------------------<_________________>----------------
  133.                     |            |<- tE ->|<- tS ->|<- tF ->|            |   
  134.  Write              |                  __________________________        |   
  135.  DD0-15     --------------------------<__________________________>-----------
  136.                     |                 |            |             |       |   
  137.                     |                 |<--- tG --->|<--  tH   -->|       |   
  138.  
  139.      +----------------------------------------------------------+
  140.      | Single word DMA                  | Mode 0| Mode 1| Mode 2|
  141.      | timing parameters                |  nsec |  nsec |  nsec |
  142. +----+----------------------------------+-------+-------+-------|
  143. | t0 | Cycle time                 (min) |  960  |  480  |  240  |
  144. | tC | DMACK to DMREQ delay       (max) |  200  |  100  |   80  |
  145. | tD | DIOR-/DIOW-      16-bit    (min) |  480  |  240  |  120  |
  146. | tE | DIOR- data access          (max) |  250  |  150  |   60  |
  147. | tF | DIOR- data hold            (min) |    5  |    5  |    5  |
  148. | tG | DIOW- data setup           (min) |  250  |  100  |   35  |
  149. | tH | DIOW- data hold            (min) |   50  |   30  |   20  |
  150. | tI | DMACK to DIOR-/DIOW- setup (min) |    0  |    0  |    0  |
  151. | tJ | DIOR-/DIOW- to DMACK hold  (min) |    0  |    0  |    0  |
  152. | tS | DIOR- setup                (min) | tD-tE | tD-tE | tD-tE |
  153. +---------------------------------------------------------------+
  154.  
  155.             Figure 7 - Single Word DMA Data Transfer
  156.  
  157.  
  158.  
  159.  
  160.  
  161.                    |<------------- t0 ------------>|                         
  162.             _____________________________________________ _ _ _ _ _  ________
  163.  DMARQ  ___/                                             \__________/        
  164.                    |                               |<--->|                   
  165.                    |                               |  tL                     
  166.                ___________________________________________________          _
  167.  DMACK- ______/                                                   \________/ 
  168.               |<-->|         |                     |         |               
  169.                 tI |<-- tD ->|<------- tK -------->|         |<-->|          
  170.                    |         |                     |         | tJ |           
  171.  DIOR-             |_________|                     |_________     |           
  172.  DIOW-  ___________/         \_____________________/         \_______________
  173.                    |         |                                    |                 
  174.                    |<--->|   |                                 -->|  |<-tZ          
  175.  READ                 tE  ________ _ _ _ _ _ _ _ _ _ _ _  ___________          
  176.  DD0-15 -----------------<________X_X_X_X_X_X_X_X_X_X_X_X<_______X_X_>-------
  177.                              |    |                                
  178.                              |<-->|                          
  179.                              | tF                             
  180.  WRITE                 ____________  _ _ _ _ _ _ _ _ _ ____________          
  181.  DD0-15 --------------<____________XX_X_X_X_X_X_X_X_X_X____________>---------
  182.                       |<---->|<--->|                                  
  183.                         tG    tH                                            
  184.  
  185.                                                                             
  186.  
  187.       +----------------------------------------+-----------+
  188.       | Multiword DMA              |   Mode 0  |   Mode 1  |
  189.       | timing parameters          |    nsec   |    nsec   |
  190.       |                            | Min | Max | Min | Max |
  191. +-----+----------------------------+-----+-----|-----+-----|
  192. | t0  | Cycle time                 | 480 |     | 150 |     |
  193. | tC  | DMACK to DMREQ delay       |     | --- |     | --- |
  194. | tD  | DIOR-/DIOW-      16-bit    | 215 |     |  80 |     |
  195. | tE  | DIOR- data access          |     | 150 |     |  60 |
  196. | tF  | DIOR- data hold            |   5 |     |   5 |     |
  197. | tFZ | DIOR- to tristate (1)      |     |  20 |     |  25 |
  198. | tG  | DIOW- data setup           | 100 |     |  30 |     |
  199. | tH  | DIOW- data hold            |  20 |     |  15 |     |
  200. | tI  | DMACK to DIOR-/DIOW- setup |   0 |     |   0 |     |
  201. | tJ  | DIOR-/DIOW- to DMACK hold  |  20 |     |   5 |     |
  202. | tKr | DIOR- negated pulse width  |  50 |     |  50 |     |
  203. | tKw | DIOW- negated pulse width  | 215 |     |  50 |     |
  204. | tLr | DIOR- to DMREQ delay       |     | 120 |     |  40 |
  205. | tLw | DIOW- to DMREQ delay       |     |  40 |     |  40 |
  206. +----------------------------------------------+-----------+
  207.  
  208.           Multiword DMA Data Transfer
  209.  
  210.  
  211.  
  212.  
  213. Note:  Under the certain conditions the information reported by the 
  214. drive may be incorrect.  If so, I issue a warning at the end of the report.
  215.  
  216.  
  217.  
  218.