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ATAIDREF.TXT
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1994-07-28
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Documentation for ATAID (AT Attachemnt Identification) Program
Table of contents
1. History 3
2. Connectors 3
2.1. Power connector 3
2.2. Interface Connector 3
2.3. I/O cable 3
3. Signal descriptions 4
3.1. Connections 4
3.2. CS0- (CHIP SELECT 0) 5
3.3. CS1- (CHIP SELECT 1) 5
3.4. DA2, DA1, and DA0 (DEVICE ADDRESS BUS) 5
3.5. DASP- (DRIVE ACTIVE, SLAVE (DRIVE 1) PRESENT) 5
3.6. DD0-DD15 (Drive data bus) 5
3.7. DIOR- (Drive I/O read) 5
3.8. DIOW- (Drive I/O write) 5
3.9. DMACK- (DMA acknowledge) (Optional) 5
3.10.DMARQ (DMA request) (Optional) 5
3.11.INTRQ (Drive interrupt) 6
3.12.IOCS16- (Drive 16-bit I/O) 6
3.13.IORDY (I/O channel ready) (Optional) 6
3.14.PDIAG- (Passed diagnostics) 6
3.15.RESET- (Drive reset) 6
3.16.SPSYNC:CSEL (Spindle synchronization/cable select)Optional) 6
4. Drive Addressing 7
1. History
When the IBM PC-AT was introduced it's key to good performance was the inclusion
of a hard disk.
The PC AT Bus interface is a widely used and implemented interface for which a
variety of peripherals have been manufactured. in order to reduce size and
cost, a the controller was eventually embedded in the drive.
Because of their compatibility with existing AT hardware and software this
interface quickly became a de facto industry standard. While the AT Attachment
Interface has its roots in the PC AT Bus, its use has extended to many other
systems.
The interface in use became widespread and as with all good electronics devices,
need room to change. Laptop makers wanted to change the physical connector
design, system builders wanted to reduce cost through integration. Everyone
wanted better perfromance, and additional devices such as CD-ROM and tape drives
became more popular, so a number of revisoins were made, are are being proposed
for future enhancements.
The standard defines an integrated bus which interfaces between disk drives
and/or other types of devices and host processors. It provides a common point
of attachment for systems manufacturers, system integrators, and suppliers of
intelligent peripherals.
2. Connectors
2.1. Power connector
Power line designation Pin number
+12V 1-01
+12V Return 1-02
+5V Return 1-03
+5V 1-04
Recommended part numbers for the mating connector to 18 AWG cable are shown
below, but equivalent parts may be used.
Connector (4 pin) AMP 1-480424-0 or equivalent.
Contacts (loose piece) AMP 60619-4 or equivalent.
Contacts (strip) AMP 61117-4 or equivalent.
2.2. Interface Connector
+-----------------------+
| 1|
|40 20 2|
======= Circuit board ======= ==-==== Circuit board ====-==
| 1|
|40 20 2|
+-----------------------+
Figure 2 - 40-Pin Connector Mounting
Recommended part numbers for the mating connector are shown below, but
equivalent parts may be used.
Connector (40 pin) 3M 3417-7000 or equivalent.
Strain relief 3M 3448-2040 or equivalent.
2.3. I/O cable
The cable specifications affect system integrity and the maximum length that can
be supported in any application.
Flat cable (stranded 28 AWG) 3M 3365-40 or equivalent.
Flat cable (stranded 28 AWG) 3M 3517-40 (shielded) or equivalent.
Cable length of 0,46m (18 inches). This distance may be exceeded in
circumstances where the characteristics of both ends of the cable can be
controlled.
Cable capacitance shall not exceed 35 pF.
3. Signal descriptions
3.1. Connections
the electrical interface is uses TTL compatable tramitters/recievers and a 40
conductor ribbon cable. the pin numbers are shown below:
+========================+=============+====+===========+
| Description | Source |Pin | Acronym |
+------------------------+-------------+----+-----------+
| Reset | Host | 1 | RESET- |
| | n/a | 2 | Ground |
| Data bus bit 7 | Host/Device | 3 | DD7 |
| Data bus bit 8 | Host/Device | 4 | DD8 |
| Data bus bit 6 | Host/Device | 5 | DD6 |
| Data bus bit 9 | Host/Device | 6 | DD9 |
| Data bus bit 5 | Host/Device | 7 | DD5 |
| Data bus bit 10 | Host/Device | 8 | DD10 |
| Data bus bit 4 | Host/Device | 9 | DD4 |
| Data bus bit 11 | Host/Device | 10 | DD11 |
| Data bus bit 3 | Host/Device | 11 | DD3 |
| Data bus bit 12 | Host/Device | 12 | DD12 |
| Data bus bit 2 | Host/Device | 13 | DD2 |
| Data bus bit 13 | Host/Device | 14 | DD13 |
| Data bus bit 1 | Host/Device | 15 | DD1 |
| Data bus bit 14 | Host/Device | 16 | DD14 |
| Data bus bit 0 | Host/Device | 17 | DD0 |
| Data bus bit 15 | Host/Device | 18 | DD15 |
| Ground | n/a | 19 | Ground |
| (keypin) | n/a | 20 | Reserved |
| DMA Request | Device | 21 | DMARQ |
| Ground | n/a | 22 | Ground |
| I/O Write | Host | 23 | DIOW- |
| Ground | n/a | 24 | Ground |
| I/O Read | Host | 25 | DIOR- |
| Ground | n/a | 26 | Ground |
| I/O Ready | Device | 27 | IORDY |
| Spindle Sync or | (note 1) | 28 | SPSYNC: |
| Cable Select | | | CSEL |
| DMA Acknowledge | Host | 29 | DMACK- |
| Ground | n/a | 30 | Ground |
| Interrupt Request | Device | 31 | INTRQ |
| 16 Bit I/O | Device | 32 | IOCS16- |
| Device Address Bit 1 | Host | 33 | DA1 |
| PASSED DIAGNOSTICS | (note 1) | 34 | PDIAG- |
| Device Address Bit 0 | Host | 35 | DAO |
| Device Address Bit 2 | Host | 36 | DA2 |
| Chip Select 0 | Host | 37 | CS0- |
| Chip Select 1 | Host | 38 | CS1- |
| Drive Active or | (note 1) | 39 | DASP- |
| Slave(Drive 1) Present| | | |
| Ground | n/a | 40 | Ground |
+------------------------+-------------+----+-----------+
3.2. CS0- (CHIP SELECT 0)
This is the chip select signal from the host used to select the Command Block
Registers.
3.3. CS1- (CHIP SELECT 1)
This is the chip select signal from the host used to select the Control Block
Registers.
Note: This signal has also been known in the industry as CS3FX-.
3.4. DA2, DA1, and DA0 (DEVICE ADDRESS BUS)
This is the 3-bit binary coded address asserted by the host to access a register
or data port in the drive.
3.5. DASP- (DRIVE ACTIVE, SLAVE (DRIVE 1) PRESENT)
This signal is not TTL compatible.It is an open collector output and each drive
pulls it up with a 10 K ohm resistor.
This is a time-multiplexed signal which indicates that a drive is active, or
that Drive 1 is present. During power on initialization or after RESET- is
negated, DASP- shall be deasserted by both Drive 0 and Drive 1 within 1 msec,
and then Drive 1 shall assert DASP- within 400 msec to indicate that Drive 1 is
present.
Drive 0 shall allow up to 450 msec for Drive 1 to assert DASP-. If Drive 1 is
not present, Drive 0 may assert DASP- to drive an activity LED.
DASP- shall be negated following acceptance of the first valid command by Drive
1 or after 31 seconds, whichever comes first.
Any time after negation of DASP-, either drive may assert DASP- to indicate that
a drive is active.
NOTE 1 Prior to the development of this standard, products were introduced
which did not time multiplex DASP-. Some used two jumpers to indicate to
Drive 0 whether Drive 1 was present. If such a drive is jumpered to indicate
Drive 1 is present it should work successfully with a Drive 1 which complies
with this standard. If installed as Drive 1, such a drive may or may not work
successfully because it may not assert DASP- for a long enough period to be
recognized. However, it would assert DASP-to indicate that the drive is active.
3.6. DD0-DD15 (Drive data bus)
This is an 8- or 16-bit bi-directional data bus between the host and the drive.
The lower 8 bits are used for 8-bit transfers (e.g. registers, ECC bytes) and,
if the drive supports the Features register capability to enable 8-bit-only data
transfers.
3.7. DIOR- (Drive I/O read)
This is the Read strobe signal. The falling edge of DIOR- enables data from a
register or the data port of the drive onto the host data bus, DD0-DD7 or DD0-
DD15. The rising edge of DIOR- latches data at the host.
3.8. DIOW- (Drive I/O write)
This is the Write strobe signal. The rising edge of DIOW- clocks data from the
host data bus, DD0-DD7 or DD0-DD15, into a register or the data port of the
drive.
3.9. DMACK- (DMA acknowledge) (Optional)
This signal shall be used by the host in response to DMARQ to either acknowledge
that data has been accepted, or that data is available.
3.10.DMARQ (DMA request) (Optional)
This signal, used for DMA data transfers between host and drive, shall be
asserted by the drive when it is ready to transfer data to or from the host.
The direction of data transfer is controlled by DIOR- and DIOW-. This signal is
used in a handshake manner with DMACK- i.e. the drive shall wait until the host
asserts DMACK- before negating DMARQ, and re-asserting DMARQ if there is more
data to transfer.
When a DMA operation is enabled, IOCS16-, CS0- and CS1- shall not be asserted
and transfers shall be 16-bits wide.
3.11.INTRQ (Drive interrupt)
This signal is used to interrupt the host system. INTRQ is asserted only when
the drive has a pending interrupt, the drive is selected, and the host has
cleared nIEN in the Device Control register. If nIEN=1, or the drive is not
selected, this output is in a high impedance state, regardless of the presence
or absence of a pending interrupt.
INTRQ shall be negated by:
- assertion of RESET- or
- the setting of SRST of the Device Control register, or
- the host writing the Command register or
- the host reading the Status register
3.12.IOCS16- (Drive 16-bit I/O)
Except for DMA transfers, IOCS16- indicates to the host system that the 16-bit
data port has been addressed and that the drive is prepared to send or receive a
16-bit data word. This shall be an open collector output.
* When transferring in PIO mode, if IOCS16- is not asserted, transfers shall
be 8-bit using DD0-7.
* When transferring in PIO mode, if IOCS16- is asserted, transfers shall be
16-bit using DD0-15.
* When transferring in DMA mode, the host shall use a 16-bit DMA channel
and IOCS16- shall not be asserted.
3.13.IORDY (I/O channel ready) (Optional)
This signal is negated to extend the host transfer cycle of any host register
access (Read or Write) when the drive is not ready to respond to a data transfer
request. When IORDY is not negated, IORDY shall be in a high impedance state.
3.14.PDIAG- (Passed diagnostics)
This signal shall be asserted by Drive 1 to indicate to Drive 0 that it has
completed diagnostics. A 10K ohm pull-up resistor shall be used on this signal
by each drive.
3.15.RESET- (Drive reset)
This signal from the host system shall be asserted for at least 25 usec after
voltage levels have stabilized during power on and negated thereafter unless
some event requires that the drive(s) be reset following power on.
3.16.SPSYNC:CSEL (Spindle synchronization/cable select) (Optional)
This signal shall have a 10K ohm pull-up resistor.
This is a dual purpose signal and either or both functions may be implemented.
If both functions are implemented then they cannot be active concurrently: the
choice as to which is active is made by a vendor-defined switch.
All drives connected to the same cable should have the same function active at
the same time. If SPSYNC and CSEL are mixed on the same cable, then drive
behavior is undefined.
Prior to the introduction of this standard, this signal was defined as DALE
(Drive Address Latch Enable), and used for an address valid indication from the
host system. If used, the host address and chip selects, DAO through DA2, CS0-,
and CS1- were valid at the negation of this signal and remained valid while DALE
was negated, therefore, the drive did not need to latch these signals with DALE.
3.16.1.SPSYNC (Spindle synchronization) (Optional)
This signal may be either input or output to the drive depending on a vendor-
defined switch. If a drive is set to Drive 0 the signal is output, and if a
drive is set to slave the signal is input.
There is no requirement that each drive implementation be plug-compatible to the
extent that a multiple vendor drive subsystem be operable. Mix and match of
different manufacturers drives is unlikely because rpm, sync fields, sync bytes
etc. need to be virtually identical. However, if drives are designed to match
the following recommendation, controllers can operate drives with a single
implementation.
There can only be one Drive 0 drive at a time in a configuration. The host or
the drive designated as Drive 0 can generate SPSYNC at least once per rotation,
but may be at a higher frequency.
SPSYNC received by a drive is used as the synchronization signal to lock the
spindles in step. The time to achieve synchronization varies, and is indicated
by the drive setting DRDY i.e. if the drive is capable of spindle
synchronization and if it is set to acquire synchronization from another SPSYNC
source, but does not achieve synchronization following power on or a reset, it
shall not set DRDY.
Driver 0 or the host generates SPSYNC and transmits it.
Drive 1 does not generate SPSYNC and is responsible to synchronize its index to
SPSYNC.
If a drive does not support synchronization, it shall ignore SPSYNC.
In the event that a drive previously synchronized loses synchronization, but is
otherwise operational, it does not clear DRDY.
3.16.2.CSEL (Cable select) (Optional)
The drive is configured as either Drive 0 or Drive 1 depending upon the value of
CSEL:
* If CSEL is grounded then the drive address is 0
* If CSEL is open then the drive address is 1
Special cabling can be used by the system manufacturer to selectively ground
CSEL e.g. CSEL of Drive 0 is connected to the CSEL conductor in the cable, and
is grounded, thus allowing the drive to recognize itself as Drive 0. CSEL of
Drive 1 is not connected to CSEL because the conductor is removed, thus the
drive can recognize itself as Drive 1.
4. Drive Addressing
A drive can operate in either of two addressing modes, CHS or LBA, on a command
by command basis. A drive which can support LBA mode indicates this in the
Identify Drive Information.
If the host selects LBA mode in the Drive/Head register, Sector Number register,
Cylinder Low register, Cylinder High register and HS3-HS0 of the Drive/Head
register contains the zero based-LBA.
In LBA mode, the sectors on the drive are assumed to be linearly mapped with an
Initial definition of: LBA 0 = (cylinder 0, head 0, sector 1). Irrespective of
translate mode geometry set by the host, the LBA address of a given sector does
not change:
LBA = ((cylinder * heads_per_cylinder + heads) * sectors_per_track) + sector - 1