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Chapter 2 Basic Programming Model ──────────────────────────────────────────────────────────────────────────── This chapter describes the 80386 application programming environment as seen by assembly language programmers when the processor is executing in protected mode. The chapter introduces programmers to those features of the 80386 architecture that directly affect the design and implementation of 80386 applications programs. Other chapters discuss 80386 features that relate to systems programming or to compatibility with other processors of the 8086 family. The basic programming model consists of these aspects: ■ Memory organization and segmentation ■ Data types ■ Registers ■ Instruction format ■ Operand selection ■ Interrupts and exceptions Note that input/output is not included as part of the basic programming model. Systems designers may choose to make I/O instructions available to applications or may choose to reserve these functions for the operating system. For this reason, the I/O features of the 80386 are discussed in Part II. This chapter contains a section for each aspect of the architecture that is normally visible to applications. 2.1 Memory Organization and Segmentation The physical memory of an 80386 system is organized as a sequence of 8-bit bytes. Each byte is assigned a unique address that ranges from zero to a maximum of 2^(32) -1 (4 gigabytes). 80386 programs, however, are independent of the physical address space. This means that programs can be written without knowledge of how much physical memory is available and without knowledge of exactly where in physical memory the instructions and data are located. The model of memory organization seen by applications programmers is determined by systems-software designers. The architecture of the 80386 gives designers the freedom to choose a model for each task. The model of memory organization can range between the following extremes: ■ A "flat" address space consisting of a single array of up to 4 gigabytes. ■ A segmented address space consisting of a collection of up to 16,383 linear address spaces of up to 4 gigabytes each. Both models can provide memory protection. Different tasks may employ different models of memory organization. The criteria that designers use to determine a memory organization model and the means that systems programmers use to implement that model are covered in Part II──Systems Programming. 2.1.1 The "Flat" Model In a "flat" model of memory organization, the applications programmer sees a single array of up to 2^(32) bytes (4 gigabytes). While the physical memory can contain up to 4 gigabytes, it is usually much smaller; the processor maps the 4 gigabyte flat space onto the physical address space by the address translation mechanisms described in Chapter 5. Applications programmers do not need to know the details of the mapping. A pointer into this flat address space is a 32-bit ordinal number that may range from 0 to 2^(32) -1. Relocation of separately-compiled modules in this space must be performed by systems software (e.g., linkers, locators, binders, loaders). 2.1.2 The Segmented Model In a segmented model of memory organization, the address space as viewed by an applications program (called the logical address space) is a much larger space of up to 2^(46) bytes (64 terabytes). The processor maps the 64 terabyte logical address space onto the physical address space (up to 4 gigabytes) by the address translation mechanisms described in Chapter 5. Applications programmers do not need to know the details of this mapping. Applications programmers view the logical address space of the 80386 as a collection of up to 16,383 one-dimensional subspaces, each with a specified length. Each of these linear subspaces is called a segment. A segment is a unit of contiguous address space. Segment sizes may range from one byte up to a maximum of 2^(32) bytes (4 gigabytes). A complete pointer in this address space consists of two parts (see Figure 2-1): 1. A segment selector, which is a 16-bit field that identifies a segment. 2. An offset, which is a 32-bit ordinal that addresses to the byte level within a segment. During execution of a program, the processor associates with a segment selector the physical address of the beginning of the segment. Separately compiled modules can be relocated at run time by changing the base address of their segments. The size of a segment is variable; therefore, a segment can be exactly the size of the module it contains. 2.2 Data Types Bytes, words, and doublewords are the fundamental data types (refer to Figure 2-2). A byte is eight contiguous bits starting at any logical address. The bits are numbered 0 through 7; bit zero is the least significant bit. A word is two contiguous bytes starting at any byte address. A word thus contains 16 bits. The bits of a word are numbered from 0 through 15; bit 0 is the least significant bit. The byte containing bit 0 of the word is called the low byte; the byte containing bit 15 is called the high byte. Each byte within a word has its own address, and the smaller of the addresses is the address of the word. The byte at this lower address contains the eight least significant bits of the word, while the byte at the higher address contains the eight most significant bits. A doubleword is two contiguous words starting at any byte address. A doubleword thus contains 32 bits. The bits of a doubleword are numbered from 0 through 31; bit 0 is the least significant bit. The word containing bit 0 of the doubleword is called the low word; the word containing bit 31 is called the high word. Each byte within a doubleword has its own address, and the smallest of the addresses is the address of the doubleword. The byte at this lowest address contains the eight least significant bits of the doubleword, while the byte at the highest address contains the eight most significant bits. Figure 2-3 illustrates the arrangement of bytes within words anddoublewords. Note that words need not be aligned at even-numbered addresses and doublewords need not be aligned at addresses evenly divisible by four. This allows maximum flexibility in data structures (e.g., records containing mixed byte, word, and doubleword items) and efficiency in memory utilization. When used in a configuration with a 32-bit bus, actual transfers of data between processor and memory take place in units of doublewords beginning at addresses evenly divisible by four; however, the processor converts requests for misaligned words or doublewords into the appropriate sequences of requests acceptable to the memory interface. Such misaligned data transfers reduce performance by requiring extra memory cycles. For maximum performance, data structures (including stacks) should be designed in such a way that, whenever possible, word operands are aligned at even addresses and doubleword operands are aligned at addresses evenly divisible by four. Due to instruction prefetching and queuing within the CPU, there is no requirement for instructions to be aligned on word or doubleword boundaries. (However, a slight increase in speed results if the target addresses of control transfers are evenly divisible by four.) Although bytes, words, and doublewords are the fundamental types of operands, the processor also supports additional interpretations of these operands. Depending on the instruction referring to the operand, the following additional data types are recognized: Integer: A signed binary numeric value contained in a 32-bit doubleword,16-bit word, or 8-bit byte. All operations assume a 2's complement representation. The sign bit is located in bit 7 in a byte, bit 15 in a word, and bit 31 in a doubleword. The sign bit has the value zero for positive integers and one for negative. Since the high-order bit is used for a sign, the range of an 8-bit integer is -128 through +127; 16-bit integers may range from -32,768 through +32,767; 32-bit integers may range from -2^(31) through +2^(31) -1. The value zero has a positive sign. Ordinal: An unsigned binary numeric value contained in a 32-bit doubleword, 16-bit word, or 8-bit byte. All bits are considered in determining magnitude of the number. The value range of an 8-bit ordinal number is 0-255; 16 bits can represent values from 0 through 65,535; 32 bits can represent values from 0 through 2^(32) -1. Near Pointer: A 32-bit logical address. A near pointer is an offset within a segment. Near pointers are used in either a flat or a segmented model of memory organization. Far Pointer: A 48-bit logical address of two components: a 16-bit segment selector component and a 32-bit offset component. Far pointers are used by applications programmers only when systems designers choose a segmented memory organization. String: A contiguous sequence of bytes, words, or doublewords. A string may contain from zero bytes to 2^(32) -1 bytes (4 gigabytes). Bit field: A contiguous sequence of bits. A bit field may begin at any bit position of any byte and may contain up to 32 bits. Bit string: A contiguous sequence of bits. A bit string may begin at any bit position of any byte and may contain up to 2^(32) -1 bits. BCD: A byte (unpacked) representation of a decimal digit in the range0 through 9. Unpacked decimal numbers are stored as unsigned byte quantities. One digit is stored in each byte. The magnitude of the number is determined from the low-order half-byte; hexadecimal values 0-9 are valid and are interpreted as decimal numbers. The high-order half-byte must be zero for multiplication and division; it may contain any value for addition and subtraction. Packed BCD: A byte (packed) representation of two decimal digits, each in the range 0 through 9. One digit is stored in each half-byte. The digit in the high-order half-byte is the most significant. Values 0-9 are valid in each half-byte. The range of a packed decimal byte is 0-99. Figure 2-4 graphically summarizes the data types supported by the 80386. Figure 2-1. Two-Component Pointer ║ ║ ╠═══════════════╣─┐ 32 0 ║ ║ │ ╔═══════╪═══════╗ ╔═══╗ ╠═══════════════╣ │ ║ OFFSET ╟───╢ + ╟───║ OPERAND ║ │ ╚═══════╪═══════╝ ╚═══╝ ╠═══════════════╣ ├─ SELECTED SEGMENT ║ ║ │ 16 0 │ ║ ║ │ ╔═══════╗ │ ║ ║ │ ║SEGMENT╟─────────∙─────╠═══════════════╣─┘ ╚═══════╝ ║ ║ ║ ║ ║ ║ Figure 2-2. Fundamental Data Types 7 0 ╔═══════════════╗ ║ BYTE ║ BYTE ╚═══════════════╝ 15 7 0 ╔═══════════════╤═══════════════╗ ║ HIGH BYTE │ LOW BYTE ║ WORD ╚═══════════════╧═══════════════╝ address n+1 address n 31 23 15 7 0 ╔═══════════════╪═══════════════╪═══════════════╪══════════════╗ ║ HIGH WORD │ LOW WORD ║ DOUBLEWORD ╚═══════════════╪═══════════════╪═══════════════╪══════════════╝ address n+3 address n+2 address n+1 address n Figure 2-3. Bytes, Words, and Doublewords in Memory MEMORY BYTE VALUES All values in hexadecimal ADDRESS ╔══════════╗ E║ ║ ╠══════════╣──┐ D║ 7A ║ ├─ DOUBLE WORD AT ADDRESS A ╠══════════╣─┐│ CONTAINS 7AFE0636 C║ FE ║ ││ ╠══════════╣ ├─ WORD AT ADDRESS B B║ 06 ║ ││ CONTAINS FE06 ╠══════════╣─┘│ A║ 36 ║ │ ╠══════════╣══╡ 9║ 1F ║ ├─ WORD AT ADDRESS 9 ╠══════════╣──┘ CONTAINS IF 8║ ║ ╠══════════╣──┐ 7║ 23 ║ │ ╠══════════╣ ├─ WORD AT ADDRESS 6 6║ OB ║ │ CONTAINS 23OB ╠══════════╣──┘ 5║ ║ ╠══════════╣ 4║ ║ ╠══════════╣──┐ 3║ 74 ║ │ ╠══════════╣─┐├─ WORD AT ADDRESS 2 2║ CB ║ ││ CONTAINS 74CB ╠══════════╣──┘ 1║ 31 ║ ├── WORD AT ADDRESS 1 ╠══════════╣─┘ CONTAINS CB31 0║ ║ ╚══════════╝ Figure 2-4. 80386 Data Types +1 0 7 0 7 0 15 14 8 7 0 BYTE ╔╤╤╤╤╤╤╤╗ BYTE ╔╤╤╤╤╤╤╤╗ WORD ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ INTEGER ║│ │ ║ ORDINAL ║ │ ║ INTEGER ║│ │ │ │ ║ ╚╧══════╝ ╚═══════╝ ╚╧══════╧═══════╝ SIGN BIT┘└──────┘ └───────┘ SIGN BIT┘└MSB │ MAGNITUDE MAGNITUDE └───────────────┘ MAGNITUDE +1 0 +3 +2 +1 0 15 0 31 16 15 0 WORD ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ DOUBLEWORD ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ ORDINAL ║│ │ │ │ ║ INTEGER ║│ │ │ │ │ │ │ │ ║ ╚╧══════╧═══════╝ ╚╧══════╧═══════╧═══════╧═══════╝ │ │ SIGN BIT┘└MSB │ └───────────────┘ └───────────────────────────────┘ MAGNITUDE MAGNITUDE +3 +2 +1 0 31 0 DOUBLEWORD ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ ORDINAL ║ │ │ │ │ │ │ │ ║ ╚═══════╧═══════╧═══════╧═══════╝ └───────────────────────────────┘ MAGNITUDE +N +1 0 7 0 7 0 7 0 BINARY CODED ╔╤╤╤╤╤╤╤╗ ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ DECIMAL (BCD) ║ │ ║ ║ │ │ │ ║ ╚═══════╝ ╚═══════╧═══════╝ BCD BCD BCD DIGIT N DIGIT 1 DIGIT 0 +N +1 0 7 0 7 0 7 0 PACKED ╔╤╤╤╤╤╤╤╗ ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ BCD ║ │ ║ ║ │ │ │ ║ ╚═══════╝ ╚═══════╧═══════╝ └───┘ └───┘ MOST LEAST SIGNIFICANT SIGNIFICANT DIGIT DIGIT +N +1 0 7 0 7 0 7 0 BYTE ╔╤╤╤╤╤╤╤╗ ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ STRING ║ │ ║ ║ │ │ │ ║ ╚═══════╝ ╚═══════╧═══════╝ -2 GIGABYTES +2 GIGABYTES 210 BIT ╔╤╤╤╤════════════╤╤═══════ ════════════════╤╤╤╤╗ STRING ║││││ ││ ││││║ ╚╧╧╧╧════════════╧╧════════ ═══════════════╧╧╧╧╝ BIT 0 +3 +2 +1 0 31 0 NEAR 32-BIT ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ POINTER ║ │ │ │ │ │ │ │ ║ ╚═══════╧═══════╧═══════╧═══════╝ └───────────────────────────────┘ OFFSET +5 +4 +3 +2 +1 0 48 0 FAR 48-BIT ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ POINTER ║ │ │ │ │ │ │ │ │ │ │ │ ║ ╚═══════╧═══════╧═══════╧═══════╧═══════╧═══════╝ └───────────────┴───────────────────────────────┘ SELECTOR OFFSET +5 +4 +3 +2 +1 0 32-BIT ╔╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╤╗ BIT FIELD ║ │ │ │ │ │ │ │ │ │ │ │ ║ ╚═══════╧═══════╧═══════╧═══════╧═══════╧═══════╝ │───────── BIT FIELD ─────────│ 1 TO 32 BITS 2.3 Registers The 80386 contains a total of sixteen registers that are of interest to the applications programmer. As Figure 2-5 shows, these registers may be grouped into these basic categories: 1. General registers. These eight 32-bit general-purpose registers are used primarily to contain operands for arithmetic and logical operations. 2. Segment registers. These special-purpose registers permit systems software designers to choose either a flat or segmented model of memory organization. These six registers determine, at any given time, which segments of memory are currently addressable. 3. Status and instruction registers. These special-purpose registers are used to record and alter certain aspects of the 80386 processor state. 2.3.1 General Registers The general registers of the 80386 are the 32-bit registers EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. These registers are used interchangeably to contain the operands of logical and arithmetic operations. They may also be used interchangeably for operands of address computations (except that ESP cannot be used as an index operand). As Figure 2-5 shows, the low-order word of each of these eight registers has a separate name and can be treated as a unit. This feature is useful for handling 16-bit data items and for compatibility with the 8086 and 80286 processors. The word registers are named AX, BX, CX, DX, BP, SP, SI, and DI. Figure 2-5 also illustrates that each byte of the 16-bit registers AX, BX, CX, and DX has a separate name and can be treated as a unit. This feature is useful for handling characters and other 8-bit data items. The byte registers are named AH, BH, CH, and DH (high bytes); and AL, BL, CL, and DL (low bytes). All of the general-purpose registers are available for addressing calculations and for the results of most arithmetic and logical calculations; however, a few functions are dedicated to certain registers. By implicitly choosing registers for these functions, the 80386 architecture can encode instructions more compactly. The instructions that use specific registers include: double-precision multiply and divide, I/O, string instructions, translate, loop, variable shift and rotate, and stack operations. 2.3.2 Segment Registers The segment registers of the 80386 give systems software designers the flexibility to choose among various models of memory organization. Implementation of memory models is the subject of Part II ── Systems Programming. Designers may choose a model in which applications programs do not need to modify segment registers, in which case applications programmers may skip this section. Complete programs generally consist of many different modules, each consisting of instructions and data. However, at any given time during program execution, only a small subset of a program's modules are actually in use. The 80386 architecture takes advantage of this by providing mechanisms to support direct access to the instructions and data of the current module's environment, with access to additional segments on demand. At any given instant, six segments of memory may be immediately accessible to an executing 80386 program. The segment registers CS, DS, SS, ES, FS, and GS are used to identify these six current segments. Each of these registers specifies a particular kind of segment, as characterized by the associated mnemonics ("code," "data," or "stack") shown in Figure 2-6. Each register uniquely determines one particular segment, from among the segments that make up the program, that is to be immediately accessible at highest speed. The segment containing the currently executing sequence of instructions is known as the current code segment; it is specified by means of the CS register. The 80386 fetches all instructions from this code segment, using as an offset the contents of the instruction pointer. CS is changed implicitly as the result of intersegment control-transfer instructions (for example, CALL and JMP), interrupts, and exceptions. Subroutine calls, parameters, and procedure activation records usually require that a region of memory be allocated for a stack. All stack operations use the SS register to locate the stack. Unlike CS, the SS register can be loaded explicitly, thereby permitting programmers to define stacks dynamically. The DS, ES, FS, and GS registers allow the specification of four data segments, each addressable by the currently executing program. Accessibility to four separate data areas helps programs efficiently access different types of data structures; for example, one data segment register can point to the data structures of the current module, another to the exported data of a higher-level module, another to a dynamically created data structure, and another to data shared with another task. An operand within a data segment is addressed by specifying its offset either directly in an instruction or indirectly via general registers. Depending on the structure of data (e.g., the way data is parceled into one or more segments), a program may require access to more than four data segments. To access additional segments, the DS, ES, FS, and GS registers can be changed under program control during the course of a program's execution. This simply requires that the program execute an instruction to load the appropriate segment register prior to executing instructions that access the data. The processor associates a base address with each segment selected by a segment register. To address an element within a segment, a 32-bit offset is added to the segment's base address. Once a segment is selected (by loading the segment selector into a segment register), a data manipulation instruction only needs to specify the offset. Simple rules define which segment register is used to form an address when only an offset is specified. Figure 2-5. 80386 Applications Register Set GENERAL REGISTERS 31 23 15 7 0 ╔═════════════════╪═════════════════╬═════════════════╧═════════════════╗ ║ EAX AH AX AL ║ ╠═════════════════╪═════════════════╬═════════════════╩═════════════════╣ ║ EDX DH DX DL ║ ╠═════════════════╪═════════════════╬═════════════════╩═════════════════╣ ║ ECX CH CX CL ║ ╠═════════════════╪═════════════════╬═════════════════╩═════════════════╣ ║ EBX BH BX BL ║ ╠═════════════════╪═════════════════╬═════════════════╩═════════════════╣ ║ EBP BP ║ ╠═════════════════╪═════════════════╬═════════════════╪═════════════════╣ ║ ESI SI ║ ╠═════════════════╪═════════════════╬═════════════════╪═════════════════╣ ║ EDI DI ║ ╠═════════════════╪═════════════════╬═════════════════╪═════════════════╣ ║ ESP SP ║ ╚═════════════════╪═════════════════╬═════════════════╪═════════════════╝ 15 7 0 ╔═════════════════╪═════════════════╗ ║ CS (CODE SEGMENT) ║ ╟─────────────────┼─────────────────╢ ║ SS (STACK SEGMENT) ║ SEGMENT ╟─────────────────┼─────────────────╢ REGISTERS ║ DS (DATA SEGMENT) ║ ╟─────────────────┼─────────────────╢ ║ ES (DATA SEGMENT) ║ ╟─────────────────┼─────────────────╢ ║ FS (DATA SEGMENT) ║ ╟─────────────────┼─────────────────╢ ║ GS (DATA SEGMENT) ║ ╚═════════════════╪═════════════════╝ STATUS AND INSTRUCTION REGISTERS 31 23 15 7 0 ╔═════════════════╪═════════════════╪═════════════════╪═════════════════╗ ║ EFLAGS ║ ╟───────────────────────────────────────────────────────────────────────╢ ║ EIP (INSTRUCTION POINTER) ║ ╚═════════════════╪═════════════════╪═════════════════╪═════════════════╝ Figure 2-6. Use of Memory Segmentation ╔════════════════╗ ╔════════════════╗ ║ MODULE ║ ║ MODULE ║ ║ A ║──┐ ┌──║ A ║ ║ CODE ║ │ │ ║ DATA ║ ╚════════════════╝ │ ╔══════════════════╗ │ ╚════════════════╝ └──╢ CS (CODE) ║ │ ╠══════════════════╣ │ ╔════════════════╗ ┌──╢ SS (STACK) ║ │ ╔════════════════╗ ║ ║ │ ╠══════════════════╣ │ ║ DATA ║ ║ STACK ║──┘ ║ DS (DATA) ╟──┘┌─║ STRUCTURE ║ ║ ║ ╠══════════════════╣ │ ║ 1 ║ ╚════════════════╝ ║ ES (DATA) ╟───┘ ╚════════════════╝ ╠══════════════════╣ ┌──╢ FS (DATA) ║ ╔════════════════╗ │ ╠══════════════════╣ ╔════════════════╗ ║ DATA ║ │ ║ GS (DATA) ╟──┐ ║ DATA ║ ║ STRUCTURE ║──┘ ╚══════════════════╝ └──║ STRUCTURE ║ ║ 2 ║ ║ 3 ║ ╚════════════════╝ ╚════════════════╝ 2.3.3 Stack Implementation Stack operations are facilitated by three registers: 1. The stack segment (SS) register. Stacks are implemented in memory. A system may have a number of stacks that is limited only by the maximum number of segments. A stack may be up to 4 gigabytes long, the maximum length of a segment. One stack is directly addressable at a time──the one located by SS. This is the current stack, often referred to simply as "the" stack. SS is used automatically by the processor for all stack operations. 2. The stack pointer (ESP) register. ESP points to the top of the push-down stack (TOS). It is referenced implicitly by PUSH and POP operations, subroutine calls and returns, and interrupt operations. When an item is pushed onto the stack (see Figure 2-7), the processor decrements ESP, then writes the item at the new TOS. When an item is popped off the stack, the processor copies it from TOS, then increments ESP. In other words, the stack grows down in memory toward lesser addresses. 3. The stack-frame base pointer (EBP) register. The EBP is the best choice of register for accessing data structures, variables and dynamically allocated work space within the stack. EBP is often used to access elements on the stack relative to a fixed point on the stack rather than relative to the current TOS. It typically identifies the base address of the current stack frame established for the current procedure. When EBP is used as the base register in an offset calculation, the offset is calculated automatically in the current stack segment (i.e., the segment currently selected by SS). Because SS does not have to be explicitly specified, instruction encoding in such cases is more efficient. EBP can also be used to index into segments addressable via other segment registers. Figure 2-7. 80386 Stack 31 0 ╔══════╪══════╪══════╪══════╗ ───────BOTTOM OF STACK ║ ║ (INITIAL ESP VALUE) ╟══════╪══════╪══════╪══════╣ ║ ║ ╠══════╪══════╪══════╪══════╣ ║ ║ │POP ╠══════╪══════╪══════╪══════╣ │ ║ ║ │ ╠══════╪══════╪══════╪══════╣ │ TOP OF ╔═════════════╗ ║ ║ ──────┼─────────────────╢ ESP ║ ╠══════╪══════╪══════╪══════╣ │ STACK ╚═════════════╝ ║ ║ │ ║ ║ │ ║ ║ │PUSH ║ ║ 2.3.4 Flags Register The flags register is a 32-bit register named EFLAGS. Figure 2-8 defines the bits within this register. The flags control certain operations and indicate the status of the 80386. The low-order 16 bits of EFLAGS is named FLAGS and can be treated as a unit. This feature is useful when executing 8086 and 80286 code, because this part of EFLAGS is identical to the FLAGS register of the 8086 and the 80286. The flags may be considered in three groups: the status flags, the control flags, and the systems flags. Discussion of the systems flags is delayed until Part II. Figure 2-8. EFLAGS Register 16-BIT FLAGS REGISTER A ┌───────────────────┴───────────────┐ 31 23 15 7 0 ╔═══════════════════╪═══════════════╤═╤═╤═╤═╤═╪═╤═╤═╤═╤═╤═╤═╤═╤═╤═╤═╤═╤═╗ ║ │V│R│ │N│ IO│O│D│I│T│S│Z│ │A│ │P│ │C║ ║ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 │ │ │0│ │ │ │ │ │ │ │ │0│ │0│ │1│ ║ ║ │M│F│ │T│ PL│F│F│F│F│F│F│ │F│ │F│ │F║ ╚═══════════════════╪═══════════════╧╤╧╤╧═╧╤╧═╪═╧╤╧╤╧╤╧╤╧╤╧╤╧═╧╤╧═╧╤╧═╧╤╝ │ │ │ │ │ │ │ │ │ │ │ │ │ VIRTUAL 8086 MODE───X──────────┘ │ │ │ │ │ │ │ │ │ │ │ │ RESUME FLAG───X────────────┘ │ │ │ │ │ │ │ │ │ │ │ NESTED TASK FLAG───X────────────────┘ │ │ │ │ │ │ │ │ │ │ I/O PRIVILEGE LEVEL───X───────────────────┘ │ │ │ │ │ │ │ │ │ OVERFLOW───S──────────────────────┘ │ │ │ │ │ │ │ │ DIRECTION FLAG───C────────────────────────┘ │ │ │ │ │ │ │ INTERRUPT ENABLE───X──────────────────────────┘ │ │ │ │ │ │ TRAP FLAG───S────────────────────────────┘ │ │ │ │ │ SIGN FLAG───S──────────────────────────────┘ │ │ │ │ ZERO FLAG───S────────────────────────────────┘ │ │ │ AUXILIARY CARRY───S────────────────────────────────────┘ │ │ PARITY FLAG───S────────────────────────────────────────┘ │ CARRY FLAG───S────────────────────────────────────────────┘ S = STATUS FLAG, C = CONTROL FLAG, X = SYSTEM FLAG NOTE: 0 OR 1 INDICATES INTEL RESERVED. DO NOT DEFINE 2.3.4.1 Status Flags The status flags of the EFLAGS register allow the results of one instruction to influence later instructions. The arithmetic instructions use OF, SF, ZF, AF, PF, and CF. The SCAS (Scan String), CMPS (Compare String), and LOOP instructions use ZF to signal that their operations are complete. There are instructions to set, clear, and complement CF before execution of an arithmetic instruction. Refer to Appendix C for definition of each status flag. 2.3.4.2 Control Flag The control flag DF of the EFLAGS register controls string instructions. DF (Direction Flag, bit 10) Setting DF causes string instructions to auto-decrement; that is, to process strings from high addresses to low addresses. Clearing DF causes string instructions to auto-increment, or to process strings from low addresses to high addresses. 2.3.4.3 Instruction Pointer The instruction pointer register (EIP) contains the offset address, relative to the start of the current code segment, of the next sequential instruction to be executed. The instruction pointer is not directly visible to the programmer; it is controlled implicitly by control-transfer instructions, interrupts, and exceptions. As Figure 2-9 shows, the low-order 16 bits of EIP is named IP and can be used by the processor as a unit. This feature is useful when executing instructions designed for the 8086 and 80286 processors. Figure 2-9. Instruction Pointer Register 16-BIT IP REGISTER ┌──────────────────┴────────────────┐ 31 23 15 7 0 ╔═════════════════╪═════════════════╪═════════════════╪═════════════════╗ ║ EIP (INSTRUCTION POINTER) ║ ╚═════════════════╪═════════════════╪═════════════════╪═════════════════╝ 2.4 Instruction Format The information encoded in an 80386 instruction includes a specification of the operation to be performed, the type of the operands to be manipulated, and the location of these operands. If an operand is located in memory, the instruction must also select, explicitly or implicitly, which of the currently addressable segments contains the operand. 80386 instructions are composed of various elements and have various formats. The exact format of instructions is shown in Appendix B; the elements of instructions are described below. Of these instruction elements, only one, the opcode, is always present. The other elements may or may not be present, depending on the particular operation involved and on the location and type of the operands. The elements of an instruction, in order of occurrence are as follows: ■ Prefixes ── one or more bytes preceding an instruction that modify the operation of the instruction. The following types of prefixes can be used by applications programs: 1. Segment override ── explicitly specifies which segment register an instruction should use, thereby overriding the default segment-register selection used by the 80386 for that instruction. 2. Address size ── switches between 32-bit and 16-bit address generation. 3. Operand size ── switches between 32-bit and 16-bit operands. 4. Repeat ── used with a string instruction to cause the instruction to act on each element of the string. ■ Opcode ── specifies the operation performed by the instruction. Some operations have several different opcodes, each specifying a different variant of the operation. ■ Register specifier ── an instruction may specify one or two register operands. Register specifiers may occur either in the same byte as the opcode or in the same byte as the addressing-mode specifier. ■ Addressing-mode specifier ── when present, specifies whether an operand is a register or memory location; if in memory, specifies whether a displacement, a base register, an index register, and scaling are to be used. ■ SIB (scale, index, base) byte ── when the addressing-mode specifier indicates that an index register will be used to compute the address of an operand, an SIB byte is included in the instruction to encode the base register, the index register, and a scaling factor. ■ Displacement ── when the addressing-mode specifier indicates that a displacement will be used to compute the address of an operand, the displacement is encoded in the instruction. A displacement is a signed integer of 32, 16, or eight bits. The eight-bit form is used in the common case when the displacement is sufficiently small. The processor extends an eight-bit displacement to 16 or 32 bits, taking into account the sign. ■ Immediate operand ── when present, directly provides the value of an operand of the instruction. Immediate operands may be 8, 16, or 32 bits wide. In cases where an eight-bit immediate operand is combined in some way with a 16- or 32-bit operand, the processor automatically extends the size of the eight-bit operand, taking into account the sign. 2.5 Operand Selection An instruction can act on zero or more operands, which are the data manipulated by the instruction. An example of a zero-operand instruction is NOP (no operation). An operand can be in any of these locations: ■ In the instruction itself (an immediate operand) ■ In a register (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP in the case of 32-bit operands; AX, BX, CX, DX, SI, DI, SP, or BP in the case of 16-bit operands; AH, AL, BH, BL, CH, CL, DH, or DL in the case of 8-bit operands; the segment registers; or the EFLAGS register for flag operations) ■ In memory ■ At an I/O port Immediate operands and operands in registers can be accessed more rapidly than operands in memory since memory operands must be fetched from memory. Register operands are available in the CPU. Immediate operands are also available in the CPU, because they are prefetched as part of the instruction. Of the instructions that have operands, some specify operands implicitly; others specify operands explicitly; still others use a combination of implicit and explicit specification; for example: Implicit operand: AAM By definition, AAM (ASCII adjust for multiplication) operates on the contents of the AX register. Explicit operand: XCHG EAX, EBX The operands to be exchanged are encoded in the instruction after the opcode. Implicit and explicit operands: PUSH COUNTER The memory variable COUNTER (the explicit operand) is copied to the top of the stack (the implicit operand). Note that most instructions have implicit operands. All arithmetic instructions, for example, update the EFLAGS register. An 80386 instruction can explicitly reference one or two operands. Two-operand instructions, such as MOV, ADD, XOR, etc., generally overwrite one of the two participating operands with the result. A distinction can thus be made between the source operand (the one unaffected by the operation) and the destination operand (the one overwritten by the result). For most instructions, one of the two explicitly specified operands──either the source or the destination──can be either in a register or in memory. The other operand must be in a register or be an immediate source operand. Thus, the explicit two-operand instructions of the 80386 permit operations of the following kinds: ■ Register-to-register ■ Register-to-memory ■ Memory-to-register ■ Immediate-to-register ■ Immediate-to-memory Certain string instructions and stack manipulation instructions, however, transfer data from memory to memory. Both operands of some string instructions are in memory and are implicitly specified. Push and pop stack operations allow transfer between memory operands and the memory-based stack. 2.5.1 Immediate Operands Certain instructions use data from the instruction itself as one (and sometimes two) of the operands. Such an operand is called an immediate operand. The operand may be 32-, 16-, or 8-bits long. For example: SHR PATTERN, 2 One byte of the instruction holds the value 2, the number of bits by which to shift the variable PATTERN. TEST PATTERN, 0FFFF00FFH A doubleword of the instruction holds the mask that is used to test the variable PATTERN. 2.5.2 Register Operands Operands may be located in one of the 32-bit general registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP), in one of the 16-bit general registers (AX, BX, CX, DX, SI, DI, SP, or BP), or in one of the 8-bit general registers (AH, BH, CH, DH, AL, BL, CL,or DL). The 80386 has instructions for referencing the segment registers (CS, DS, ES, SS, FS, GS). These instructions are used by applications programs only if systems designers have chosen a segmented memory model. The 80386 also has instructions for referring to the flag register. The flags may be stored on the stack and restored from the stack. Certain instructions change the commonly modified flags directly in the EFLAGS register. Other flags that are seldom modified can be modified indirectly via the flags image in the stack. 2.5.3 Memory Operands Data-manipulation instructions that address operands in memory must specify (either directly or indirectly) the segment that contains the operand and the offset of the operand within the segment. However, for speed and compact instruction encoding, segment selectors are stored in the high speed segment registers. Therefore, data-manipulation instructions need to specify only the desired segment register and an offset in order to address a memory operand. An 80386 data-manipulation instruction that accesses memory uses one of the following methods for specifying the offset of a memory operand within its segment: 1. Most data-manipulation instructions that access memory contain a byte that explicitly specifies the addressing method for the operand. A byte, known as the modR/M byte, follows the opcode and specifies whether the operand is in a register or in memory. If the operand is in memory, the address is computed from a segment register and any of the following values: a base register, an index register, a scaling factor, a displacement. When an index register is used, the modR/M byte is also followed by another byte that identifies the index register and scaling factor. This addressing method is the mostflexible. 2. A few data-manipulation instructions implicitly use specialized addressing methods: ■ For a few short forms of MOV that implicitly use the EAX register, the offset of the operand is coded as a doubleword in the instruction. No base register, index register, or scaling factor are used. ■ String operations implicitly address memory via DS:ESI, (MOVS, CMPS, OUTS, LODS, SCAS) or via ES:EDI (MOVS, CMPS, INS, STOS). ■ Stack operations implicitly address operands via SS:ESP registers; e.g., PUSH, POP, PUSHA, PUSHAD, POPA, POPAD, PUSHF, PUSHFD, POPF, POPFD, CALL, RET, IRET, IRETD, exceptions, and interrupts. 2.5.3.1 Segment Selection Data-manipulation instructions need not explicitly specify which segment register is used. For all of these instructions, specification of a segment register is optional. For all memory accesses, if a segment is not explicitly specified by the instruction, the processor automatically chooses a segment register according to the rules of Table 2-1. (If systems designers have chosen a flat model of memory organization, the segment registers and the rules that the processor uses in choosing them are not apparent to applications programs.) There is a close connection between the kind of memory reference and the segment in which that operand resides. As a rule, a memory reference implies the current data segment (i.e., the implicit segment selector is in DS). However, ESP and EBP are used to access items on the stack; therefore, when the ESP or EBP register is used as a base register, the current stack segment is implied (i.e., SS contains the selector). Special instruction prefix elements may be used to override the default segment selection. Segment-override prefixes allow an explicit segment selection. The 80386 has a segment-override prefix for each of the segment registers. Only in the following special cases is there an implied segment selection that a segment prefix cannot override: ■ The use of ES for destination strings in string instructions. ■ The use of SS in stack instructions. ■ The use of CS for instruction fetches. Table 2-1. Default Segment Register Selection Rules Memory Reference Needed Segment Implicit Segment Selection Rule Register Used Instructions Code (CS) Automatic with instruction prefetch Stack Stack (SS) All stack pushes and pops. Any memory reference that uses ESP or EBP as a base register. Local Data Data (DS) All data references except when relative to stack or string destination. Destination Strings Extra (ES) Destination of string instructions. 2.5.3.2 Effective-Address Computation The modR/M byte provides the most flexible of the addressing methods, and instructions that require a modR/M byte as the second byte of the instruction are the most common in the 80386 instruction set. For memory operands defined by modR/M, the offset within the desired segment is calculated by taking the sum of up to three components: ■ A displacement element in the instruction. ■ A base register. ■ An index register. The index register may be automatically multiplied by a scaling factor of 2, 4, or 8. The offset that results from adding these components is called an effective address. Each of these components of an effective address may have either a positive or negative value. If the sum of all the components exceeds 2^(32), the effective address is truncated to 32 bits.Figure 2-10 illustrates the full set of possibilities for modR/M addressing. The displacement component, because it is encoded in the instruction, is useful for fixed aspects of addressing; for example: ■ Location of simple scalar operands. ■ Beginning of a statically allocated array. ■ Offset of an item within a record. The base and index components have similar functions. Both utilize the same set of general registers. Both can be used for aspects of addressing that are determined dynamically; for example: ■ Location of procedure parameters and local variables in stack. ■ The beginning of one record among several occurrences of the same record type or in an array of records. ■ The beginning of one dimension of multiple dimension array. ■ The beginning of a dynamically allocated array. The uses of general registers as base or index components differ in the following respects: ■ ESP cannot be used as an index register. ■ When ESP or EBP is used as the base register, the default segment is the one selected by SS. In all other cases the default segment is DS. The scaling factor permits efficient indexing into an array in the common cases when array elements are 2, 4, or 8 bytes wide. The shifting of the index register is done by the processor at the time the address is evaluated with no performance loss. This eliminates the need for a separate shift or multiply instruction. The base, index, and displacement components may be used in any combination; any of these components may be null. A scale factor can be used only when an index is also used. Each possible combination is useful for data structures commonly used by programmers in high-level languages and assembly languages. Following are possible uses for some of the various combinations of address components. DISPLACEMENT The displacement alone indicates the offset of the operand. This combination is used to directly address a statically allocated scalar operand. An 8-bit, 16-bit, or 32-bit displacement can be used. BASE The offset of the operand is specified indirectly in one of the general registers, as for "based" variables. BASE + DISPLACEMENT A register and a displacement can be used together for two distinct purposes: 1. Index into static array when element size is not 2, 4, or 8 bytes. The displacement component encodes the offset of the beginning of the array. The register holds the results of a calculation to determine the offset of a specific element within the array. 2. Access item of a record. The displacement component locates an item within record. The base register selects one of several occurrences of record, thereby providing a compact encoding for this common function. An important special case of this combination, is to access parameters in the procedure activation record in the stack. In this case, EBP is the best choice for the base register, because when EBP is used as a base register, the processor automatically uses the stack segment register (SS) to locate the operand, thereby providing a compact encoding for this common function. (INDEX * SCALE) + DISPLACEMENT This combination provides efficient indexing into a static array when the element size is 2, 4, or 8 bytes. The displacement addresses the beginning of the array, the index register holds the subscript of the desired array element, and the processor automatically converts the subscript into an index by applying the scaling factor. BASE + INDEX + DISPLACEMENT Two registers used together support either a two-dimensional array (the displacement determining the beginning of the array) or one of several instances of an array of records (the displacement indicating an item in the record). BASE + (INDEX * SCALE) + DISPLACEMENT This combination provides efficient indexing of a two-dimensional array when the elements of the array are 2, 4, or 8 bytes wide. Figure 2-10. Effective Address Computation SEGMENT + BASE + (INDEX * SCALE) + DISPLACEMENT ┌ ┐ │ --- │ ┌ ┐ ┌ ┐ ┌ ┐ │ EAX │ │ EAX │ │ 1 │ │ CS │ │ ECX │ │ ECX │ │ │ ┌ ┐ │ SS │ │ EDX │ │ EDX │ │ 2 │ │ NO DISPLACEMENT │ ─┤ DS ├─ + ─┤ EBX ├─ + ─┤ EBX ├─ * ─┤ ├─ + ─┤ 8-BIT DISPLACEMENT ├─ │ ES │ │ ESP │ │ --- │ │ 4 │ │ 32-BIT DISPLACEMENT │ │ FS │ │ EBP │ │ EBP │ │ │ └ ┘ │ GS │ │ ESI │ │ ESI │ │ 6 │ └ ┘ │ EDI │ │ EDI │ └ ┘ └ ┘ └ ┘ 2.6 Interrupts and Exceptions The 80386 has two mechanisms for interrupting program execution: 1. Exceptions are synchronous events that are the responses of the CPU to certain conditions detected during the execution of an instruction. 2. Interrupts are asynchronous events typically triggered by external devices needing attention. Interrupts and exceptions are alike in that both cause the processor to temporarily suspend its present program execution in order to execute a program of higher priority. The major distinction between these two kinds of interrupts is their origin. An exception is always reproducible by re-executing with the program and data that caused the exception, whereas an interrupt is generally independent of the currently executing program. Application programmers are not normally concerned with servicing interrupts. More information on interrupts for systems programmers may be found in Chapter 9. Certain exceptions, however, are of interest to applications programmers, and many operating systems give applications programs the opportunity to service these exceptions. However, the operating system itself defines the interface between the applications programs and the exception mechanism of the 80386. Table 2-2 highlights the exceptions that may be of interest to applications programmers. ■ A divide error exception results when the instruction DIV or IDIV is executed with a zero denominator or when the quotient is too large for the destination operand. (Refer to Chapter 3 for a discussion of DIV and IDIV.) ■ The debug exception may be reflected back to an applications program if it results from the trap flag (TF). ■ A breakpoint exception results when the instruction INT 3 is executed. This instruction is used by some debuggers to stop program execution at specific points. ■ An overflow exception results when the INTO instruction is executed and the OF (overflow) flag is set (after an arithmetic operation that set the OF flag). (Refer to Chapter 3 for a discussion of INTO). ■ A bounds check exception results when the BOUND instruction is executed and the array index it checks falls outside the bounds of the array. (Refer to Chapter 3 for a discussion of the BOUND instruction.) ■ Invalid opcodes may be used by some applications to extend the instruction set. In such a case, the invalid opcode exception presents an opportunity to emulate the opcode. ■ The "coprocessor not available" exception occurs if the program contains instructions for a coprocessor, but no coprocessor is present in the system. ■ A coprocessor error is generated when a coprocessor detects an illegal operation. The instruction INT generates an interrupt whenever it is executed; the processor treats this interrupt as an exception. The effects of this interrupt (and the effects of all other exceptions) are determined by exception handler routines provided by the application program or as part of the systems software (provided by systems programmers). The INT instruction itself is discussed in Chapter 3. Refer to Chapter 9 for a more complete description of exceptions. Table 2-2. 80386 Reserved Exceptions and Interrupts Vector Number Description 0 Divide Error 1 Debug Exceptions 2 NMI Interrupt 3 Breakpoint 4 INTO Detected Overflow 5 BOUND Range Exceeded 6 Invalid Opcode 7 Coprocessor Not Available 8 Double Exception 9 Coprocessor Segment Overrun 10 Invalid Task State Segment 11 Segment Not Present 12 Stack Fault 13 General Protection 14 Page Fault 15 (reserved) 16 Coprocessor Error 17-32 (reserved)