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1995-08-05
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Extended BASIC Assembler
------------------------
written by Adrian Lees
version 1.00, 3 November 1994
1.10, 5 August 1995
Bug fix: tokenised mnemonics, eg. SIN, COS and ATN
are now accepted correctly.
Documentation: Arc cosine instruction is ACS not ACN
The module ExtBASICasm provides a patch for version 1.05 and 1.06 of BASIC V,
as supplied with RISC OS 3.11 and 3.50 respectively, to allow the direct use
of the extra instructions provided by the ARM3 and ARM610 processors.
Additionally the missing floating-point and general coprocessor instructions
have been added, and the register name LR may now be used in preference
to R14.
To make the necessary changes to the BASIC module it must be located in RAM.
The ExtBASICasm module will therefore attempt to RMFaster the BASIC module
which will require a small amount of memory in the RMA, in addition to that
required by the ExtBASICasm module itself. More importantly, BASIC must not
be active, ie. running, at the time because then the module cannot be removed
to allow it to be moved. Loading ExtBASICasm should therefore be performed
at the command line. It is safe to do this from the ShellCLI, ie. whilst the
desktop is active, even with BASIC programs running because BASIC holds all
its information within the application workspace.
The instructions added by the module are as follows:
ARM3 and ARM610 instructions
----------------------------
SWP{cond}{B} Rd,Rm,[Rn]
ARM610 instructions
-------------------
MCR{cond} CP#,<expression1>,Rd,Cn,Cm{,<expression2>}
MRC{cond} CP#,<expression1>,Rd,Cn,Cm{,<expression2>}
MRS{cond} Rd,<psr>
MSR{cond} <psr>,Rm
MSR{cond} <psrf>,Rm
MSR{cond} <psrf>,<#expression>
Floating-point instructions
---------------------------
Floating point coprocessor data transfer
LDF{cond}prec Fd,[Rn]{,#offset}
LDF{cond}prec Fd,[Rn,#offset]{!}
LDF{cond}prec Fd,<label | expression>
STF{cond}prec Fd,[Rn]{,#offset}
STF{cond}prec Fd,[Rn,#offset]{!}
STF{cond}prec Fd,<label | expression>
Floating point coprocessor register transfer
FLT{cond}prec{round} Fn,Rd
FIX{cond}{round} Rd,Fn
WFS{cond} Rd
RFS{cond} Rd
WFC{cond} Rd
RFC{cond} Rd
Floating point coprocessor data operations
ADF{cond}prec{round} Fd,Fn,<Fm | #value>
MUF{cond}prec{round} Fd,Fn,<Fm | #value>
SUF{cond}prec{round} Fd,Fn,<Fm | #value>
RSF{cond}prec{round} Fd,Fn,<Fm | #value>
DVF{cond}prec{round} Fd,Fn,<Fm | #value>
RDF{cond}prec{round} Fd,Fn,<Fm | #value>
POW{cond}prec{round} Fd,Fn,<Fm | #value>
RPW{cond}prec{round} Fd,Fn,<Fm | #value>
RMF{cond}prec{round} Fd,Fn,<Fm | #value>
FML{cond}prec{round} Fd,Fn,<Fm | #value>
FDV{cond}prec{round} Fd,Fn,<Fm | #value>
FRD{cond}prec{round} Fd,Fn,<Fm | #value>
POL{cond}prec{round} Fd,Fn,<Fm | #value>
MVF{cond}prec{round} Fd,<Fm | #value>
MNF{cond}prec{round} Fd,<Fm | #value>
ABS{cond}prec{round} Fd,<Fm | #value>
RND{cond}prec{round} Fd,<Fm | #value>
SQT{cond}prec{round} Fd,<Fm | #value>
LOG{cond}prec{round} Fd,<Fm | #value>
LGN{cond}prec{round} Fd,<Fm | #value>
EXP{cond}prec{round} Fd,<Fm | #value>
SIN{cond}prec{round} Fd,<Fm | #value>
COS{cond}prec{round} Fd,<Fm | #value>
TAN{cond}prec{round} Fd,<Fm | #value>
ASN{cond}prec{round} Fd,<Fm | #value>
ACS{cond}prec{round} Fd,<Fm | #value>
ATN{cond}prec{round} Fd,<Fm | #value>
URD{cond}prec{round} Fd,<Fm | #value>
NRM{cond}prec{round} Fd,<Fm | #value>
Floating point coprocessor status transfer
CMF{cond}prec{round} Fm,Fn
CNF{cond}prec{round} Fm,Fn
CMFE{cond}prec{round} Fm,Fn
CNFE{cond}prec{round} Fm,Fn
General co-processor instructions
---------------------------------
Coprocessor data operations
CDO{cond} CP#,copro_opcode,Cd,Cn,Cm{,expression}
CDP{cond} CP#,copro_opcode,Cd,Cn,Cm{,expression}
(the values of copro_opcode and the optional expression
must lie within the range 0..15)
Coprocessor data transfer
LDC{cond}{L}{T} CP#,Cd,[Rn]{,#offset}
LDC{cond}{L}{T} CP#,Cd,[Rn,#offset]{!}
LDC{cond}{L}{T} CP#,Cd,<label | expression>
STC{cond}{L}{T} CP#,Cd,[Rn]{,#offset}
STC{cond}{L}{T} CP#,Cd,[Rn,#offset]{!}
STC{cond}{L}{T} CP#,Cd,<label | expression>
Assembler directives
--------------------
To support the assembly of floating-point coprocessor instructions the
following directives are provided:
EQUFS <expression>
EQUFD <expression>
EQUFP <expression>
EQUFE <expression>
These directives accept an expression that evaluates to either an integer
or a real number. The result is then converted into the required precision
and stored in the object code at P%.(or O% if indirect assembly is being used)
The amount of memory allocated by each directive is shown below:
bytes
EQUFS 8
EQUFD 16
EQUFE 24
EQUFP 24 ;not yet implemented
Notes
-----
* Registers are specified in the following form:
ARM registers: R0..R15
Floating-point registers: F0..F7
General co-processor registers: C0..C15
* Coprocessor numbers (CP#) may be specified using either of the following
forms:
P0..P15
CP0..CP15
* Wherever a register or coprocessor number is specified an expression
may be substituted in the usual manner allowed by BASIC V.
This module employs the routines used within BASIC to evaluate all
expressions (eg. register numbers, offsets and labels) and hence its
interpretation of expressions is guaranteed to be the same as BASIC.
* There is a subtle inconsistency between the ARM2/3 and ARM610 datasheets
regarding the ARM's interpretation of the W-bit in the post-indexed LDC/STC
instructions.
The behaviour of each processor is described below:
ARM2áand ARM3
Setting the W bit for post-indexed expressions forces the -TRANS
pin low for the transfer cycle, indicating to the memory system
that no address translation should be performed for this access.
Write-back occurs independently of the setting of the W bit
Note that in user mode the W bit is ignored.
ARM610
The W bit must be set to ensure that write-back occurs.
This module will assemble all post-indexed LDC/STC instructions without
setting the W bit unless the T suffix is appended to the opcode. ie. the
behaviour of the assembler matches the ARM2 rather than the ARM610.
When assembling code for the ARM610 all post-indexed instructions should
include the T suffix to ensure that the W bit is set.
* According to the information in the datasheets, the Debugger module
does not correctly disassemble a number of the coprocessor and
floating-point instructions, and hence a discrepancy between the
operation of the Debugger and ExtBASICasm does not necessarily
indicate an error in the latter.
If, however, you do find an error then please do not hesitate to
contact me:
Post: Adrian Lees
7 Russell Drive
Ampthill
BEDFORD
MK45 2UA
England
Email: eee93023@ibm3090.bham.ac.uk