home
***
CD-ROM
|
disk
|
FTP
|
other
***
search
/
The World of Computer Software
/
World_Of_Computer_Software-02-387-Vol-3of3.iso
/
s
/
simic104.zip
/
EXAMPLES
/
BUSHOLD.NET
next >
Wrap
Text File
|
1993-01-07
|
1KB
|
30 lines
!Documentation
(c) Copyright 1982 Genashor Corp. All Rights Reserved.
This circuit demonstrates the ability of SIMIC to properly handle
the merging of electrical attributes at wireties. This circuit
consists of two tristate drivers on a bus with an active bus hold
circuit used to retain the last driven value. All other known
gate simulators incorrectly predict the final state of the bus
using the stimulus described in the SIMIC run file, BUSHOLD.RUN.
!Delay
!Format Delay= Change=
C= Global delays specified as delay vs. loading curves in
C= [<intercept>,<slope>] format.
Del10 [0,10]
Del100 [0,100]
!Logical
!Format Part= Type= I= O= Odel=
Type=bushold I=EnA,DataA,EnB,DataB O=E Olod=1
C= These are the bus driving devices:
u1 tpadn EnA,DataA Bus Del10
u2 tpadn EnB,DataB Bus Del10
C= This is the Bus Hold circuit (Two small geometry inverters) :
u3 inv Bus NBus Del10 ODrive=resistive
u4 inv NBus Bus Del100 ODrive=resistive $
Ilod=1
C= This is a receiving device off the bus (which adds 1 pF loading)
u5 and Bus E Del10 Ilod=1