Unified Memory Structure

Overview:   An efficient, high-throughput memory system contributes to the overall processing capabilities for all of O2's specialized engines and associated pathways.   Data coming in and out of memory passes through the memory controller residing on O2's MRE ASIC.   Data between this ASIC and memory can achieve data rates of up to 2 Gbytes/s from O2's synchronous DRAM implementation.

In addition to high speed system pathways, the memory subsystem is centrally located for direct access by the CPU, graphics, imaging, video and display functions. This, combined with O2's shared memory scheme, is the essence of O2's UMA Architecture.

Features:

• Unified Memory Architecture
• Free memory allocation scheme
• Memory tile structures
• 4 banks of dual-interleaved SIMMs per system
• 256-bit SDRAM memory word every cycle at 66 MHz
• SDRAMs with CAS latency of 2, page rate of 1
• 32 to 256 MByte capacity with 16 Mbit SDRAMs
• 128 to 1024 MByte capacity with 64 Mbit SDRAMs
• SIMMS types can be mixed, but in pairs.

• All engines can access data in shared memory space
• Virtually unlimited texture memory (constrained by main memory)