common i.c.'s
pin assignments and logic

7417574ls17574f175
quad d-type flip-flop

pin assignment

logic diagram

truth table

operating mode inputs outputs mr cp dN qN qN rESET (CLEAR) lOAD "1" lOAD "0" l h h x x H L l h l h l h

h = high VOLTAGE LEVEL STEADY STATE. H = high VOLTAGE LEVEL ONE SETUP TIME PRIOR TO THE low-TO-high CLOCK TRANSITION. l = low VOLTAGE LEVEL STEADY STATE. L = low VOLTAGE LEVEL ONE SETUP TIME PRIOR TO THE low-TO-high CLOCK TRANSITION. = low-TO-high CLOCK TRANSITION. x = DON'T CARE.

74ls24174f241
octal buffer, tri-state

pin assignment

logic diagram

truth table inputs outputs oeA iA oeB iB yA yB l l h l h x h h l l h x l h (z) l h (z) h = high VOLTAGE LEVEL l = low VOLTAGE LEVEL x = dON'T CARE (z) = high IMPEDANCE (OFF) STATE

74ls266
quad 2-input exclusive nor gate (open collector)

pin assignment

logic diagram

truth table inputs output a b y l l h h l h l h h l l h h = high VOLTAGE LEVEL l = low VOLTAGE LEVEL