This section is posted separately as the "Personal Computer Chiplist"
and archived along side this FAQ. Refer to section one for
instructions on retrieving this file.
Newsgroups: comp.sys.ibm.pc.hardware.chips,comp.sys.ibm.pc.hardware.systems,
comp.sys.ibm.pc.hardware.misc,comp.sys.intel
Subject: Personal Computer CHIPLIST 7.0 part * of *
From: offerman@einstein.et.tudelft.nl (Aad Offerman)
Summary: This list contains the various CPU's and NPX's and their features,
used in the IBM PC, IBM PC/XT, IBM PC/AT, IBM PS/2 and compatbles,
and the differences between them.
Archive-name: pc-hardware-faq/chiplist
[From: jabram@ichips.intel.com (Jeff Abramson)] This is a hard question. You have tradeoffs between price, performance, compatibility, upgradebility, and power consumption. As a desktop unit owner, you probably have less concerns about power, but as a laptop owner, this is very important. The frequency of the CPU defines how fast its internal clock runs. This defines how fast instructions are executed. In many ways, this is meaningless, because a RISC machine (MIPS) running at 100MHz may in reality be slower than a 50Mhz i486 because a RISC system must execute more instructions to perform the same function (in some cases). Even when comparing processors in the same family, this info can be misleading. For example, an Intel486-25 is faster than an AMD386-40, since the 486 has microarchitectural advancements over the 386. The same can be said for the Pentium, where a 66Mhz Pentium is twice as fast as a 66MHz 486. For compatibility, keep in mind that the Intel parts are the basis for all of these processors. Therefore you always run the risk that an imitator's part may not be compatible. AMD [486] chips are compatible because they are copied. For some of you, these factors may be important. As far as upgradability goes, this depends on both your motherboard and the processor. If you purchase a 486DX, then you can upgrade to a DX2 and double your internal clock simply by buying an overdrive chip if your motherboard has the ZIF socket. If it doesn't then you can replace the CPU with a DX2. Many new 486 motherboards contain overdrive sockets for the Pentium chip that is pin compatible.
[From: jabram@ichips.intel.com (Jeff Abramson)] The Intel386DX contains full 32 bit buses for external data, internal data, and address. The Intel386SX contains a smaller 16 bit external data bus, and a smaller 24 bit address bus. The Intel486DX contains a floating point unit, the Intel486SX does not. A common rumor is that the 486SX is simply a DX part that has a failure in the floating point unit, so it has been disabled and the part has been produces as an SX. This was true for early production parts and samples, but not for the mass produces SX parts that we see today.
[From: jabram@ichips.intel.com (Jeff Abramson)] ZIF stands for Zero Insertion Force, and describes a socket on your motherboard that supports an upgrade processor (overdrive processor). In general, an overdrive upgrade works in conjunction with your original processor so you cannot remove the original processor after upgrade. NOTE: Some motherboards do not have a ZIF socket so you must replace the existing processor to upgrade.
[From: jabram@ichips.intel.com (Jeff Abramson)] Overclocking is a term generally used to describe how you have increased the clock frequency on your board to run your system at a higher speed. For example, if you plug a 25MHz i486 into a board that is configured to run a 33MHz i486, then you are overclocking your CPU. Most boards allow you to configure your clocking via jumpers, and others require a new clock oscillator. Although users have had success with overclocking, it is a dangerous practice for two reasons. First, the chip has been designed to meet a certain speed. Therefore, some circuits do not have the margin to operate at a higher frequency. The chips coming from a wafer have various speed specs (statistical distribution), so you may be lucky and own a CPU that has the circuit margins you need to overclock. But you don't know - and if you overclock, you may get data failure. The data failure may be reproducable - and therefore avoidable, but most likely not. Second, you have reliability concerns when overclocking. Overclocking means faster frequency, which means more current and power. This can lead to real failures in your CPU. Electromigration is one such failure where metal lines in your CPU will actually break or connect if they get too much current. This is irreversable, and most likely not covered under warranty. So when can you overclock? Really only if you don't care about burning out your CPU and you don't care if you get wrong data every now and then. If you own a machine and you use it just for games, then overclocking may be something to try - and you simply upgrade to a new CPU when you burn out the current one. Otherwise, it's not worth the small performance gain.
The two processors are relatively close for overall usage. The DX-50 has more I/O bandwidth and the DX2-66 has more computational power.
See reference in: "What are the differences between the 80x86 CPUs?"
[From: jruchak@mtmis1.mis.semi.harris.com (John Anthony Ruchak)] If you do a lot of number-crunching with CAD/CAM applications, spreadsheets, and the like, a math co-processor is likely to increase performance. If on the other hand, your primary work is word processing, a math co-processor will have barely any effect at all. Also, a math co-processor will not provide any benefit if your CPU already has one built-in (486/586-DX chips). In addition, a math co-processor is not likely to improve the over-all performance of Microsoft Windows, except when you are running the afore-mentioned number-crunching programs.
[From: Shaun Burnett (burnesa@cat.com)] No, they are not pin compatible. The 486DX and above contain an on-chip floating point unit. Therefore, a 387 (SX or DX) math coprocessor is not needed. All software written for a 387 coprocessor will run on your 486. If you want a math coprocessor for a 486SX, you need to purchase the 487SX or a 486 Overdrive processor. While we're talking about math coprocessors, I'll make a brief note about the Weitek. Some motherboards may have a socket for a Weitek math coprocessor. These coprocessors are not compatible with the Intel 387 math coprocessor and should only be used if your software requires it. The Weitek 3167 replaced the Weitek 1167 and is for the 386 while the Weitek 4167 is for a 486.
Under certain circumstances, based on divisor ranges, mantissa bit 13
and beyond can be incorrect during floating point division. This
problem effects the functions:
FDIV, FDIVR, FPTAN, FPATAN, FPREM and FPREM1
in single, double and extended precision modes. Many programs and
operating systems are already incorporating software patches to work
around the problem. For most users, the accuracy supplied by the
Pentium even without a patch is more than enough. However, since the
media hype made the problem sound like it would have a serious impact
on everyone, Intel has agreed to replace all faulty Pentiums free of
charge.
If you purchased your Pentium in 1994 or earlier, chances are near 100% that it has the problem. Purchasing it after this date does not guarantee a bug free CPU. The problem existed in all speed grades. The program: ftp.intel.com:/pub/IAL/pentium/$cpuid.exe - executable ftp.intel.com:/pub/IAL/pentium/cpuidf.txt - instructions is Intel's official program to identify CPUs with the FDIV bug. This program uses the CPU ID register to compare against the list of known buggy Pentiums rather than attempting to reproduce the bug through software, so it should be accurate even if the OS has a software FDIV patch already in place.
From the US and Canada, call 1-800-628-8686. For other countries, see the file: ftp.intel.com:/pub/IAL/pentium/cpusup.txt Be sure to have your credit card handy. Intel won't place any charges on it as long as you return the defective Pentium within 30 days. If you don't have a credit card, contact Intel and they will refer you to a local service center.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)]
Read/write memory in computers is implemented using Random Access Memory
chips (RAMs). RAMs are also used to store the displayed image in a video
board, to buffer frames in a network controller or sectors in a disk
controller, etc. RAMs are sold by their size (in bits), word width (how
many bits can you access in one cycle), and access time (how fast you
can read a location), among other characteristics.
SRAMs and DRAMs
---------------
RAMs can be classified into two types: "static" and "dynamic."
In a static RAM, each bit is represented by the state of a circuit
with two stable states. Such a "bistable" circuit can be built with four
transistors (for maximum density) or six (for highest speed and lowest
power). Static RAMs (SRAMs) are available in many configurations.
(Almost) all SRAMs have one pin per address line, and all of them
are able to store data for as long as power is applied, without any
external circuit activity.
In a dynamic RAM (DRAM), each bit is represented by the charge on a
*very* small (30-50 femptofarads) capacitor, which is built into a
single, specialized transistor. DRAM storage cells take only about
a quarter of the silicon area that SRAM cells take, and silicon
area translates into cost.
The cells in a DRAM are organized into rows and columns. To access
a bit, you first select its row, and then you select its column.
Unfortunately, the charge leaks off the capacitor over time,
so each cell must be periodically "refreshed" by reading it and
writing it back. This happens automatically whenever a row is accessed.
After you're finished accessing a row, you have to give the DRAM time
to copy the row of bits back to the cells: the "precharge" time.
Because the row and column addresses are not needed at the same
time, they share the same pins. This makes the DRAM package smaller
and cheaper, but it makes the problem of distributing the signals
in the memory array difficult, because the timing becomes so
critical. Signal integrity in the memory array is one of the
things that differentiate a lousy motherboard from a high quality
one.
EDO RAM
-------
Extended Data Out is a minor variation on the control logic in the DRAM
chip that tells the output pin when to turn on.
In a "standard" (Fast Page Mode) DRAM, the output pin turns off as soon
as the Column Address Strobe (CAS) pin goes false. The problem with
that comes when you try to do a "burst" read cycle wherein Row Address
Strobe (RAS) is held true while CAS toggles up and down real fast. The
RAM only drives the data half the time and the other half the time is
wasted. This makes a cache fill cycle take longer than it otherwise
might, because the cache really can't look at the data unless the DRAM
is driving it. (You can't store data on a PC board trace because of
inductive kick and other effects. Trust me, you novice board designers
out there.)
In an EDO (Nippon Electric Corp calls it Hyper Page Mode) DRAM, the
output pin keeps driving until RAS and CAS *both* go false. Your cache
can fill faster because the whole duration (grossly oversimplifying) is
usable as sampling time.
(Why didn't they do it that way to begin with, some of you are asking.
The EDO DRAM can't read and write in the same RAS cycle. The FPM can.
That used to be important, but it's not a capability that PCs with
caches happen to use.)
With today's (cost-oriented) SRAM and ASIC technology, only synchronous
SRAMs can take much advantage of the extra bandwidth. That's why you don't
get a big benchmark boost when you switch to EDO but leave your cache
the way it was before. You have to upgrade both to see the improvement.
Because it's a minor control variation, the chip maker can do most of the
wafer fabrication steps before deciding whether a wafer full of chips will
be FPM or EDO. Both types can be made on the same process and circuit
design, and tested on the same equipment. Therefore, once they all tool
up to make it, EDO and FPM will cost about the same. Right now (July '95)
EDO costs more only because it's still rare.
SIMMs and SIPPs
---------------
Through the 1970s, RAMs were shipped in tubes, and the board makers
soldered them into boards or plugged them into sockets on boards.
This became a problem when end-users started installing their own
RAMs, because the leads ("pins") were too delicate. Also, the
individual dual in-line package (DIP) sockets took up too much board
area.
In the early 1980s, DRAM manufacturers began offering DRAMs on tiny
circuit boards which snap into special sockets, and by the late '80s
these "single in-line memory modules" (SIMMs) had become the most popular
DRAM packaging. Board vendors who didn't trust the new SIMM sockets
used modules with pins: single inline pinned packages (SIPPs),
which plug into sockets with more traditional pin receptacles.
PC-compatibles store each byte in main memory with an associated
check bit, or "parity bit." That's why you add memory in multiples
of nine bits. The most common SIMMs present nine bits of data at
each cycle (we say they're "nine bits wide") and have thirty contact
pads, or "leads." (The leads are commonly called "pins" in the trade,
although "pads" is a more appropriate term. SIMMs don't *have* pins!)
At the high end of the PC market, "36 bit wide" SIMMs with 72 pads
are gaining popularity. Because of their wide data path, 36-bit SIMMs
give the motherboard designer more configuration options (you can
upgrade in smaller chunks) and allow bandwidth-enhancing tricks
(i.e. interleaving) which were once reserved for larger machines.
Another advantage of 72-lead SIMMs is that four of the leads are used
to tell the motherboard how fast the RAMs are, so it can configure
itself automatically. (I do not know whether the current crop of
motherboards takes advantage of this feature.)
"3-chip" and "9-chip" SIMMs
In 1988 and '89, when 1 megabit (1Mb) DRAMs were new, manufacturers
had to pack nine RAMs onto a 1 megabyte (1MB) SIMM. Now (1993) 4Mb DRAMs
are the most cost-effective size. So a 1MB SIMM can be built with
two 4Mb DRAMs (configured 1M x4) plus a 1Mb (x1) for the check-bit.
VRAMs
-----
In graphics-capable video boards, the displayed image is almost
always stored in DRAMs. Access to this data must be shared between
the hardware which continuously copies it to the display device (this
process is called "display refresh" or "video refresh") and
the CPU. Most boards do it by time-sharing ordinary, single-port
DRAMs. But the faster, more expensive boards use specialized DRAMs
which are equipped with a second data port whose function is tailored
to the display refresh operation. These "Video DRAMs" (VRAMs)
have a few extra pins and command a price premium. They nearly double
the bandwidth available to the CPU or graphics engine.
(As far as I know, the first dual-ported DRAMs were built by Four-
Phase Systems Inc., in 1970, for use in their "IV-70" minicomputers, which
had integrated video. The major DRAM vendors started offering VRAMs
in about 1983 [Texas Instruments was first], and workstation vendors
snapped them up. They made it to the PC trade in the late '80s.)
Speed
-----
DRAMs are characterized by the time it takes to read a word,
measured from the row address becoming valid to the data coming out.
This parameter is called Row Access Time, or tRAC. There are many
other timing parameters to a DRAM, but they scale with tRAC
remarkably well. tRAC is measured in nanoseconds (ns).
A nanosecond is one billionth (10 e-9) of a second.
It's so difficult to control the semiconductor fabrication processes,
that the parts don't all come out the same. Instead, their performance
varies widely, depending on many factors. A RAM design which would
yield 50 ns tRAC parts if the fab were always tuned perfectly, instead
yields a distribution of parts from 80 to 50. When the plant is new,
it may turn out mostly nominal 70 ns parts, which may actually deliver
tRAC between 60.1 ns and 70.0 ns, at 70 or 85 degrees Celcius and
4.5 volts power supply. As it gets tuned up, it may turn out mostly 60
ns parts and a few 50s and 70s. When it wears out it may get less
accurate and start yielding more 70s again.
RAM vendors have to test each part off the line to see how fast it is.
An accurate, at-speed DRAM tester can cost several million dollars, and
testing can be a quarter of the cost of the parts. The finished parts
are not marked until they are tested and their speed is known.
The memory between 640k and 1Meg is used for the BIOS, the video aperture, and a number of other things. With the proper memory manager, DOS can take advantage of it. Many systems, however, won't identify its existence on boot. This does not mean it isn't there.
Individual DRAMs are marked with their speed after they are tested. The mark is usually a suffix to the part number, representing tens of nanoseconds. Thus, a 511024-7 on a SIMM is very likely a 70 ns DRAM. (vendor numbering scheme table to be added)
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)] There is no reliable formula for deriving the required RAM speed from the clock rate or wait states on the motherboard. Do not buy a motherboard that doesn't come with a manual that clearly specifies what speed SIMMs are required at each clock rate. You can always substitute *faster* SIMMs for the ones that were called out in the manual. If you are investing in a substantial quantity of RAM, consider buying faster than you need on the chance you can keep it when you get a faster CPU. That said, most 25 MHz and slower motherboards work fine with 80 ns parts, most 33 MHz boards and some 40 MHz boards were designed for 70 ns parts, and some 40 MHz boards and everything faster require 60 ns or faster. Some motherboards allow programming extra wait states to allow for slower parts, but some of these designs do not really relax all the critical timing requirements by doing that. It's much safer to use DRAMs that are fast enough for the no-wait or one-wait cycles at the top end of the motherboard's capabilities.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)] Almost always. But there are exceptions. 1. Some motherboards do not supply enough refresh address bits for a 4Mb x1 or a 1Mb x4 DRAM. These old motherboards will not work with 4 MB 9-chip SIMMs or 1 MB 3-chip SIMMS. 2. Some EL CHEAPO motherboards do not have proper terminations on the lines which drive the DRAM array. These boards may show only marginal compatibility with various SIMMs, not working with all prefectly good SIMMs you try, favoring SIMMs with parameters skewed towards one end or another of the allowed ranges. In some cases, most of the SIMMs you happen to try might be 9-chip modules, and in other cases they might be 3-chip modules. A random selection of a dozen SIMMs might lead you to conclude the motherboard doesn't "work" with 3-chip modules, or with a "mixture" of 3-chip and 9-chip modules. You might find the real solution is to use SIMMs one speed faster than the manual calls for, because the particular motherboard design just cuts too many things too close.
[From: rbean@execpc.com (Ron Bean)] All 72-pin SIMMs are 32 bits wide (36 with parity), but double-sided SIMMs have four RAS (Row Address Strobe) lines instead of two. This can be thought of as two single-sided SIMMs wired in parallel. But since there is only one set of data lines, you can only access one "side" at a time. Usually, 1Mb, 4Mb, and 16Mb 72-pin SIMMs are single-sided, and 2Mb, 8Mb, and 32Mb SIMMs are double-sided. This only refers to how the chips are wired-- SIMMs that are electrically "single-sided" may have chips on both sides of the board. Most 486 motherboards use memory in banks of 32 bits (plus parity), and may treat a double-sided SIMM as "two banks" (see your motherboard's manual for details). Some can take four SIMMs if they're single-sided, but only two if they're double-sided. Others can take four of either type. Pentium (and some 486) motherboards use pairs of 72-pin SIMMs for 64-bit memory. Since double-sided SIMMs can only access 32 bits at a time, you still need to use them in pairs to make 64 bits.
[From: gnewman@world.std.com (Gary Newman)]
Memory errors are categorized as either "HARD" failures, or "SOFT"
failures. Either form of failure can cause anything from an
unexplained system crash to a nice warning message saying:
"soft error corrected at address 0x00343487 pattern 0x0004000"
The methods that have been developed to deal with these failures are
outlined here.
HARD ERRORS occur when one or more bits in a memory consistently read
back different data than is written to them. There are a myriad of
causes for these failures including failed: memory cells, memory
chips, solder connections, SIMM socket connections, and circuit
traces. Hard errors are signs of truly broken hardware and require
physical repair to correct. If you are lucky, simply removing and
reinserting a SIMM in its socket is sufficient to make a better
connection. Usually it means you have a bad memory chip or
motherboard.
SOFT ERRORS occur when one or more bits in a memory read back
different data than was written to them, BUT after rewriting the same
data the memory reads it back correctly. In other words: the error is
transient and not reproducible. Soft errors are usually intermittent
with anywhere from hours to years between occurrences. There are two
design causes for soft errors, motherboard noise and internal DRAM
noise due to alpha particles or marginal circuits. On a well designed
motherboard, noise does not cause measurable soft errors unless the
board is defective.
Both soft errors and hard errors can be caused by static electricity
damage or otherwise defective parts. Unfortunately these problem
parts don't always cause instant hard errors. Failures can appear
weeks or months after initial damage as soft (due to degraded
performance) or hard errors. "Burn in" (which is heavy exercise of
hardware for it's first few days) is a method used by manufacturers to
weed out these failures at the factory.
Users of computers can also "change the design" of their computer
without understanding the ramifications of what they are doing.
Adding "SIMM converters" to fit 30 pin SIMMs into a 72 socket,
decreasing the DRAM refresh rate, overclocking, and changing the DRAM
access timing all can push a design beyond allowable specifications.
The problems frequently show up as parity errors, or on a system
without parity just as system flakiness.
INTERNAL DRAM NOISE is caused by two different sources. Marginal
circuits on the DRAM are one source that quality manufacturers nearly
always find at the factory through testing of the parts. HOWEVER,
SOME MARGINAL DRAM MAKES IT TO MARKET! The result is a part that
produces a soft error more often than normal (see below). A system of
mine had such a part that produced a single bit error (always in the
same DRAM chip of a SIMM) once a month.
ALL DRAM PRODUCES SOFT ERRORS DUE TO ALPHA PARTICLES. The plastic
packaging of the DRAM contains small amounts of radioactivity that
produce alpha particles. These are energetic, fast moving, helium
atoms which are missing their electrons. When an alpha particle
emitted by the packaging hits a sense line in the DRAM during a read
cycle, the noise it produces causes the sense amplifier to misread the
data. Then, as with all DRAM, the memory cell is refreshed after
reading and the bad data becomes permanent.
Memory Error Likelyhood
In 1990, alpha particle induced soft errors occurred in 16 Mb computer
systems at the mean rate of roughly one error every 3 months.
Improved DRAM designs have greatly reduced that error rate so that
today the mean error rate in a 16 Mb system is roughly one bit error
every 16 years. Note that since the errors only occur when memory is
being read, faster access rates to memory make for shorter times
between errors. When a computer is idle, the only DRAM access is due
to infrequent memory refresh cycles. When a program is constantly
reading from memory at the maximum memory bandwidth, bit errors occur
more frequently.
With computers DESIGNED to produce memory errors at a rate of roughly
one bit error per system per 16 years, manufacturers have been cutting
costs by not including "parity" memory with systems they sell. THIS
ERROR RATE PRODUCES A SINGLE BIT ERROR DURING A TYPICAL THREE MONTH
WARRANTY IN 1.6 PERCENT OF ALL THE COMPUTERS SOLD! There are two main
risks of using a system without parity memory. One is that the
computer user will have no warning when a memory error (soft or hard)
has occurred, and the other is that side effects of the error may be
hard to isolate. A single bit error can produce side effects such as:
a wrong result in a spreadsheet, erroneous data in a database, a bug
in the instructions of an application program or operating system
causing mysterious system crashes.
With 100 million computers in use today, we should expect roughly
6 million single bit errors per year. Computer hardware and software
companies must receive thousands of "side effect" bug reports and
support calls due to memory errors alone. The costs of NOT including
parity memory must be huge!
[From: gnewman@world.std.com (Gary Newman)]
Memory diagnostics and Power On Self Tests (POSTs) find only hard
errors WHEN THE USER LOOKS FOR THEM. The POST only reports these
errors when a computer is booted. So unless a memory diagnostic
program is run by the user, a hard memory error may go undetected
until the next reboot. The effects of an error can spread far and
wide during that time. Some systems BIOS allows the user to disable
POST to speed up reboot. Beware that doing this can cause widespread
data corruption if a hard error is present on a system without parity
memory.
The ONLY method of finding hard or soft memory errors during operation
is the use of PARITY MEMORY. This is simply the addition of one extra
bit for every byte of memory to the computer, increasing memory SIMM
costs by about 10% due to packaging economics. For a 16 Mb memory
today parity adds about $50 to the end user price of the computer
system. SOFTWARE CANNOT REPLACE THE FUNCTION OF PARITY MEMORY!
In its simplest form, hardware already in all computers manufactured
today uses information in the parity memory. This allows it to detect
any single bit memory errors before the computer can make any use of
the bad data. Use of parity memory prevents the error from
propagating and producing side effects. The only user unfriendly
aspect to this is that computers without ECC (see below) can only halt
the running program to prevent the use of the bad data. However, that
is almost always better, and less costly, than allowing the spread of
bad data.
At its best, the OS on the computer system can display a warning that
a memory error occurred in a specific SIMM and that the program is
being halted. This is typical for the Unix OS. If the error occurs
in the OS itself, the whole system is halted. The MSDOS operating
system appears to leave the problem to the system's BIOS to deal with.
The better BIOSs will display a message and halt. The worst will
simply freeze. All of these alternatives are better and less costly,
than allowing the spread of bad data.
It is interesting to note that Pentium computers access memory 64 bits
at a time, allowing use of Error Correcting Circuits (called ECC) when
parity memory is included. The cost of adding ECC to the memory
interface chips is modest, and most server computers have done
this. The result is that soft errors can not only be detected, but
also corrected on the fly without effecting the running programs.
Computers that do this produce warning messages such as:
"soft error corrected at address 0x00343487 pattern 0x0004000"
so you know which SIMM produced the error. Frequent errors in the
same SIMM indicate a bad memory chip. That's how we found the SIMM
that produced one error a month for three months straight! Single bit
hard errors can also be corrected on the fly. A single burned out
memory bit or bad SIMM pin is "worked around" by the ECC. No need to
fix it until a convenient time comes around.
What about errors that parity let's slip by? Those are double bit
errors and are thus expected once every few thousand years.
Perhaps double bit errors will become important when there are
billions of computers in use... or gigabytes of DRAM on the average
computer.
[From: gnewman@world.std.com (Gary Newman)] Perhaps the lack of widespread knowledge about memory errors is the cause of the near eradication of parity memory. In that case, I hope the above has helped spread the word about an inexpensive time, money, and anxiety saver. Computers based on the Intel Triton (Triton-I) chipset CANNOT DETECT MEMORY ERRORS. In other words, Intel chose to not support parity memory with this chipset. Beware that buying a system based on Triton will leave you no future way to add parity error detection to your system. For any computer system where it's worth spending $50 to avoid the annoying, and possibly quite damaging, effects of memory errors PARITY MEMORY IS A MUST. On some computer systems the owner is willing to take some pain in order to save the $50 that parity memory adds in costs. If your computer will be used solely to play games or you don't mind occasionally having corrupt files or flaky programs then you may want to consider a system which has no memory error detection.
[From: gnewman@world.std.com (Gary Newman)] Once you've decided you want a computer that supports parity error detection, you will find that nearly all mainstream mail order systems are not available with it. Here are a few approaches that work. Buy a corporate or server system advertised with parity support. Dell Optiplex, HP Vectra, and others are available, but usually at a "corporate" priced premium of $600 or so. Buy from a local system builder who will provide parity support. Purchase a system with parity support but without parity SIMMs. All intel Neptune based P5 computers have such support. Then swap out the non-parity SIMMs after replacing them with parity simms you purchased from one of the many memory vendors. Then the non-parity SIMMs can be either sold to vendors who resell, or put in a game system you may have hanging around.
The precise method is to count the number and type of each chip (after looking them up in a databook for that DRAM manufacturer). However, you can get a good guess just by counting the number of chips. DRAMs (for PC SIMMs) are either 1 or 4 bits wide. The total bit width is 8 or 9 (for 30 pin SIMMs) and 32 or 36 (for 72 pin SIMMs). DRAMs to hold parity are usually 1 bit wide to allow byte writes. Some examples: 2 chips: 8 bit (2x4bit) - no parity 3 chips: 9 bit (2x4bit + 1x1bit) - parity 8 chips: 8 bit (8x1bit) or 32 bit (8x4bit) - no parity 9 chips: 9 bit (9x1bit) - parity 12 chips: 36 bit (8x4bit + 4x1bit) - parity Some new 72 pin SIMMs have two 32 (or 36) bit banks per SIMM and therefore have double the number of chips as a normal SIMM. It also seems that some cheap SIMMs have begun using 'fake' parity on SIMMs; XOR gates that generate parity from 8 bit data rather than store and recall the actual parity generated by the DRAM controller. The only way to tell if you've been taken by one of these fake parity SIMMs is to look up all of the suspected parts in a DRAM databook.
Yes, just about all SIMMs are compatible, be they from another personal computer, a mainframe, or even a laser printer, though are a few some odd systems out there. There are three significant issues: speed, parity and number of pins (data width). Speed is obvious, check the rating, ie: 70ns, to make sure they meet the minimum requirements of your system. Parity either exists or doesn't exist and can be identified by an extra bit per byte, ie: 9 bits or 36 bits. If your system does not require parity, you can still use SIMMs with parity. If, however, your system does require parity, you can't use SIMMs without parity. For this case, many PC's have an option to disable the parity requirement via a jumper or BIOS setting; refer to your motherboard manual. The final issue is the number of pins on the SIMM; the two most common are 30 pins (8 or 9 bit SIMMs) and 72 pins (32 or 36 bit SIMMs); the second is physically larger thus the one can not be used in the other. A few motherboards have both types of sockets.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)] Modern motherboards are equipped with variable clocks and features for tuning board performance at each speed. The BIOS knows how to program the register bits which control these options. 1. Wait states may be adjustable to allow for slower DRAMs or cache RAMs. If you don't have a motherboard manual, or it doesn't say, then you will just have to experiment. 2. Sometimes a wait or two on a write is required with write-through cache. The programming allows for slower DRAMs. The extra wait state may cost you enough time that you would do better running at a slower clock rate where the wait state is not required. 3. Burst rates refer to the number of wait states inserted for each longword access in the cache fill cycle. Bob Nichols (rnichols@ihlpm.ih.att.com) adds: These numbers refer to the number of clock cycles for each access of a "burst mode" memory read. The fastest a 486 can access memory is 2 clock cycles for the first word and 1 cycle for each subsequent word, so "2-1-1-1" corresponds to "zero wait states." Anything else is slower. How fast you can go depends on the external clock speed of your CPU, the access time of your cache SRAMs, and the design of the cache controller. It can also be affected by the amount of cache equipped, since "x-1-1-1" is generally dependent on having 2 banks of cache SRAMs so that the accesses can be interleaved. With a 50MHz bus (486DX-50), few motherboards can manage "2-1-1-1" no matter how fast the SRAMs are. At 33MHz or less (486DX-33, 486DX2-66), many motherboards can achieve "2-1-1-1" if the cache SRAMs are fast enough and there are 2 banks equipped (cache sizes of 64KB or 256KB, typically).
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)]
Why cache improves performance
------------------------------
Today's microprocessors ("uPs") need a faster memory than can be made
with economical DRAMs. So we provide a fast SRAM buffer
between the DRAM and the uP. The most popular way to set it up is
by constructing a "direct mapped cache," which is the only setup
I'll describe here.
Generic motherboard cache architecture
--------------------------------------
The direct mapped cache has three big features:
1. a "data store" made with fast SRAMs,
2 a "tag store" made with even faster SRAMs, and
3. a comparator.
The data store is the chunk of RAM you see in the motherboard price
lists. It holds "blocks" or "lines" of data recently used by the CPU.
Lines are almost always 16 bytes. The address feeding the cache is
simply the least significant part of the address feeding main memory.
Each memory location can be cached in only one location in the data
store.
There are two "policies" for managing the data store. Under the
"write-back" (or "copy-back") policy, the master copy of the data is
in cache, and main memory locations may be "stale" at times. Under
"write-through", writes go immediately to main memory as well as to
cache and memory is never "stale."
The tag store mantains one "word" of information about each line of
data in the data store.
In a "write-back" or "copy-back" cache, the tag word contains two items:
1. the part of the main memory address that was *not*
fed to the data store, and
2. a "dirty" bit.
A write-through cache doesn't need a dirty bit. The tag store is
addressed with the most significant address bits that are being fed to
the data store. The tag is only concerned with the address bits that
are used to select a line. With a 16 byte line, address bits 0
through 3 are irrelevant to the tag.
An example: The motherboard has 32 MB main memory and 256 KB cache.
To specify a byte in main memory, 25 bits of address are required: A0
through A24. To specify a byte in data store, 18 bits (A0 through
A17) are required. Lines in cache are 16 bytes on 16 byte boundaries,
so only A4 through A17 are required to specify a line. The tag word
for this system would represent A18 through A24 (plus dirty bit). The
tag store in this system would be addressed by A4 through A17,
therefore the tag store would require 16 K tag words seven bits wide.
The dirty bit is written at different times than the rest of the tag,
so it might be housed separately, and this tag store might be built in
three 16K x4 SRAMs.
What happens when it runs
-------------------------
Each motherboard memory cycle begins when the uP puts out a memory
address. The data store begins fetching, and simultaneously the
tag begins fetching. When the tag word is ready, the Comparator
compares the tag word to the current address.
If they match, a cache hit is declared and the uP reads or writes
the data store location. If the hit is a write, the copy-back
cache marks the line "dirty" by setting its dirty-bit in the line's
tag word. The write-through motherboard simultaneously stores the
write data in data store and begins a DRAM write cycle. The uP
moves on.
If the tag word doesn't match, what a bummer, it's a cache miss.
If the line in cache is dirty, double bummer, the line must be
copied back to main memory before anything else can happen. All
16 bytes are copied back, even if the hit was a one-byte write.
This data transfer is called a "dirty write flush."
On a read-miss, the motherboard has to copy a line from main memory
to cache (and update the tag, the whole operation is called a "cache
fill"), and the uP can stop waiting as soon as the bytes it wants
go by. On a write-miss, the caches I've worked with ignore the
event (that's an oversimplification) and the main memory performs
a write cycle. I've heard of systems that fill on a write-miss,
that is they replace the cache line whenever it misses, read or
write, dirty or not. I've never seen such a system.
Terms
-----
The 486, the 68020, and their descendants have caches on chip.
We call the on-chip cache "primary" and the cache on the
motherboard "secondary." The 386 has no cache, therefore the cache
on a 386 motherboard is "primary." I like to call the DRAM array
"core" for brevity. Motherboard = "mb." Megabyte = "MB."
Problems
--------
I added "core" and I had to disable my secondary cache to
get the board running. Or, I added core and performance took a dive.
Disabling secondary cache improved it, but still real slow.
What happened?
Whenever you are adding memory and you cross a power-of-2
address boundary, another address bit becomes interesting to the
tag. That is, the tag does not care when you add your 8th MB
(MB) but it cares a lot about the new address bit 24 when you add
your 9th MB, or your 17th (bit 25). Evidently, at the low-price
end of the mb market there are boards with not enough tag RAM
sockets to support all the core they can hold. Most of these EL
CHEAPO mbs don't even try to use cache in the region beyond the
tag's coverage. Some of them don't have the logic to stay out or
the BIOS doesn't know to enable it. These boards just don't run
right.
Do not buy a mb if you are not sure it can cache all of core. The
worst case is with core fully stuffed with whatever the board claims
to hold, and the smallest cache configuration. Some motherboards
ask you to add cache when you add core, so that they don't have to
provide for that worst case tag width. These motherboards may ask
you to move some jumpers in the tag area. The jumpers control
which address bits the tag looks at. Do not buy a motherboard if
you don't know how to set all the jumpers.
Look in your motherboard manual. Each motherboard is different. You will have to add or replace cache RAMs and move jumpers.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)] Perhaps you don't *have* to for the board to run, but the missing RAM will cost you performance. Most "write-back" mbs cope with the missing RAM by treating all lines as dirty. You get a lot of unneccessary write cycles; you might even do better with write-through. Your bargain-basement no-documentation no-brand mb might not have the pullup resistor on that socket, and it might run for a second, ten minutes, or ten years with that pin not driven. I think it's a pointless risk to leave the socket empty.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)] Only the person who designed your mb knows for sure. There is no simple formula related to clock rate. However, most people tell me their 33 MHz mbs' manuals call for 25 ns data store and 20 ns tag store, and their 40 and 50 MHz mbs want 20 ns data store and 15 or 12 ns tag. Tqhe tag has to be faster than data store to make time for the comparator to work. Do not buy a motherboard if you do not know what speed and size of cache RAMs it requires in all its speeds and configurations. If you're not sure, it doesn't hurt to use faster RAMs than your manual calls for. If your manual says 20 ns for location x and you happen to have 15 ns parts, it's ok to "mix" the speeds. It's ok to "mix" RAMs from more than one manufacturer. However, the faster RAMs will not buy you more performance.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)] For most applications, copy-back gives better performance than write-through. The amount of win will depend on your application and may not be significant. Write-through is simpler, but not by much any more.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)] At the high end of the mb market, caches are available with more than one set. In these caches, the data store is broken into two or four parts, or sets, with a separate tag for each. On a miss, clever algorithms (such as Least Recently Used) can be used to pick which set will be filled, because each set has a candidate location. The result is a higher hit rate than a direct mapped (single set) cache the same size can offer. The primary cache on the 486 is four-way set associative.
[From: ralf@alum.wpi.edu (Ralph Valentino)]
Here is a quick overview of the various bus architectures available
for the PC and some of the strengths and weaknesses of each. Some
terms are described in more detail at the bottom.
XT bus:
8 data bits, 20 address bits
4.77 MHz
Comments: Obsolete, very similar to ISA bus, many XT cards will
work in ISA slots.
ISA bus: Industry Standard Architecture bus (aka. AT bus)
8/16 data bits, 24 address bits (16Meg addressable)
8-8.33MHz, asynchronous
5.55M/s burst
bus master support
edge triggered TTL interrupts (IRQs) - no sharing
low cost
Comments: ideal for low to mid bandwidth cards, though lack of
IRQs can quickly become annoying.
MCA bus: Micro Channel Architecture bus
16/32 data bit, 32 address bits
80M/s burst, synchronous
full bus master capability
good bus arbitration
auto configurable
IBM proprietary (not ISA/EISA/VLB compatible)
Comments: Since MCA was proprietary, EISA was formed to compete with
it. EISA gained much more acceptance; MCA is all but dead.
EISA bus: Enhanced Industry Standard Architecture bus
32 data bits, 32 address bits
8-8.33MHz, synchronous
32M/s burst (sustained)
full bus master capability
good bus arbitration
auto configurable
sharable IRQs, DMA channels
backward compatible with ISA
some acceptance outside of the PC architecture
high cost
Comments: EISA is great for high bandwidth bus mastering cards
such as SCSI host adaptors, but its high cost limits
its usefulness for other types of cards.
P-EISA: Pragmatic EISA (also Super-ISA)
(see the description of the HiNT chipset elsewhere in this FAQ)
VLB: VESA Local Bus
32 data bits, 32 address bits
25-40MHz, asynchronous
130M/s burst (sustained is closer to 32M/s)
bus master capability
will coexist with ISA/EISA
slot limited to 2 or 3 cards typical
backward compatible with ISA
moderate cost
Comments: VLB is great for video cards, but its lack of a good bus
arbiter limits its usefulness for bus mastering cards and
its moderate cost limits its usefulness for low to mid
bandwidth cards. Since it can coexist with EISA/ISA, a
combination of all three types of cards usually works best.
PCI: Peripheral Component Interconnect local bus
32 data bits (64 bit option), 32 address bits (64 bit option)
up to 33MHz, synchronous (upto 66MHz PCI 2.1 option)
132M/s burst at 33MHz (sustained) (264M/s with 64 bit option)
full bus master capability
good bus arbitration
slot limited to 3 or 4 cards typical
auto configurable
will coexist with ISA/EISA/MCA as well as another PCI bus
strong acceptance outside of the PC architecture
support for 5V and 3.3V peripheral cards
moderate cost
Comments: The newest of the buses, combining the speed of VLB with
the advanced arbitration of EISA. Great for both video
cards and bus mastering SCSI/network cards.
Notes: 64 bit option was defined in the original PCI 2.0 spec. 66MHz
operation is an option of the PCI 2.1 spec and is only
available for the 3.3V PCI bus. PCI 2.1 compliance does NOT imply
66MHz operation.
=Terms=
Auto configurable: Allows software to identify the board's
requirements and resolve any potential resource conflicts
(IRQ/DMA/address/BIOS/etc).
Bus master support: Capable of First Party DMA transfers.
Full bus master capability: Can support any First Party cycle from any
device, including another CPU.
Good bus arbitration: Fair bus access during conflicts, no need to
back off unless another device needs the bus. This prevents CPU
starvation while allowing a single device to use 100% of the available
bandwidth. Other buses let a card hold the bus until it decides to
release it and attempts to prevent starvation by having an active card
voluntarily release the bus periodically ("bus on time") and remain
off the bus for a period of time ("bus off time") to give other
devices, including the CPU, a chance even if they don't want it.
16Meg addressable: This limits first party DMA transfers to the lower
16 Meg of address space. There are various software methods to
overcome this problem when more than 16 Megs of main memory are
available. This has no effect on the ability of the processor to
reach all of main memory.
Backward compatible with ISA: Allows you to place an ISA card in the
slot of a more advanced bus. Note, however, that the ISA card does
not get any benefit from being in an advanced slot, instead, the slot
reverts to an ISA slot. Other slots are unaffected.
No, they will not. MCA, unlike EISA and VLB, is not backward compatible with ISA.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)]
The motherboard "chip set" contains all the logic that's not in
the microprocessor ("uP") and its coprocessor, or the memory.
These functions always include:
* Address decoding and "memory mapping"
* keyboard interface controller (which includes reset generator)
* Direct Memory Access (DMA) channels
* interrupt controller
* bus controller(s)
* battery-powered "real time" clock/calendar circuit
* crystal-controlled clock oscillator(s)
* main memory controller
They almost always include:
* controller for cache external to the uP
* "turbo" switch logic
* programmable "wait state" logic
and some of them include:
* controller(s) for PCMCIA slots
* "green" power-conservation logic
* video display logic for CRT, LCD, or both
* serial ports, parallel ports, floppy, SCSI and/or IDE, etc. controllers
* network interface controllers (for Ethernet)
Some people consider the BIOS ROM part of the "chip set."
Sometimes part of an EISA or VLB bus controller is implemented
in an optional, socketed integrated circuit. A motherboard like that
can be sold with the socket empty, and you have to go back and
buy the "bus mastering option" later when you find out you need it.
"Chip sets" are usually a set of highly integrated, special purpose
integrated circuits. The keyboard interface controller is usually
in a 40-pin dual-inline pin (DIP) package compatible with the Intel
8048 single-chip microcomputer which was used for that function in the
IBMPC-AT. The rest of the logic often fits in a single IC. In the trade,
you may see this single IC referred to as "the chipset," even though
the keyboard interface and other logic is external. The Asian data sheets
often call the high-integration chips "LSIs."
The word "ChipSet" is a trademark of Chips and Technologies
Inc. (San Jose, California), which introduced a 5-chip set of LSIs
for AT-clone motherboards in early 1985. CTI may also own "chipset"
and "Chipset"; I don't know.
CTI was very successful at promoting the term "ChipSet," but less
successful at associating it in the public mind with their particular
brand. People use the word to refer to any high integration chip
used in PCs. For example, you'll hear people talk about the "ET4000
video chipset." The ET4000 is a single chip which integrates most
of an SVGA controller. The word "ASIC" (application-specific integrated
circuit) would be more appropriate.
Single, high-integration ICs are not very good at driving heavily
loaded signals, like the ones in the memory array and the expansion
slots. Better motherboards use buffer chips external to the LSI
for this electrical function. It may not show up in "WinMark"
comparisons, but it shows in electrical compatibility. Well-buffered
motherboards are less likely to require SIMM "cherry-picking,"
and are more likely to work at high ambient temperatures.
The 74F245, which costs about 15 cents in high volume, is often used for
this electrical buffering.
[From: burnesa@cat.com (Shaun Burnet)]
AMI BIOS Del key during the POST
Award BIOS Ctrl-Alt-Esc
DTK BIOS Esc key during the POST
IBM PS/2 BIOS Ctrl-Alt-Ins after Ctrl-Alt-Del
Phoenix BIOS Ctrl-Alt-Esc or Ctrl-Alt-S
[From: mike@pencom.com (Mike Heath)]
Some 286 machines don't have a CMOS configuration menu in the BIOS.
They require a software CMOS setup program. If you don't have the
Installation and/or Diagnostics diskette for your machine, you can
try using a shareware/freeware program. Try looking in:
oak.oakland.edu:/SimTel/msdos/at
or
ftp.uu.net:/systems/msdos/simtel/at
Bus mastering is the ability of an expansion (ISA/EISA/VLB/MCA/etc) card to directly read and write to main memory. This allows the CPU do delegate I/O work out to the cards, freeing it to do other things. For all of the above busses, bus mastering capability is assumed. Unless specifically stated otherwise (labeled "SLAVE" for instance), you should assume each slot has this capability. For cards, this is not assumed. If you want a bus mastering card, you should specifically request it and expect to pay more. Note that some cards (RLL/MFM/IDE/com) are not available in bus mastering versions. A bus mastering card will only work in a slot that supports bus mastering. If placed in a non-bus mastering slot, it will fail immediately. A non-bus mastering card will work identically in either type of slot.
Yes, you can put ISA cards in both EISA slots and VLB slots, as both buses were specifically designed to be 100% ISA compatible. ISA cards will not directly effect the performance of EISA/VLB cards; a well balanced system will have both. Note, however, that the total bandwidth of the bus will be split between all cards, so there is a strong advantage to using EISA/VLB cards for the high bandwidth devices (disk/video).
Only EISA cards matter in the ECU; ISA and VLB entries are only place markers. While this is a good way to keep track of IRQ, DMA and BIOS conflictions, ISA and VLB need not be placed in the configuration at all, nor should it be assumed that the settings for them match the actual card settings. If you wish to add them, you can use the "Generic ISA Card" configuration file for either. Do not expect card vendors to supply them.
Many EISA cards support both Standard (ISA) and Enhanced (EISA) modes. In Standard mode, the card will appear to be an ISA card to the OS; it will generate edge triggered interrupts and only accept ISA addressing (for bus mastering cards), for instance. An important thing to note is that the card may still do EISA specific things like 32-bit data bus mastering and EISA configuration setup as this functionality is hidden from the OS.
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)] Sure. Even inferior operating systems can use it for something. The question is how much performance it buys. In ISA, the DMA channels and bus-mastering IO cards can only address the first 16 MB. Therefore the device drivers have to copy data up and down or just not use the space. I am told the Linux SCSI drivers know how to do this. I don't know about OS/2 or MSWindows.
[From: ralf@alum.wpi.edu (Ralph Valentino)] The HiNT Caesar Chip Set (CS8001 & CS8002) can come in three different configurations. All three of these configurations have EISA style connectors and are (sometimes incorrectly) sold as EISA motherboards. The differences should be carefully noted, though. The rarest of these configuration uses a combination of the first HiNT chip (CS8001) and the Intel chip set. This configuration can support the full EISA functionality: 32 address bits, 32 data bits, level sensitive (sharable) interrupts, full EISA DMA, watch dog (sanity) timer, and so forth. The second configuration is called Super-ISA, which uses both of the HiNT chips. This configuration is very common in low-end models. It supports a very limited functionality: 24 address bits, 32 data bits, edge triggered (non-sharable) interrupts, ISA (16 data, 24 address) DMA, and no watch dog timer. Some EISA boards, such as the Adaptec 1742A EISA Fast SCSI-2 host adapter, can be configured to work in this mode by hacking their EISA configuration file (.CFG) to turn off these features. Other EISA cards require these features and are therefore unusable in these systems. The final configuration is called Pragmatic EISA, or P-EISA. Like Super-ISA, both HiNT chips are used but external support logic (buffers and such) are added to provide a somewhat increased functionality: 32 address bits, 32 data bits, edge triggered (non-sharable) interrupts, ISA (16 data, 24 address) DMA, and no watch dog timer. The full 32 bits for address and data allow bus mastering devices access to the complete range of main memory. As with Super-ISA, there may be incompatibilities with some EISA cards.
[From: rbean@execpc.com (Ron Bean)] Well, you're not alone-- expensive workstations come with inaccurate clocks too! Usually they just run at the wrong speed, which means you can compensate with software that measures the drift rate and applies a correction factor. In the long run, this can be *very* accurate. Other programs can periodically set your clock to match another one that's known to be accurate (see the question on setting your clock). If your clock is more erratic (eg, it stops when the machine is turned off, or the date gets scrambled), try replacing the battery (remember to write down your CMOS settings first!). The CMOS RAM takes considerably less power than the clock, so it may keep working even though the battery is too weak to run the clock (see the question on replacing the battery for details). The interrupt-based "DOS time" can also be affected by programs that disable interrupts for too long, so if you don't reboot your machine for a couple of days (or do something else that resets the system time to match the CMOS clock) you may find that it's drifted also. Several programs are available to keep your clock on time. For a free DOS-based program, look for a file called adclk100.zip. Some shareware programs for Windows are listed at http://www.eecis.udel.edu/~ntp/ along with a lot of other time-related stuff. For Linux start with 'man 8 clock', and also check out the xntpd package at the URL above (but don't use the correction factor in /etc/adjtime if you're running xntpd, they'll just confuse each other). If you're running more than one OS on the same machine (such as Windows & Linux) you should only let one of them reset the CMOS clock. A typical cheap quartz watch is rated at +/- 15 sec per month (3 minutes per year) which is about 5.7 ppm (parts per million), and in practice they are often much more accurate than that. Dallas Semiconductor rates their encapsulated clock modules for +/- 1 min per month, or 22.8 ppm. Many motherboards are off by 100 ppm. Clocks with external crystals can be "fine-tuned" with a trimmer capacitor, although I've never heard of anyone actually doing this on a motherboard. The crystal's frequency will change slightly over time as the crystal "ages", and can also be affected by temperature changes. The original IBM AT used the Motorola MC146818, which is a real-time clock plus 50 bytes of CMOS RAM. This chip is discussed in the book "The Undocumented PC", from Addison-Welsey. The Dallas Semiconductor DS1285 is a drop-in replacement for the MC146818, and the DS1287 is the same chip encapsulated with its own battery and clock crystal. Other variants include larger amounts of CMOS RAM.
[From: rbean@execpc.com (Ron Bean)]
There are several ways to do this. A good place to start is
http://www.eecis.udel.edu/~ntp/ which includes a lot of interesting
time-related stuff, including ways to set your clock from time servers on
the internet, or from dial-up modem services (long distance rates apply).
If you just want an accurate voice announcement, you can hear WWV by
dialing (303)499-7111.
Several countries broadcast time signals by shortwave radio. Most radio
clocks that will connect to a serial port cost $3-4000, but you can get
plans for an inexpensive "gadget box" (actually a 300 baud modem) that
sits between your computer and any shortwave radio tuned to Canada's CHU
on 3.33, 7.335, or 14.670 MHz (ftp://ftp.udel.edu/pub/ntp/gadget.tar.Z).
If you're running some version of unix or NT, the xntpd package includes
drivers for most radio clocks.
GPS signals also include time information, and some GPS receivers have
a data connector. This could become the low-cost solution in the near
future, as cheaper GPS receivers become available.
In Germany, the Physikalisch-Technische Bundesanstalt (PTB) broadcasts
a coded time signal on 77.5 kHz from a transmitter near Frankfurt, and
inexpensive receivers are available that can plug into a serial port. In
the US, NIST runs a similar station (WWVB) on 60 kHz, but the data is
encoded differently and receivers are expensive and hard to find.
You may have heard about Heathkit's "Most Accurate Clock", which
decodes the time signal from WWV and has a serial port. Heath no longer
sells kits, but they still sell the factory-built version of the clock
(cost is in the $4-500 range). Their address is P.O. Box 1288, Benton
Harbor, MI 49023.
NIST publishes a 30-page booklet (NIST Special Publication 432) that
explains all of their time services in detail, including WWV, WWVB, and
the GOES satellite service. It can be obtained from the Government
Printing Office or directly from:
NIST/Radio Station WWV
2000 East County Road 58
Fort Collins, CO 80524-9499
Of course, many people don't care what time it is anyway. But if your
machine is on a network it can sometimes cause problems if it's system
time doesn't match it's neighbors.
[From: rbean@execpc.com (Ron Bean)] The battery maintains power to the CMOS RAM and the real-time clock when your PC is turned off. You may have a small lithium "coin" battery soldered to the motherboard, or a larger external one plugged into a connector. Some motherboards have a jumper to select either type, and a few have a NiCd battery that recharges automatically, or a lithium battery encapsulated in the clock chip. NOTE: Always write down your CMOS settings before you mess with the battery! In fact, you should write them down now anyway, in case the battery fails later. The batteries that are soldered in or encapsulated with the clock chip are supposed to last 10 years or more, but your mileage may vary. Some people find that the external type has to be replaced every couple of years. Self-recharging NiCds that get power from a disk drive cable are available as aftermarket items. A few people have tried to save money by substituting 4 alkaline AA batteries for the expensive external lithium battery, but they have to be replaced more often. If you need to replace a soldered-in battery, have a repair shop install a socket (you shouldn't attempt this yourself, unless you're experienced at soldering on expensive multi-layer circuit boards). If the battery is encapsulated in the chip, there is no way to replace it without replacing the chip-- again, consult a repair shop if it's not socketed. These chips can be "turned off" via software to extend battery life during storage, and are shipped from the factory that way.
IRQ2 is used to cascade the second programmable interrupt controller (PIC) on AT machines. The IRQ2 line on the old XT bus has been renamed to IRQ9. This has one and only one side effect: from a software point of view, IRQ2 = IRQ9. You can freely use IRQ2 on any hardware device, provided you are not already using IRQ9. Your associated software driver can be set to IRQ2 or IRQ9, which ever it happens to prefer. Note that many video cards have an IRQ2 enable jumper for very, very old backward compatibility reasons; you should disable this before attempting to use the IRQ for something else. There are no unexpected side effects.
[From: wlim@lehman.com (Willie Lim)]
[From: r.j.mersel@is.twi.tudelft.nl (Rob Mersel)]
(Note that DRQ is the DMA Channel)
Default IRQ/DRQ settings AT systems:
IRQ IO BASE DRQ Card or Device
ADDRESS
(HEX)
=== ======= === ================
* * 0 unassigned (? bit DMA)
* * 1 unassigned (8 bit DMA)
* * 3 unassigned (8 bit DMA)
* * 5 unassigned (16 bit DMA)
* * 6 unassigned (16 bit DMA)
* * 7 unassigned (16 bit DMA)
0 * * timer (reserved)
1 * * keyboard (reserved)
2 * * interrupt 8-15 (cascade) (see Q 2.40)
3 2E8-2EF * COM4:
3 2F8-2FF * COM2:
4 3E8-3EF * COM3:
4 3F8-3FF * COM1:
5 278-27F * LPT2:
6 3F0-3F7 2 Floppy drive controller
7 378-37F * LPT1: (PRN:)
8 * * real-time clock (reserved)
9 * * unassigned (see Q 2.40)
10 * * unassigned
11 * * unassigned
12 * * unassigned
13 * * math co-processor
14 1F0-1F7 * Hard drive controller (drive 0)
14 3F6-3F7 * Hard drive controller (drive 1)
15 170-177 * Secondary hard drive controller (drive 2)
15 376-377 * Secondary hard drive controller (drive 3)
Adapter card IRQ/DRQ settings:
IRQ IO BASE DRQ Card or Device
ADDRESS
(HEX)
=== ======= === ================
* 200-207 * Game port
2 330 * MPU-401 Emulation (PAS 16)
3 300 * 3Com Etherlink II, II/TP, II/16, II/16TP, 16/16TP
3 300 * Novell NE2000
3 300 * SMC/Western Digital 8003EP, 8013EWC, 8013WB
5 368 * Ungermann-Bass Ethernet NIUpc (long), NIUpc/EOTP (short)
5 ??? * DEC etherWORKS LC, Turbo, Turbo/TP
5 220 1 Sound Blaster Emulation (PAS 16)
5 220-22F 1 Sound Blaster 2.0 (default)
* 338-339 * Sound Blaster 2.0 FM music chip
5 A20 5 Proteon P1390
7 * 3 Pro Audio Spectrum 16 (PAS 16)
9 300 5 Boca Ethernet BEN100, BEN102, BEN300
Default IRQ/DRQ settings XT systems:
IRQ IO BASE DRQ Card or Device
ADDRESS
(HEX)
=== ======= === ===============
* * 0 DRAM-refresh (used on motherboard only?)
* * 1 unassigned
0 * * timer (reserved)
1 * * keyboard (reserved)
2 * * unassigned
3 2E8-2EF * COM4:
3 2F8-2FF * COM2:
4 3E8-3EF * COM3:
4 3F8-3FF * COM1:
5 ? 3 Hard drive controller
6 3F0-3F7 2 Floppy drive controller
7 378-37F * LPT1: (PRN:)
===============
Ralph Valentino (ralf@worcester.com) (ralf@alum.wpi.edu)
Senior Design Engineer, Instrinsix Corp.
Last Update July 04 1997 @ 02:51 AM