Advanced Chipset Setup

Remember…

Configurations may vary according to your system, BIOS version and brand. So, some settings may be present on your computer, some may not or have a different name. Be sure of what you are doing! If you find a configuration having a different name, please let us know.

• Refresh
• Data Bus
• Cacheing
• Memory

• Automatic Configuration: Allows the BIOS to set automatically several important settings (e.g. Clock divider, wait states, etc.). Very useful for newbies. Disabled recommended if you want to play around with the settings. If you have some special adapter cards, you will also have to disable this option.
• Keyboard Reset Control: Enable Ctrl-Alt-Del warm reboot. Enabled recommended for more control over your system.

Refresh

• Hidden Refresh: Allows the RAM refresh memory cycles to take place in memory banks not used by your CPU at this time, instead or together with the normal refresh cycles, which are executed every time a certain interrupt (DRQ0 every 15 ms) is called by a certain timer (OUT1). Every time it takes 2 to 4 ms for the refresh. One refresh cycle every ~16 us refreshes 256 rows in ~ 4ms. Each refresh cycle only takes the equivalent of one memory read or less, as CAS (Column Address Strobe) is not needed for a refresh cycle. Some RAM can do it, some not. Try. If the computer fails, turn it off. Enabled recommended. There are typically 3 types of refresh schemes: cycle steal, cycle stretch, or hidden refresh. Cycle steal actually steals a clock cycle from the CPU to do the refresh. Cycle stretch actually delays a cycle from the processor to do the refresh. Since it only occurs every say 4ms or so, it's an improvement from cycle steal. We're not really stealing a cycle, only stretching one. Hidden refresh typically doesn't stretch or steal anything. It's usually tied to DTACK (Data acknowledge) or ALE (Address Latch Enable) or some other signal relating to memory access. Since memory is accessed ALL of the time it is easy to synchronize the refresh on the falling edge of this event. Of course, the system performance is at its optimum efficiency, refresh wise since we're not taking clock cycles away from the CPU.
• Slow Refresh: Causes RAM refresh to happen less often than usual, around four times. This increases the performance slightly due to the reduced contention between the CPU and refresh circuitry, but not all DRAM memories necessarily support these reduced refresh rates (in which case you will get parity errors and crashes). It also saves power, a good opportunity for laptop computers. Enabled recommended
• Concurrent Refresh: Both the processor and the refresh hardware have access to the memory at the same time. If you switch this off, the processor has to wait until the refresh hardware has finished (it's a lot slower). Enabled recommended.
• Burst Refresh: Performs several refresh cycles at once. Increase the system performance.
• DRAM Burst at 4 Refresh: Refresh is occurring at Bursts of four, increasing the system performance.
• Hi-speed Refresh: Refreshes are occurring at an higher frequency, which is improving the system performance. Of course, not all types of memory can support it and Slow Refresh is preferred.
• Staggered Refresh: Refresh is performed on memory banks sequentially. The advantages are related to less power consumption and less interference between memory banks.
• Slow Memory Refresh Divider: The AT refresh cycle occurs normally every 16 ns, straining the CPU. If you can select an higher value, such as 64 ns, you will increase the performance of your system.
• Decoupled Refresh Option: Enables the ISA bus and the RAM to refresh separately. Because refreshing the ISA bus is more slow, this causes less strain on the CPU.
• Refresh Value: The lower this value is, the best the performance.
• Refresh RAS Active Time: The amount of active time needed for Row Address Strobe during refresh. The lower the better.

Data Bus

• Single ALE Enable: Address Latch Enable (ALE) is an ISA Bus Signal (Pin B28) that indicates that a valid address is posted on the bus. The bus is used to communicate with 8 and 16 bit peripheral cards. Some chipsets have the capability to support an enhanced mode in which multiple ALE assertions may be made during a single Bus Cycle. Single ALE Enable apparently enables or disables that capability. May slow the video bus speed if enabled. Disabled (No) recommended.
• AT BUS Clock Selection (or AT Bus Clock Source): Gives a division of the CPU clock (or System Clock) so it can reach the ISA - EISA bus clock. An improper setting may cause significant decrease in performance. The settings are in terms of CLK/x, (or CLKIN/x and CLK2/x) where x may have values like 2, 3, 4, 5, etc. CLK represents your processor speed, with the exception that clock-multiple processors need to use the EXTERNAL clock rate, so a 486DX33, 486DX2/66, and 486DX3/99 all count as 33 and should have a divider value of 4. For 286 and 386 processors, CLK is half the speed of the CPU. You should try to reach 8.33 Mhz (that's the old bus clock of IBM AT; there may be cards which could do higher, but it's not highly recommended). On some motherboards, the AT bus speed is 7.15 Mhz. On new BIOS versions, there is an AUTO setting that will look at the clock frequency and determine the proper divider. Here are some appropriate settings:

Selecting the right clock divider. You can try other clock settings to increase performance. If you choose a too small divider (CLK/2 for a DX33) your system may hang. For a too big divider (CLK/5 for a DX33) the performance of ISA cards will decrease. This setting is for data exchange with ISA cards, NOT VL bus and PCI cards which run at CPU bus clock speeds: 25Mhz, 33Mhz and higher. If your ISA cards are fast enough to keep up, it is possible to run the bus at 12 Mhz. Note that if you switch crystals to overclock your CPU, you are also overclocking the ISA bus unless you change settings to compensate. Just because you can overclock the CPU doesn't mean you can get away with overclocking the ISA bus. It might just be one card that causes trouble, but one is enough. It might cause trouble even if you aren't using it by responding when it shouldn't.

• ISA Bus Speed: As above, but related to PCI.
• Bus Mode: It can be set in synchronous and asynchronous modes. In synchronous mode, the CPU clock is used, while in asynchronous mode the ATCLK is used.
• AT Cycle Wait State: Whenever an operation is performed with the AT bus, it indicates the number of wait states inserted. You may need some wait states if old ISA cards are used, notably if they are in operation with fast adapter cards.
• 16-bit Memory, I/O Wait State: The number of wait states before 16-bit memory and I/O operations.
• 8-bit Memory, I/O Wait State: As above, except this setting is for 8-bit operations.
• 16-bit I/O Recovery Time: The additional delay time inserted after every 16-bit operations. This value is added to the minimum delay inserted after every AT cycles.
• Fast AT Cycle: If enabled, may speed up transfer rates with ISA cards, notably video.
• ISA IRQ: Inform the PCI cards of the IRQs used by ISA cards, so they be discarded.
• DMA Wait States: The number of wait states inserted before direct memory access (DMA). The lower the better.
• DMA Clock Source: The source of the DMA clock for which some peripheral controllers, like floppy, tape, network and SCSI adapters use to address memory, which is 5 MHz maximum.
• E0000 ROM belongs to ATBUS: Tells if the E0000 area (upper memory) belongs to the MB DRAM or to the AT bus. Yes recommended.
• Memory Remapping: Remaps the memory used by the BIOS (A0000 to FFFF - 384 k) above the 1 Mb limit. If enabled you cannot shadow Video and System BIOS. Disabled recommended.
• Fast Decode Enable: Enabled recommended. Refers to some hardware that monitors the commands sent to the keyboard controller chip. The original AT used special codes not processed by the keyboard itself to control the switching of the 286 processor back from protected mode to real mode. The 286 had no hardware to do this, so they actually have to reset the CPU to switch back. This was not a speedy operation in the original AT, since IBM never expected that an OS might need to jump back and forth between real and protected modes. Clone makers added a few PLD chips to monitor the commands sent to the keyboard controller chip, and when the "reset CPU" code was seen, the PLD chips did an immediate reset, rather than waiting for the keyboard controller chip to poll its input, recognize the reset code, and then shut down the CPU for a short period. This "fast decode" of the keyboard reset command allowed OS/2 and Windows to switch between real and protected mode faster, and gave much better performance. (early 286 clones with Phoenix 286 BIOS had this setting to enable/disable the fast decode logic.) On 386 and newer processors, the fast decode is probably not used, since these CPUs have hardware instructions for switching between modes. There is another possible definition of the "Fast Decode Enable" command. The design of the original AT bus made it very difficult to mix 8-bit and 16-bit RAM or ROM within the same 128K block of high address space. Thus, an 8-bit BIOS ROM on a VGA card forced all other peripherals using the C000-Dfff range to also use 8 bits. By doing an "early decode" of the high address lines along with the 8/16 bit select flag, the I/O bus could then use mixed 8 and 16 bit peripherals. It is possible that on later systems, this BIOS flag controls the "fast decode" on these address lines.
• Extended I/O Decode: The normal range of I/O addresses is 0-0x3ff; 10 bits of I/O address space. Extended I/O-decode enables wider I/O-address bus. The CPU support a 64K I/O space, 16 address lines. Most motherboards or I/O adapters can be decoded only by 10 address bits.
• I/O Recovery Time: I/O recovery time is the number of wait states to be inserted between two consecutive I/O operations. It is generally specified as a two number pair -- e.g. 5/3. The first number is the number of wait states to insert on an 8 bit operation, the second the number of waits on a 16 bit operation. A few BIOSes specify an I/O Setup time (AT Bus (I/O) Command Delay). It is specified similarly to IO Recovery Time, but is a delay before STARTING an I/O operation rather than a delay BETWEEN I/O operations. 5/3 has been recommended as a value which will often yield a good combination of performance and reliability. When enabled, more I/O wait states are inserted. A transfer from IDE hard drive to memory happens without any handshaking, meaning the data has to be present (in the cache of the hard disk) when the CPU wants to read them from an I/O Port. This is called PIO (Programmed I/O) and works with a REP INSW assembler instruction. Now I/O Recovery Time enabled adds some wait states to this instruction. When disabled, the hard drive is a lot faster. Note that there is a connection between I/O Recovery Time and AT BUS Clock Selection. For example, if the AT BUS Clock is set to 8 MHz and you have a normal hard disk, I/O Recovery Time can be turned off, resulting in a higher transfer rate from hard disk.
• IDE Multi Block Mode: Enable IDE drives to transfer several sectors per interrupt. According to the hard drive cache size, six modes are possible. Mode 0 (standard mode transferring a single sector at a time), Mode 1 (no interrupts), Mode 2 (Sectors are transferred in a single burst), Mode 3 (32-bit instructions with speeds up to 11.1 Mb/sec.In BIOSes usually abbreviated as "32-bit mode". Not to be confused with 32-bit protected modeinstructions(!) or Windows' 32-bit disk access.), Mode 4 (up to 16,7 Mb/sec.) and Mode 5 (up to 20 Mb/sec.). The so-called "PIO mode 5" is completely bogus. It was launched by some controller manufacturers but was never accepted, never absorbed into the standards and you will not find any disk drives supporting it. Nor will you find any such drives in the future. The relevant parameter for block mode is the number of sectors per interrupt. The maximum number of sectors per interrupt is often (but not always) related to the drive's buffer size. If this setting is not set properly, communication with COM ports may not work properly. If the block size (sectors/interrupt) is set to too large a value, you may experience serial port overruns and CRC errors. To fix this, decrease the block size (preferred) or disable block mode altogether.For more info, please have a look at The EIDE FAQ-ATA harddisks.
• IDE DMA Transfer Mode: Settings are Disabled, Type B (for EISA) and Standard (for PCI). Standard is the fastest but may cause problems with IDE CD ROMs. The standard type is type F. Note that both are so-called "third party DMA" and should not be confused with first-party (busmastering) DMA offered by many modern boards.
• IDE Multiple Sector Mode: When IDE DMA Transfer Mode is enabled, this sets the number of sectors per burst, with a maximum of 64. Problems may occur with COM ports.
• IDE Block Mode: Enables multi-sectors transfers. Also known as IDE HDD Block Mode.

Warning. This setting is known to cause crashes in Win95. Disabled recommended. Extremely annoying.

• IDE 32-bit Transfer: When enabled, the read / write rate of the hard disk is faster. When disabled only 16-bit data transfers is possible. The read/write rate of the harddisk stays the same, but the transfers over the host bus are maybe faster. So, don't expect anything really dramatic. Actually, you should ordinarily expect no difference at all, since even with 16-bit transfers, the local bus is fast enough to accomodate just about any disk drive. However, some interface hardware uses faster timing on the ATA (IDE) bus when 32-bit transfers are used. In those cases you may notice a speedup. Note that ATA (IDE) is a 16-bit bus. The 32-bit transfers referred to here are strictly the transfers between CPU and interface chip. 
• Extended DMA Registers: Within a AT, DMA occurs for 16 Mb. When enabled, DMA covers the whole 4 Gb of a 32-bit processor.

Cacheing

• Cache Read Option: Often referred as SRAM Read wait state or Cache Read Hit Burst (SRAM: Static Random Access Memory). A specification of the number of clocks needed to load four 32-bit words into a CPU internal cache. Typically specified as clocks per word. 2-1-1-1 indicates 5 clocks to load the four words and is the theoretical minimum for current high end CPUs (486DX, 486SX, 486DX2, 486DX4, Pentium). Conceptually, the m-n-n-n notation is narrowly limited to CPUs supporting burst mode and with caches organized as 4 word "lines". However it would not be a surprise to see it extended to other CPU architectures. It takes simple integer values, such as 2-1-1-1, 3-1-1-1 or 3-2-2-2. This determines the number of wait states for the cache RAM in normal and burst transfers (the latter for 486 only). The lower you computer can support, the better. 4-1-1-1 is usually recommended.
• Cache Write Option: Same thing as memory wait states, but according to cache ram.
• Fast Cache Read/Write: Enable if you have two banks of cache, 64K or 256K.
• Cache Wait State: Like conventional memory, the lower wait states for your cache, the better. 0 will give the optimal performance, but 1 wait state may be required for bus speed higher than 33 MHz.
• Tag Ram Includes Dirty: Enabling will cause an increase in performance, because the cache is not replaced during cycles, simply written over. It will usually cut the maximum cachable range in half, as one bit is taken off the address tag in order to be used as a dirty tag bit. So, if you have a lot of memory, you might be better off without dirty tag bit.
• Non-Cacheable Block-1 Size: Disabled. The Non-Cacheable region is intended for a memory-mapped I/O device that isn't supposed to be cached. For example, some video cards can present all video memory at 15 Mb - 16 Mb so software doesn't have to bank-switch. If the non-cacheable region covers actual RAM memory you are using, expect a significant performance decrease for accesses to that area. If the non-cacheable region covers only non-existent memory addresses, don't worry about it. If you don't want to cache some memory you can exclude 2 regions of memory. There are good reasons not to cache some memory areas. For example, if the memory area corresponds to some kind of buffer memory on a card so that the card may alter the contents of this buffer without warning the cache to invalidate the corresponding cache lines. Some BIOSes take more options than enabled /disabled, namely Nonlocal /Noncache /Disabled (VLB only?).
• Non-Cacheable Block-1 Base: 0KB. Enter the base address of the area you don't want to cache. It must be a multiple of the Non-Cacheable Block-1 Size selected.
• Non-Cacheable Block-2 Size: Disabled.
• Non-Cacheable Block-2 Base: 0KB.
• Cacheable RAM Address Range: Usually chipsets allow memory to be cached just up to 16 or 32 MB. This is to limit the number of bits of a memory address that need to be saved in the cache together with its contents. If you only have 4MB of RAM, select 4MB here. The lower the better, don't enter 16MB if you only have 8MB installed!
• Video BIOS Area Cacheable: To cache or not to cache video BIOS, a good question. You should try what is better - video access is faster with 'enabled', but cache has its size. With an "accelerated" video card it may be necessary to make the video RAM region non-cacheable so the CPU can see any changes the drawing engine makes in the frame buffer.

Memory

• Memory Read Wait State: (often referred as DRAM Wait States) Each wait states adds 30 ns of RAM access speed. The CPU is often much faster than the memory access time. On a 486, 1 or more wait states are often required for RAM with 80ns or higher access time. And, depending on the processor and motherboard, also for lower than 80ns access time. The less wait states, the better. Consult your manual. If wait states are too low, a parity error will occur. For 386 or 486 non-burst memory access cycle takes 2 clock ticks. A rough indication of RAM speed necessary for 0 wait states is 2000/Clock[MHz] - 10 [ns]. For a 33Mhz processor, this would give 50ns of access time required, so if you do not have 50ns memories, wait state is required. The number of wait states necessary is approximately (RamSpeed[ns] +10) * Clock[MHz] /1000 - 2. For 70ns RAM and a 33Mhz processor (very standard configuration), this would give roughly 1 wait state. But this really is dependent on chipset, motherboard and cache design, CPU type and whether we talk about reads or writes. Take these formulas with a large grain of salt. You can find out the access time of your RAM chips by looking at their product numbers. Mostly at the end there is a 70, 80, 90, or even 60. If 10 stands there, it means 100 ns. Some RAM chips also have an explicitly written speed in ns. The RAM you buy these days mostly have 70ns or 60ns.
• Memory Write Wait State: Same as above except for writting (self evident).

In some BIOSes, these two options are combined as DRAM Wait State. In that case, the number of read and write wait states is necessarily equal.

• DRAM CAS Timing Delay: The default is no CAS delay. DRAM is organized by rows and columns and accessed through strobes. Then a memory read/write is performed, the CPU activates RAS (Row Access Strobe) to find the row containing the required data. Afterwards, a CAS (Column Access Strobe) specifies the column. RAS and CAS are used to identify a location in a DRAM chip. RAS access is the speed of the chip while CAS is half the speed. When you have slow DRAM, you should use 1 state delay.
• DRAM Refresh Method: Selects the timing pulse width of RAS from RAS Only or CAS before RAS (which one is better?).
• RAS Precharge Time: Technically, this is the duration of the time interval during which the Row Address Strobe signal to a DRAM is held low during normal Read and Write Cycles. This is the minimum interval between completing one read or write and starting another from the same (non-page mode) DRAM. Techniques such as memory interleaving, or use of Page Mode DRAM are often used to avoid this delay. Some chipsets require this parameter in order to set up the memory configuration properly. The RAS Precharge value is typically about the same as the RAM Access (data read/write) time. The latter can be used as an estimate if the actual value is unavailable. At least one BIOS describes the precharge and access times as RAS LOW and RAS HIGH Times. For a 33 MHz CPU, 4 is a good choice, while lower values should be selected for slower speeds.
• RAS Active Time: The amount of time a RAS can be kept open for multiple accesses. High figures will improve performance.
• RAS to CAS Delay Time: Amount of time a CAS is performed after a RAS. The lower the better, but some DRAM will not support low figures.
• CAS Before RAS: Reduces refresh cycles and power consumption.
• CAS Width in Read Cycle: The number of wait states for the CPU to read DRAM. The lower the better.
• Interleave Mode: Controls how the CPU access different DRAM banks.
• Fast Page Mode DRAM: This speeds up memory access for DRAM capable of handling it (most do). When access occurs in the same memory area, RAS and CAS are not necessary.