A technique which attempts to minimise the time a processor spends waiting for instructions to be fetched from memory. Instructions following the one currently being executed are loaded into a prefetch queue when the processors extenal bus is otherwise idle. If the processor executes a branch instruction or receives an interrupt then the queue must be flushed and reloaded from the new address.
Instruction prefetch is often combined with pipelining.
The latest versions of the Motorola 680x0 and Intel 80x86 use pre-fetching.
[Which versions? Other processors? Relation to pipelining?]
(16 Feb 1995)