Copyright: SIMetrix Copyright © 2001 Newbury Technology Ltd.


.GRAPH

Simulator control reference

.graph signal_name|"expression"
[ persistence = persistence ]
[ axisname = axisname ]
[ graphname = graphname ]
[ axistype = digital|grid|axis|auto ]
[ curvelabel = curvelabel ]
[ xlabel = xlabel ]
[ ylabel = ylabel ]
[ xunit = xunit ]
[ yunit = yunit ]
[ xmin = xmin ]
[ ymin = ymin ]
[ xmax = xmax ]
[ ymax = ymax ]
[ analysis = analyses_list ]
[ ylog = lin|log|auto ]
[ xlog = lin|log|auto ]
[ nowarn = true|false ]
[ initXLims = true|false]
[ complete = true|false ]

.GRAPH instructs Easy-SPICE to plot a graph of the specified signal or expression. The graph can be plotted incrementally as the simulation proceeds or may be delayed until  the run is complete.

Parameter name	Type	Description
signal_name | expression	string	Specifies item to be plotted. If this is an expression, then it must be enclosed in double quotation marks not curly braces. Note that if plotting an expression or a signal representing a subcircuit current, it is recommended that COMPLETE (see below) is also set to true so that the plot is not created until the run is complete. Incremental plotting of expressions is supported but it is inefficient and may slow down the simulation especially for long runs on small circuits.
persistence	integer	Number of curves to be displayed at once. On repeated runs, any curves from earlier runs remain until the number of curves exceeds this value at which point the oldest is deleted automatically. If this parameter is absent or zero, the curves are never deleted.
graphname	string	If specified, the curves will be directed to their own graph sheet within the current window. The value of graphname is arbitrary and is used to identify the graph so that multiple .graph controls can specify the same one. It works in a similar way to axisname an example of which is given below. This name is not used as a label for display purposes but simply as a means of identification.
axistype	string	Can be one of four values to specify type of y-axis:  DIGITAL. Use a digital axis. This is a small axis that carries only one curve. It is intended for digital signals but may also carry analog curves. GRID. Use a separate grid stacked on top of the main one. The AXISNAME parameter may be used to identify a particular grid used by another .GRAPH control. AXIS. Use a separate y-axis alongside the main one. The AXISNAME parameter may be used to identify a particular axis used by another .GRAPH control. AUTO. This is the default value. A suitable axis is chosen automatically.
axisname	string	This is only used if AXISTYPE is specified. The value of AXISNAME is arbitrary and is used to identify the axis so that multiple .graph controls can specify the same one. An example of this is given below. This name is not used as a label for display purposes but simply as a means of identification. Axes can be labelled using ylabel and xlabel.
curvelabel	string	Label for curve displayed in graph legend. If omitted, the label will be the signal name or expression.
xlabel	string	Label for x-axis. Default is reference of curve being plotted (E.g. time, frequency etc.)
ylabel	string	Label for y-axis. If there is only a single curve, this will default to the label for the curve otherwise the default is blank.
xunit	string	Units for x-axis. Default is units of reference.
yunit	string	Units for y-axis. Default is units of curves plotted provided they are all the same. If any conflict, the default will be blank
xmin	real	Minimum limit for x-axis. This must be specified in conjunction with ymin
ymin	real	Minimum limit for y-axis. This must be specified in conjunction with xmin
xmax	real	Maximum limit for x-axis. This must be specified in conjunction with ymax
ymax	real	Maximum limit for y-axis. This must be specified in conjunction with xmax
analysis	string	Specifies for what analysis modes the plot should be enabled. By default it will be enabled for all analysis modes. Any combination of the following strings, separated by a pipe ('|') symbol.  TRAN. Transient analysis AC. AC analysis DC. DC sweep analysis NOISE. Noise analysis Other analysis modes do not produce plottable results
xlog		One of three values LIN Use linear axis LOG Use log axis AUTO Axis will be log if x values are log spaced. (E.g for decade AC sweep) and all values are positive. Default if omitted: AUTO
ylog	string	One of three values LIN Use linear axis LOG Use log axis AUTO Axis will be log if x values are log spaced. (E.g for decade AC sweep) and all values are positive. Default if omitted: LIN
nowarn	boolean	If true, no warnings are given if an attempt is made to plot a non-existent signal. Default: false.
initXLims	boolean	When this is TRUE (the default), the x-axis limits are initialised according to the analysis. E.g. if the analysis is transient and runs from 0 to 1mS, the x-axis will start with these limits. If set to FALSE, the x-axis limits are calculated to fit the curve and updated incrementally. You should set this to FALSE if you are plotting an expression whose x values are not the same as the x values for the analysis e.g. using the XY() function for an X-Y plot.
complete	boolean	If true, the plot is not produced until the analysis is completed. Otherwise the plot is updated at a rate determined by the global option ProbeUpdatePeriod. This can be set using the options dialog box (File|Options|General...). Default: false.

.GRAPH supersedes the older and less flexible .TRACE. The latter is, however, still supported and may sometimes be convenient for specifying multiple signals on one line.

Using multiple .GRAPH controls

If specifying several .GRAPH controls to plot a number of curves on the same graph, you should make sure that the various parameters are consistent. If for example, a conflict arises if you specify xmin and xmax for two .GRAPH's that plot curves in the same graph sheet, and the values for xmin and xmax are different for each. You can specify xmin and ymin for just one of the .GRAPH controls or you can specify for all and make sure they are all the same. The same applies to other non-boolean parameters i.e. ymin, ymax, xlabel, ylabel, xunits and yunits. The parameter initXLims, however must be specified with the same value for all .GRAPH controls specifying the same graph sheet.

Conflicting values of ylog and xlog are resolved by plotting the curves on separate axes or graph sheets respectively.

Creating X-Y plots

To create an X-Y plot, use the XY() function. You should also specify "initXLims=false". E.g.

.GRAPH "XY( imag(vout), real(vout) )" initXLims=false xlog=LIN complete=true

The above will create a nyquist plot of the vector vout.

Using .GRAPH in sub-circuits

.GRAPH maybe used in a sub-circuit in which case a plot will be produced for all instances of that sub-circuit. Note, however, that it will only work for single values and not for expressions when inside a subcircuit. The value of the curveLabel parameter will be prefixed with the instance name so that the displayed curves can be correctly identified.

Examples

.graph C2_P curveLabel="Amplifier output" nowarn=true

Plots the vector C2_P and gives it the label "Amplifier output". As NOWARN is TRUE, no warning will be given if C2_P does not exist.

.graph vout_quad

+ axisType="grid"

+ axisName="grid1"

+ persistence=2

+ curveLabel="Quadrature"

+ nowarn=true

+ analysis = TRAN|DC

.graph vout

+ axisType="grid"

+ axisName="grid1"

+ persistence=2

+ curveLabel="In Phase"

+ yLabel="Filter Outputs"

+ nowarn=true

+ analysis = TRAN|DC

The above illustrates the use of the parameters AXISTYPE and AXISNAME. Both the vectors specified by the above .GRAPH controls will be plotted on the same but separate grid. Because both grids have been given the AXISNAME "grid1", each curve will be plotted on the same one. If the values of axisname for the above were different, each curve would be plotted on a different grid. The ANALYSIS parameter has been specified in both cases, so plots will only be created for transient and dc sweep analyses.


.ac
.ac - AC Analysis

Simulator control reference	See also

.ac DEC|OCT|LIN NUMPTS FSTART FSTOP

Instructs simulator to perform small signal ac analysis.

LIN	Analysis points are linearly spaced.

DEC	Analysis points are logarithmically spaced in decades

OCT	Analysis points are logarithmically spaced in octaves

NUMPTS	lin : Total number of points
dec : Number of points per decade
oct : Number of points per octave

FSTART	Start frequency

FSTOP	Stop frequency

An ac analysis calculates the small signal frequency response of the circuit about the dc operating point. The latter is automatically calculated prior to commencing the frequency sweep. One or more inputs may be specified for ac analysis by using voltage or current sources with the ac specification. The results of an ac analysis are always complex

Examples :

AC analysis from 1kHz to 1MHz with 25 points per decade:

.ac dec 25 1k 1meg


.alias

Simulator control reference

.alias alias_name device_name device_type

This control may only be used in device model library files. It is not recognised by the simulator. It permits a device model or subcircuit to be referenced by a different name. This allows one model definition to be used for multiple part numbers.

alias_name	Alias name

device_name	Device to which alias refers

device_type	Type of device to which alias refers. Must be one of the following
C, D, LTRA, NJF, NMF, NMOS, NPN, PJF, PMF, PMOS, PNP, R, SW or SUBCKT.
see .model for more details.

Example:

.model BC547C npn ( IS=7.59E-15 VAF=19.3 BF=500 IKF=0.0710 NE=1.3808

+    ISE=7.477E-15 IKR=0.03 ISC=2.00E-13 NC=1.2 NR=1 BR=5 RC=0.75 CJC=6.33E-12

+    FC=0.5 MJC=0.33 VJC=0.65 CJE=1.25E-11 MJE=0.55 VJE=0.65 TF=4.12E-10

+    ITF=0.4 VTF=3 XTF=12.5 RB=172 IRB=0.000034 RBM=65

.alias BC549C BC547C NPN

The above would provide identical definitions for both BC547C and BC549C bipolar transistors.

Notes:

.alias definitions will recognise models defined in other files provided the file in which the alias resides and the file in which the model definition resides are part of the same library specification. A library specification is a single pathname possibly with a wildcard ('?' or '*') to refer to multiple files. E.g. \Easy-SPICE\models\*.mod is a library specification and refers to all files with the extension '.mod' in the directory \Easy-SPICE\models.

Aliases must refer directly to a model or subcircuit definition and not to other aliases.


.dc
.dc - DC Sweep Analysis

Simulator control reference	See also

.dc device_name start stop step

.dc PARAM parameter_name start stop step

.dc MODEL model_name model_parameter_name start stop step

.dc TEMP start stop step

Instructs simulator to perform a DC sweep analysis.

device_name	Component reference of voltage source, current source, resistor or controlled source to be swept

start	Start value for sweep

stop	Stop value for sweep

step	Increment at each point

parameter_name	Parameter name. This would be used in an expression to define a component or model value.

model_name	Model name e.g. Q2N2222

model_parameter_name
Model parameter name e.g. IS

If start is arithmetically greater than stop then step must be negative.

A dc analysis performs a dc operating point analysis for a range of  linearly spaced values of the specified device, parameter, temperature or model parameter.

It is not necessary to declare parameters with .PARAM if using parameter sweep.

Sweep V1 from -5V to +5V in 0.2V steps

.dc V1 -5 5 0.2

Sweep the parameter Vthresh from 2 to 3 in steps of 0.1

.DC PARAM Vthresh 2.0 3.0 0.1

Sweep the BF parameter for the model Q2N2222  between 100 and 300 in steps of 10

.DC MODEL Q2N2222 BF 100 300 10


.ends

Simulator control reference

.ends

Terminates a sub-circuit definition. See .subckt


.file and .endf

Simulator control reference

.file filename

file_contents

.endf

The .file control allows the contents of a file referenced in a .MODEL control to be placed directly in the netlist. Files are referenced in arbitrary logic blocks, PWLFILE voltage sources, digital sources and digital state machines. Each of these may refer to files defined using .file and .endf.

Example

.model COUNT_8 d_logic_block file=counter_def

.file counter_def

PORT	(DELAY = 10n)	CountOut	out[0:7] ;

EDGE	(DELAY=5n, WIDTH=8, CLOCK=in[0])	Count ;

Count = Count + 1 ;

CountOut = count ;

.endf

The .MODEL control refers to a file called "counter_def". This could be a real disk file called counter_def or counter_def.ldf, but in the above example it is instead defined directly in the netlist using .file and .endf

Important Note

.file and .endf will not be recognised in library files.


.ic
.ic - Initial Condition

Simulator control reference

.ic V(NODE1)=VAL1  [ V(NODE2)=VAL2 ]...

This control sets transient analysis initial conditions.

NODE1, NODE2 etc.	Name of circuit node (or net) to which initial condition is to be applied. See notes below.

VAL1, VAL2 etc.	Voltage to be applied to net as initial condition.

If the UIC parameter is specified with the .tran control no DC operating point will be calculated so an initial condition will set the bias point in the same way as an IC=...  parameter on a BJT, capacitor, diode, JFET or MOSFET.

If the UIC parameter is absent from the .tran control then a DC operating point is calculated before the transient analysis. In this case the net voltages specified on the .ic control are forced to the desired initial values during the DC operating point solution. Once transient analysis begins this constraint is released. Note that the voltage force is effectively carried out via a 1Ω resistor so initial conditions will not work on low impedance nets.


.inc

Simulator control reference

.inc pathname

Insert the contents of the specified file.

pathname	File system pathname for file to be included

The .inc control is replaced by the specified file in its entirety as if was part of the original file. .inc controls may also be nested i.e. there may be .inc controls within the included file. Nesting may be to any level.


.keep

Simulator control reference

.keep /top|/subs|/noi|/nov|signalname [signalname [signalname ] ...]

This control instructs the simulator what values to store during a simulation. By default, all voltages and currents not within subcircuits are stored.

/subs	Store all available voltages and currents including subcircuit data. (Overrides /nov and /noi).

/nov	Don't store currents in voltage sources and inductors or any voltages.

/noi	Don't store currents. (Except those in voltage sources and inductors)

/top	If present, overrides /subs.

signalname.	Name of explicit signal (e.g. voltage or current) to store.

Note that currents in devices other than voltage sources or inductors are not available in ac or noise analysis. You can use 0V voltage sources as current probes in these analysis modes.


.lib

Simulator control reference	See Also

.lib PATHNAME

This control specifies a DOS pathname to be searched for model and sub-circuit libraries. Any number of .lib controls may be specified and wildcards (i.e. * and ? ) may be used. For further information refer to Device Library and Parts Management.

Example:

The following control instructs the simulator to search all files with the .mod extension in c:\simlib for any required sub-circuits or device models.

.lib c:\simlib\*.mod

If the path name contains spaces it must be enclosed in quotation marks (")


.model

Simulator control reference

.model MODELNAME MODELTYPE ( PARAM1=VAL1 [ PARAM2=VAL2 ]... )

This control specifies a set of model parameters that are used by one or more devices. .model controls usually reside in model libraries.

MODELNAME	Model name. Any text string to uniquely identify model. Must begin with a letter but may contain any legal ASCII character other than a space and '.' .

MODELTYPE	Model type. Must be one of the following:

XSPICE models

ad_converter	analog-to-digital converter
adc_bridge	analog-to-digital interface bridge
adc_schmitt	analog-to-digital schmitt trigger
cm_cap	Capacitor with voltage initial condition
cm_ind	Inductor with current initial condition
d_and	digital n-input and gate
d_buffer	digital one-bit-wide buffer
d_cap	Digital capacitor
d_dff	digital d-type flip flop
d_dlatch	digital d-type latch
d_fdiv	digital frequency divider
d_init	Digital initial condition
d_inverter	digital one-bit-wide inverter
d_jkff	digital jk-type flip flop
d_logic_block	arbitrary logic block
d_nand	digital n-input nand gate
d_nor	digital n-input nor gate
d_open_c	digital one-bit-wide open-collector buffer
d_open_e	digital one-bit-wide open-emitter buffer
d_or	digital n-input or gate
d_osc	controlled digital oscillator
d_pulldown	digital pulldown resistor
d_pullup	digital pullup resistor
d_pulse	digital pulse
d_ram	digital random-access memory
d_res	Digital resistor
d_source	digital signal source
d_srff	digital set-reset flip flop
d_srlatch	digital sr-type latch
d_state	digital state machine
d_tff	digital toggle flip flop
d_tristate	digital one-bit-wide tristate buffer
d_xnor	digital n-input xnor gate
d_xor	digital n-input xor gate
da_converter	digital-to-analog converter
dac_bridge	digital-to-analog interface bridge
s_xfer	s-domain transfer function block

SPICE Models

C	Capacitor
D	Diode
LTRA	Lossy transmission line
NJF	N-channel JFET
NMF	N-channel GaAsFET
NMOS	N-channel MOSFET
NPN	NPN BJT (Bipolar junction transistor)
PJF	P-channel JFET
PMF	P-channel GaAsFET
PMOS	P-channel MOSFET
PNP	PNP BJT
R	Resistor
SW	Voltage controlled switch
PARAM1, PARAM2 	Parameter name. Valid values depend on the model type.

VAL1, VAL2 etc	Parameter value.

Example:

The following is a model for a 1N5404 diode.

.model D1n5404  D(Is=15.48f Rs=7.932m Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=150p

+               M=.3 Vj=.75 Fc=.5 Isr=120n Nr=2 Bv=525 Ibv=100u)


.nodeset

Simulator control reference

.nodeset v(NODE1)=VAL1  [ v(NODE2)=VAL2 ]...

This control sets an initial guess voltage at the specified node for the dc operating point solution.

NODE1, NODE2 etc.	Name of circuit node (or net) to which nodeset is to be applied. See notes below.

VAL1, VAL2 etc.	Nodeset voltage to be applied.

Initially nodesets work exactly the same way as initial conditions. The nodeset voltage is applied via a 1 Ohm (by default) resistor and the solution is completed to convergence (by any of the methods). The nodeset is then released and the solution repeated. If the nodeset voltage is close to the actual solution the convergence of the second solution should be rapid.

Nodesets can be used to force a particular solution for circuits that have more than one stable state. Consider the following circuit:

A nodeset has been applied to the collector of Q1. This has forced Q1 to be on and Q2 to be off. If the nodeset were absent the solution would actually leave both Q1 and Q2 partially on. In real life this would not be stable but is numerically accurate.

The other application of nodesets is to help convergence for the DC bias point. With Easy-SPICE, it is rarely necessary to use nodeset's to find the DC solution of a circuit. They can, however, be useful for speeding up the operating point analysis for circuits that have already been solved.


.noise
.noise - Noise Analysis

Simulator control reference	See also

.noise V( OUTPUTNODE [, REFNODE  ] ) SOURCENAME DEC|LIN|OCT NUMPTS FSTART FSTOP [ INTERVAL ]

This control instructs the simulator to perform a noise analysis.

OUTPUTNODE	Node on circuit at which noise is measured.

REFNODE	Node to which OUTPUTNODE is referenced. Defaults to ground if omitted.

SOURCENAME	Input source (i.e. voltage or current) to which the input noise measurement is referred.

LIN	Analysis points are linearly spaced.

DEC	Analysis points are logarithmically spaced in decades

OCT	Analysis points are logarithmically spaced in octaves

NUMPTS	LIN : Total number of points
DEC : Number of points per decade
OCT : Number of points per octave

FSTART	Start frequency

FSTOP	Stop frequency

INTERVAL	If present, the simulator provides a much more comprehensive output including the individual contribution by each device to the output noise. There is little point in making this value anything other than 1.

During noise analysis the simulator calculates the total noise measured between the OUTPUTNODE and REFNODE at each frequency point. It also calculates and outputs this noise referred back to an input specified by SOURCENAME . As for all other analysis modes a DC operating point analysis is carried out first but, unlike AC analysis, the results of this analysis are not made available. If INTERVAL is not present the simulator outputs just three vectors. The output and input noise mentioned above named ONOISE and INOISE respectively and FREQUENCY. If  INTERVAL is present then a much larger number of vectors are generated covering the contribution from each noise generating device to the total output noise. The names of these extra vectors begin with the component reference of the device followed by a suffix to indicate the source of the noise within the device. A listing of the suffixes is given below. It is important to note that it is not the noise being generated by each device that is output but the proportion of that noise that is propagated to the output.

It is not necessary to specify a separate AC analysis alongside the noise analysis as it is with SPICE2 and commercial derivatives of SPICE2. (Easy-SPICE is based on SPICE3).

The magnitude of any AC independent voltage or current source on the circuit has no effect on the results of a noise analysis.

All noise results are in V/√Hz except input noise referred back to a current source which is in A/√Hz.

Device vector name suffixes

BJT:

#rc	Noise due to collector resistance

#rb	Noise due to base resistance

#re	Noise due to emitter resistance

#ic	Shot noise in collector

#ib	Shot noise in base

#1overf	Flicker (1/f) noise

no suffix	Total transistor noise

Diode:

#rs	Noise due to series resistance

#id	Shot noise

#1overf	Flicker (1/f) noise

no suffix	Total diode noise

JFET and all MOSFET's:

#rd	Noise due to drain resistance

#rs	Noise due to source resistance

#id	Shot noise in drain

#1overf	Flicker (1/f) noise

no suffix	Total JFET noise

Resistor, Voltage controlled switch

no suffix	Total device noise

Examples:

Run noise analysis from 100Hz to 1MHz with 25 points per decade. Calculate noise at node named vout and noise referred back to voltage source vin .

.noise V( vout ) vin dec 25 100 1meg

Run noise analysis from 10Hz to 100kHz with 25 points per decade. Calculate noise between nodes vout and q1_c and noise referred back to input current source I1. Calculate contribution to output noise by each noise generating device.

.noise V( vout, q1_c ) I1 dec 25 10 100k 1


.op
.op - Bias Point Analysis

Simulator control reference	See also

.op

This control instructs the simulator to perform a DC operating point analysis. Note that a DC operating point analysis is carried out automatically for transient (unless the UIC parameter is specified), ac, .dc, transfer function and noise analyses.

DC operating point analysis attempts to find a stable bias point for the circuit. It does this by first applying an initial guess and then uses an iterative algorithm to converge on a solution. If it fails to find a solution by this method the simulator then attempts two further strategies.

For the first, known as "GMIN stepping", an impedance is effectively placed between each node of the circuit and ground and the solution calculated. If successful then the impedance is increased and a further solution sought using the previous solution as a starting point. This procedure is repeated until the impedance is effectively removed.

If this approach fails a second strategy known as "source stepping" is employed. For this all voltage and current sources in the circuit are initially set to near zero and the solution found. The sources are then gradually increased until they reach their final value.

If the final approach fails then the analysis will abort.

"OFF" Parameters.

Some semiconductor devices feature the device parameter "OFF". If there are devices in the circuit which specify this parameter, the bias point solution is found in two stages. In stage 1 the devices with "OFF" specified are treated as if their output terminals are open circuit and the operating point algorithm completes to convergence. In stage 2, The "OFF" state is then released and the solution restarted but initialised with the results of stage 1.

The result of this procedure is that "OFF" devices that are part of latching circuits are induced to be in the OFF state. Note that the "OFF" parameter only affects circuits that have more than one possible DC solution such as bistables. If the "OFF" parameter is specified in - say - an amplifier circuit - with a unique solution, the final result will be the same. It will just take a little longer to arrive at it.

Nodesets

Nodesets work in a similar way to the "OFF" parameter in that the solution is found in two stages. In the first the "nodeset" is applied and the solution found. It is then released and convergence continues. Nodeset are an aid to convergence and, like the "OFF" parameter, can coerce a particular solution if there is more than 1 stable state See .nodeset for details

Initial Conditions

Initial conditions force a particular voltage at a circuit node during bias point solution. The force is released for any subsequent analysis. See .ic for more details.

Operating point output file

During the operating point analysis, a file is created which provides information on the operating values of every device in the circuit. This file has the name OP.TXT by default but this can be changed. Three simulator options control the name and creation of this file. These are:

NOOPINFO	If set, the operating point info file is not created

OPINFO	If set, the operating point info file is created for other analyses as well as .OP

OPINFOFILE	Sets name of file to receive operating point info


.options
.options - Simulator options

Simulator control reference

.options [ OPT1 [=VAL1]] ...

This control allows the setting of various options specific to the simulator.

OPT1	Option name. Must be one specified in list below.

VAL1	Option value. Not all options have a value.

List of simulator options

Option name	Default value	Units	Description
ABSTOL	1p	A	The absolute current error tolerance. It is sometimes desirable to increase this for circuits that carry large currents (>1A) to speed the solution and aid convergence.
ABSTOLMAX	1µ	A	ABSTOL selectively relaxed to this value if needed to allow transient analysis to continue. See Convergence and accuracy issues
BADMOS3	Off		For compatibility with old versions of SPICE. MOS3 model in version 3e and earlier had discontinuity which was fixed for 3f. This option disables fix.
CHGTOL	1e-14	Coulombs	The absolute charge tolerance. It is not usually necessary to change this value.
DEFL	100	metres	Default value for MOS channel length
DEFW	100	metres	Default value for MOS channel width (metres)
DEFAD	0	m2	Default value for MOS drain diffusion area.
DEFAS	0	m2	Default value for MOS source diffusion area m2.
DigMinTime	1pS	Secs	Minimum digital resolution. Not yet fully supported
FLUXTOL	1e-11	V.secs	The absolute flux tolerance for inductors. It is not usually necessary to change this value.
GMIN	1e-12	Siemens (mhos)	The minimum conductance allowed by the program. This has the effect of placing a resistor = 1/GMIN in parallel with every branch of the circuit.
GMINMULT	10		Multiplier at each step of GMIN stepping method.
GMINSTEPS	10		Number of steps used for GMIN stepping method of finding dc operating point. See .OP
GMINSTEPITERLIMIT	20		Iteration limit for each step in GMIN stepping.
ITL1	100		DC iteration limit.
ITL2	50		DC sweep iteration limit.
ITL4	10		Normal transient timepoint iteration limit.
ITL6			Same as SRCSTEPS
ITL7	40		Upper transient timepoint iteration limit. This is specific to Easy-SPICE. See Convergence and accuracy issues
LogicThreshHigh	5	V	Output voltage for logic high level. Used for & | and ~ operators for arbitrary source. See Arbitrary source
LogicThreshLow	0	V	Output voltage for logic low level. Other comments as for LogicThreshHigh
LogicHigh	2.2	V	Upper threshold for logic inputs. Other comments as for LogicThreshHigh
LogicLow	2.1	V	Lower threshold for logic inputs. Other comments as for LogicThreshHigh
MatchedSubcircuits	off		If set, components within subcircuits are treated as matched for Monte Carlo analysis
MAXORD	2		Maximum integration order. For "METHOD=TRAP" max value is 2. For "METHOD=GEAR" max value is 6. There are few advantages to changing this value.
MC_ABSOLUTE_RECT	Off		If set Monte Carlo distribution will be rectangular for absolute tolerances. Otherwise the distribution will be Gaussian.
MC_MATCH_RECT	Off		If set Monte Carlo distribution will be rectangular for matched tolerances. Otherwise the distribution will be Gaussian.
METHOD	trap		Numerical integration method. Either "TRAP" (default) or "GEAR". More info: See Convergence and accuracy issues
MINBREAK	5e-5 X tmaxstep	secs	Minimum time between transient analysis breakpoints. A breakpoint is a point in time when an analysis is forced regardless of whether it is required by the timestep selection algorithm. Typically they are set at known turning points such as the start and end of a rising pulse. If two breakpoints are closer than MINBREAK they are merged into one. (there are exceptions to this e.g if the two breakpoints were generated by a single rising edge). Increasing MINBREAK can help convergence and simulation speed especially if transmission lines are used. (tmaxstep is the last parameter of the .tran control.)
MINGMINMULTIPLIER	1.000001		In GMIN stepping, the step size is multiplied by variable factor at each step. This step is reduced if convergence fails. If it is reduced below this value, the simulation will abort.
MinTimeStep	1e-9 * Max time step	Secs	Minimum transient time step. Simulation will abort if it reaches this value.
NOOPINFO	Off		Switches off creation of operating point info file for .OP analyses.
NOOPITER	off		Use GMIN stepping for DC operating point analysis first. (i.e skip normal iteration method)
NORAW	off		Output transient analysis values at intervals of tstep only. See .TRAN
NOSENSFILE	Off		Switches off creation of sensitivity analysis data file.
OLDLIMIT	Off		If set SPICE 2 MOS limiting algorithm is used.
OldMosNoise	Off		MOS2 and BSIM3 devices return device noise in V2/Hz for standard SPICE3 whereas other device's noise is returned in V/√Hz. With Easy-SPICE all devices return noise in V/√Hz. Setting this option restores to behaviour th that of standard SPICE.
OPINFO	Off		If set DC operating point info file is created for all analyses. Normally it is created only for .OP analyses.
OPINFOFILE	Off		Specify name of operating point info file. This is OP.TXT by default.
PIVREL	1e-3		This affects the matrix solution. Setting this parameter to a high value e.g, 0.99 can sometimes fix convergence problems but will slow down the simulation. Valid values lie between 0 and 1.
PIVTOL	1e-13		The absolute minimum value for a matrix entry to be accepted as a pivot. Unexplained "Singular matrix" errors can sometimes be overcome by lowering this value. (But note that "Singular matrix" errors are usually caused by errors in the circuit such as floating nodes or shorted voltage sources).
RELTOL	0.001		This is the relative tolerance that must be met for each analysis point. Reducing this number will improve accuracy at the expense of simulation time or/and convergence reliability. Simulation results can not be relied upon if its value is increased beyond 0.01. A more detailed discussion is given in Convergence and accuracy issues
RELTOLMAX	0.01		RELTOL selectively relaxed to this value if needed to allow transient analysis to continue. See Convergence and accuracy issues
SENSFILE	"SENS.TXT"		Specify name of sensitivity data file.
SearchDefaultTol	off		If set, the library is searched for default models prior to a Monte Carlo analysis.
SRCSTEPS	10		Number of steps used for source stepping method of finding dc operating point.
TEMP	27	(C)	Operating temperature of circuit. Note this value can be overridden locally for some devices. You can also use .TEMP for this.
TIMESTATS	Off		Full simulation timing statistics are generated if this is enabled. Note that this can slow down runs for small circuits on Windows 95 and 98 platforms.
TNOM	27	(C)	Temperature at which model parameters are defined. This can be overridden in the model control.
TRTOL	7		This only affects transient analysis. It is a relative value that is used to determine an acceptable value for the "local truncation error" before an analysis point is accepted. Reducing this value cause the simulator to model the effects of energy storage elements more accurately at the expense of simulation time.
TRYTOCOMPACT	Off		Forces compaction of data for lossy transmission lines. This speeds up simulation at the expense of accuracy.
VNTOL	1μ	V	The absolute voltage error tolerance. Circuits with large voltages present (>100) may benefit from an increase in this value.
VNTOLMAX	1m	V	VNTOL selectively relaxed to this value if needed to allow transient analysis to continue. See Convergence and accuracy issues


.param

Simulator control reference	See Also

.PARAM parameter_name parameter_value [parameter_name parameter_value]...

where parameter_name may be:

A constant

or

An expression enclosed by '{' and '}'

.PARAM Examples

.PARAM Vthresh 2.4

.PARAM Vthresh {(Vhigh+Vlow)/2}

.PARAM F0 1k Alpha 1 C1 {2*c2}

.PARAM R1 {2/(2*pi*freq*C1*alpha}

Constants

The following constant values may be used

E	2.71828

PI	3.14159

TRUE	1

FALSE	0

Note that these values may not be used in arbitrary source expressions unless enclosed by '{' and '}'.

Global Simulation Parameters

The parameter TEMP may be used. This returns the circuit temperature in Celsius. The value is updated during temperature sweeps.

How parameter expressions are evaluated

The following describes the sequence in which netlist expressions are evaluated.

1.	When the netlist is read in, an attempt is made to evaluate any expressions making only the values of command line parameters available. If the evaluation is successful, the expression is substituted with the result of the evaluation. If it is not the expression is passed on to the simulator.

2.	When the simulation starts all constant .PARAM values are stored, then any .PARAM controls which themselves are an expression are evaluated. At this stage, any swept parameters (in a .DC control) are not made available nor is the global TEMP parameter for a temperature sweep.

3.	At this stage, unless the analysis is a temperature sweep or parameter sweep, all expressions should have been successfully evaluated. If any remain, an error will be flagged and the simulation will abort. For the case of temperature or parameter sweeps some expressions that depend on the swept parameter will remain unresolved. These will be evaluated at each stage of the sweep.

Parameter Rules

Expressions that depend only on command line values can be placed anywhere in the netlist except for the device name; they can even be used for node names (although we would advise great caution if doing this). They don't have to be numeric expressions they can resolve to a text string. Expressions that depend on global or .PARAM parameters may only be used for instance parameters, model parameters and parameters passed to subcircuits.

Parameters defined in .PARAM controls may be used in arbitrary source expressions directly. E.g.

.PARAM Vthresh 2.3

B1 n1 n2 v=(v(n4)-Vthresh)*v(n3)

Parameters defined on the command line may not be used in this way although the following is legal:

In script or command line:

Let Vthresh=2.3

In netlist

B1 n1 n2 v=(v(n4)- {Vthresh} )*v(n3)

.PARAM netlist order

.PARAM controls that resolve to a constant are order independent ; they can be placed anywhere in a netlist. They can even be placed after another .PARAM expression that depends on its value (but note this does not apply in subcircuits). .PARAM controls that are defined as an expression that depends on other .PARAM's also defined as an expression must be placed in sequential order. For example, the following is OK:

.PARAM C2 {C1*alpha*alpha/4}

.PARAM C1 1n

.PARAM alpha 1

.PARAM R1 {2/(2*PI*F0*C2*alpha}

The first .PARAM depends on alpha and C1 which are defined later in netlist. This is OK (as long as it is not in a subcircuit) because alpha and C1 are constants. The fourth .PARAM depends on C2 which is defined as an expression. The definition for must - and does in the above example - come before the definition of R1. The following would yield an error as the definition for C2 comes after the definition of R1:

.PARAM R1 {2/(2*PI*F0*C2*alpha}

.PARAM C1 1n

.PARAM alpha 1

.PARAM C2 {C1*alpha*alpha/4}

Note that .PARAM's inside sub-circuits are local to the sub-circuit. This is explained in next section.

Subcircuit Parameters

Parameters may be declared within sub circuits. E.g

.subckt ADevice n1 n2 n3 n4

.PARAM Vthresh 3.5

...

...

ends

In the above example, in reference to Vthresh within the subcircuit would use the value declared by the .PARAM declared inside the subcircuit. That value would not be available outside the subcircuit definition. Parameters may also be passed to subcircuits.  E.g.

X1 1 2 3 4 ADevice : threshold=2.4

or

X1 1 2 3 4 ADevice params: threshold=2.4

Any reference to threshold within the sub-circuit definition would use that value.

Default values for parameters may also be specified in sub-circuit definition:

.subckt ADevice n1 n2 n3 n4 params: threshold=2.4

...

.ends

If that sub-circuit is called without specifying threshold the default value of 2.4 will be used. Note that it is not compulsory to declare default values.


.sens

Simulator control reference

.sens v(nodename [,refnodename])| i(sourcename)

This control instructs the simulator to perform a DC sensitivity analysis. In this analysis mode, a DC operating point is first calculated then the linearised sensitivity of the specified circuit voltage or current to every model and device parameter is evaluated. The results are output to a file (SENS.TXT by default but can be changed with SENSFILE option) and they are also placed in a new Group. The latter allows the data to be viewed in the message window (type Display) at the command line and can also be accessed from scripts for further analysis.

This analysis mode is not supported by the Choose Analysis... dialog box. To specify this mode, enter the above control in the text window (press F11)


.subckt

Simulator control reference

.subckt subcktname N1 [ N2 ]...[params: param_name1 param_value1 [param_name2 param_value2]...]

This control begins a subcircuit definition.

subcktname	Sub-circuit name. This must begin with a letter but may contain any legal ASCII character except any whitespace (space, tab) or ' . ' . The name must be unique i.e. no other subcircuits may have the same name.

N1, N2 etc	Node names available externally. Must not be zero.

param_name, param_value
Parameter name and value. This sets default values for parameters used within the subcircuit. These values can be overridden for each subcircuit instance. See Using Expressions for Circuit Parameters. for more info. Note that it is not compulsory to declare default values for subcircuit parameters

A sub-circuit consists of a .subckt control followed by a series of device or model descriptions and terminating in a .ends control. A sub-circuit is a circuit that can be called into the main circuit (or indeed another subcircuit) by reference to its name. The .subckt control is used to define the subcircuit while a subcircuit call - an 'X' device - is used to create an instance of that sub-circuit. Subcircuits have a number of uses:

•	To repeat a commonly used section of circuit.

•	To hide detail from the main circuit to aid circuit readability.

•	To distribute models of integrated devices such as op-amps.

For a detailed discussion refer to Subcircuits.

Subcircuit definitions usually reside in a text file and are read in as libraries. Refer to Using the model library.


.temp

Simulator control reference

.temp TEMPERATURE

This control sets the default simulation temperature. Some devices can override this on a per instance basis. Units are degrees centigrade.


.tf
.tf - Transfer Function Analysis

Simulator control reference	See also

.tf V( NODE1 ,NODE2 ) SOURCENAME

or

.tf I( VSOURCENAME ) SOURCENAME

This control instructs the simulator to perform a small signal transfer function analysis.

NODE1, NODE2	Output of circuit as voltage. Note that NODE2 is compulsory unlike standard SPICE3. Use '0' to refer to ground

SOURCENAME	Input source. This can be a current or voltage.

VSOURCENAME	Output of circuit as current.

This analysis mode calculates transfer function parameters with the circuit linearised about the operating point. Input impedance, output impedance and the gain from input to output are calculated. These values are assembled together in a group in the same way as other analysis modes. To view the results type display at the command line.


.trace

Simulator control reference

.trace signal_name graph_ id [signal_name graph_id]...

Where 	signal_name is the name of a net or pin
graph_ id is an integer between 1 and 999 to specify which graphs traces should use - see explanation below

This control instructs the simulator to plot the specified signal as the simulation proceeds. These are known as "traces".

graph_ id is an arbitrary number that makes it possible to direct traces to different graphs. Two traces with the same id will be always be put in the same graph. Traces from subsequent simulations with that id will also go to that graph if it still exists otherwise a new one will be created. To force two traces to go to separate graphs, use different id's. Note that it doesn't matter what the id's value actually is - it could be 1 or 100 - as long as traces that must go to the same graph use the same value.

Note that the AutoAxis feature available for normal plotting also works for Traces. So if a current and voltage trace are both directed to the same graph, separate axes will be created for them.

Examples

.trace v1_p 1 q1#c 1

In the above example a voltage - v1_p - and a current - q1#c - will both be traced on the same graph. As they have different units, the AutoAxis feature will force the curves to two different y axes.

.trace v1_p 1 q1#c 2

In this example the voltage and current traces will be directed to different graph sheets.

Notes

The .TRACE control has now been largely superseded by the .GRAPH control which is much more flexible. However, the .TRACE control is still useful for specifying multiple traces on a single line. .GRAPH can only specify one signal at a time.


.tran
.tran - Transient Analysis

Simulator control reference	See also

.tran TSTOP

OR

.tran TSTEP TSTOP [ TSTART [ TMAXSTEP ]] [ UIC ]

This control instructs the simulator to perform a transient analysis. In this mode the simulator computes the behaviour of the circuit over the specified time interval. The circuit's currents and voltages are calculated at discrete time points separated by a variable time step. This time step is adjusted automatically by the simulator according to circuit activity. The circuit may contain any number of time varying voltage and current sources (stimuli) to simulate external signals, test generators etc..

TSTEP	This parameter behaves differently with Easy-SPICE than with SPICE and SPICE derivatives. In standard SPICE it affects the interval between printed results but has no effect on the simulation time step. In Easy-SPICE this only affects the simulation if the option noraw (see .options) is specified. In this case simulation output is only produced at intervals of TSTEP. This saves memory at the expense of detail. In most circumstances it is best to set this to zero (or omit it altogether using first form of the .tran control shown above) in which case noraw is disabled. TSTEP is also used to define default values for pulse and exponential stimuli.
Note that if TSTEP and noraw are specified a simulation time point is forced at TSTEP intervals in order to calculate the output. This differs from SPICE and many of its derivatives which generate output at TSTEP by interpolation.

TSTOP	Stop time.

TSTART	Start time. This is the time at which the storage of transient analysis outputs commences. It is not the time at which the analysis begins; this is always zero. TSTART is zero if it is omitted.

TMAXSTEP	Maximum time step. In periods of inactivity in the circuit the simulator increases the time step in order to minimise total simulation time. TMAXSTEP is the largest value for the timestep that will be used. If not specified it is set to (TSTOP-TSTART)/50 .

UIC	If this is specified a DC operating point is not calculated prior to the transient analysis and initial condition specifications are used instead

Note:

Form 1 (see above) of the .tran control is specific to Easy-SPICE and is not supported by standard SPICE.


AC Source

AC ( [MAG [PHASE ]] )

This specification is used only with ac and noise analyses.

MAG	Magnitude (Volts or amps)	Default if omitted = 1

PHASE	Phase (degrees)	Default if omitted = 0


ADC model

Netlist entry:

Axxxx analog_in clock_in [ data_out_0 data_out_1 .. data_out_n ] data_valid model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
analog_in	Analog input	in	v	v, vd, i, id	n/a
clock_in	Clock input	in	d	d	n/a
data_out	Data output	out	d	d	1 - 32
data_valid	Data valid output	out	d	d	n/a
Model format:

.MODEL model_name ad_converter parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
input_offset	Offset voltage	real	0	none	No	n/a
input_range	Input full scale signal range	real	1	none	No	n/a
twos_complement	Use 2's complement output. (default - offset binary)	boolean	FALSE	none	No	n/a
convert_time	Total conversion time	real	1.00E-06	0 - INF	No	n/a
min_clock	Min clock period	real	5.00E-07	0 - INF	No	n/a
data_valid_delay	Data valid inactive time	real	1.00E-07	0 - INF	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
input_load	Input load	real	1.00E-12	0 - INF	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

This is a 1-32 bit analog to digital converter. The operation of this device is illustrated by the following diagrams:

Conversion timings.

The ADC starts the conversion at the rising edge of the clock. The analog input signal is also sampled at this point. The output data changes in response to this, CONVERT_TIME seconds later. At the same time the data_valid output goes low (inactive) then high again after a delay equal to DATA_VALID_DELAY. It is possible to start a new conversion before the previous conversion is complete provided it is started later than MIN_CLOCK seconds after the previous conversion was started. MIN_CLOCK must always be less than CONVERT_TIME. If the MIN_CLOCK specification is violated, the conversion will not start.


ALB - Combinational Register Declaration
Combinational Register Declaration

Arbitrary logic block langauge definition -  Registers and variables

COMB (	[, DELAY=reg_delay]
[, WIDTH=reg_width]
[, BITWISE=0|1 ] ) name [ = initial_condition ] ;

reg_delay	Register delay in seconds. You can use engineering units in the normal way. If BITWISE  is '1' (the default) this delay is applied on a bit by bit basis. If  BITWISE is '0' then the delay is applied to the whole register. That is the output will not change until all inputs have remained stable for the delay time. Setting BITWISE to '0' is useful when using combinational registers to implement asynchronous state machines as it eliminates race conditions.
Default: REG_DELAY parameter in .MODEL control defines default value. This is turn has a default value of 1nS.

reg_width	Register width in bits. This has a maximum of 32.
Default: 32

name	Register name.

initial_condition	Value assigned to register when simulation starts.
Default: 0


ALB - Example 1
Arbitrary logic block - Example 1

Arbitrary logic block overview

We start with a simple example. The following is a description of a simple 8 bit synchronous counter.  (This definition would be put into a file referred to in a .MODEL control. This is described later). A circuit using this model is supplied as an example. See Examples\ALB_Examples\Count.sch

PORT	(DELAY = 10n)	CountOut	out[0:7] ;

EDGE	(DELAY=5n, WIDTH=8, CLOCK=in[0])	Count ;

Count = Count + 1 ;

CountOut = count ;

We will go through this line by line.

The first line:

PORT	(DELAY = 10n)	CountOut	out[0:7] ;

is a PORT statement and in this case defines the characteristics of an output.

"(DELAY = 10n)"

says that the output delay is 10nS that is the actual output pins will change state 10nS after the output is assigned.

"CountOut" names the output CountOut.

"out[0:7]" defines the port as an output and specifies the actual pins used on the device. This specifies the first 8 pins on the output port. There are two sets of pins on an ALB one assigned for inputs and referred to as "in[a:b]" and the other assigned for outputs and referred to as "out[a:b]". The line ends in a semi-colon which terminates the statement. All statements must end in a semi-colon.

The next line:

EDGE	(DELAY=5n, WIDTH=8, CLOCK=in[0])	Count ;

defines an edge triggered register.

CLOCK=in[0] specifies the pin used for the clock (it must always be an input pin). This is always positive edge triggered.

DELAY=5n

This is the clock to output delay. (See illustration below)

WIDTH=8

This specifies the width of the register i.e. 8 bits

The next line:

Count = Count + 1 ;

defines the operation to be performed at each clock edge. In this case the value in the register is simply incremented by one. When it reaches 255 it will reset to 0.

The final line

CountOut = count ;

defines what appears at the output. This says that the output equals the count register.

The following diagram illustrates the internal structure of the counter.

Reset Count at 200

We will now make a small modification to the counter so that the counter only counts up to 199 before resetting back to zero. Change the line:

Count = Count + 1 ;

to:

Count = Count==199 ? 0 : Count + 1 ;

This says "If the count equals 199 set to zero otherwise increment by one". As before, this will happen on each clock edge.

Add an Asynchronous Reset

The logic definition language supports the addition of asynchronous controls to synchronous registers. Here we will add an asynchronous reset. The complete definition becomes:

PORT   (DELAY = 10n)  CountOut   out[0:7] ;

PORT                  Reset      in[1] ;

EDGE	(DELAY=5n, WIDTH=8, CLOCK=in[0])	Count ;

Count := !Reset ? 0 ;

Count = Count==199 ? 0 : Count + 1 ;

CountOut = count ;

To add the reset signal we have to add two lines to the definition. The first:

PORT                  Reset      in[1] ;

defines the signal pin to be used for the reset and the second:

Count := !Reset ? 0 ;

defines the action to be taken. This is an synchronous action statement. The '!' means NOT so the line says "If  Reset is NOT TRUE (i.e. low) set the count to zero otherwise do nothing. Asynchronous action statements are always of the form:

register_name := condition ? action ;

The ':' signifies that the statement is asynchronous and that the action should happen immediately.


ALB - Example 2
Arbitrary logic block - Example 2

Arbitrary logic block overview

A Simple Multiplier

PORT (DELAY=10n)    MultOut out[0:7] ;

PORT                in1 in[0:3] ;

PORT                in2 in[4:7] ;

MultOut = in1*in2 ;

The above defines a simple combinational circuit, that of a 4X4 digital multiplier. The inputs in1 and in2 are treated as 4 bit unsigned values so if both are zero the output will be zero and if both are 1111 (i.e. 15) the result will be 11100001 (i.e. 225). See the circuit EXAMPLES\ALB_Examples\Mult.sch.


ALB - Example 3
Arbitrary logic block - Example 3

Arbitrary logic block overview

A ROM Lookup Table

The following definition is that of a lookup table to define a sine wave:

PORT (DELAY=10n) ROMout out[0:7] ;

PORT             input  in[0:7] ;

READONLY (WIDTH=8) ROM[256] =

128, 131, 134, 137, 140, 143, 146, 149, 152, 156, 159, 162,

165, 168, 171, 174, 176, 179, 182, 185, 188,  191, 193, 196,

199, 201, 204, 206, 209, 211, 213, 216, 218, 220, 222, 224,

226, 228, 230, 232, 234, 236,  237, 239, 240, 242, 243, 245,

246, 247, 248, 249, 250, 251, 252, 252, 253, 254, 254, 255,

255, 255, 255,  255, 255, 255, 255, 255, 255, 255, 254, 254,

253, 252, 252, 251, 250, 249, 248, 247, 246, 245, 243, 242,

240, 239, 237, 236, 234, 232, 230, 228, 226, 224, 222, 220,

218, 216, 213, 211, 209, 206, 204, 201, 199,  196, 193, 191,

188, 185, 182, 179, 176, 174, 171, 168, 165, 162, 159, 156,

152, 149, 146, 143, 140, 137,  134, 131, 128, 124, 121, 118,

115, 112, 109, 106, 103, 99, 96, 93, 90, 87, 84, 81, 79, 76,

73, 70,  67, 64, 62, 59, 56, 54, 51, 49, 46, 44, 42, 39, 37,

35, 33, 31, 29, 27, 25, 23, 21, 19,  18, 16, 15, 13, 12, 10,

9, 8, 7, 6, 5, 4, 3, 3, 2, 1, 1, 0, 0, 0, 0, 0,  0, 0, 0, 0,

0, 0, 1, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 15, 16,

18, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 42, 44, 46,

49, 51, 54, 56, 59, 62, 64,  67, 70, 73, 76, 79, 81, 84, 87,

90, 93, 96, 99, 103, 106, 109, 112, 115, 118, 121, 124 ;

ROMout = ROM[input] ;

See the example circuit EXAMPLES\ALB_Examples\SineLookUp.sch


ALB - Example 4
Arbitrary logic block - Example 4

Arbitrary logic block overview

Example 4 - D Type Flip Flop

The following is the definition for the 74X74 Dtype flip flop supplied with the standard Easy-SPICE model library. This model is somewhat more complicated as it models a number of timing artefacts such as setup time and minimum clock width. Each line below has been annotated to describe its function. Full details are explained in Language definition.

// Input port definitions

PORT D      in[0] ;    // D input

PORT CK     in[1] ;    // Clock

PORT SR     in[2:3] ;  // Set/reset inputs. r bit 3 s bit 2

PORT out    out[0:1] ; // Outputs Q and !Q

// Edge triggered register.

// HOLD is hold time i.e. time after clock edge that data must

// remain stable. Setup time is implemented by delaying the D input

// MINCLOCK is minimum clock width.

// USER[n] references values supplied in the .MODEL control

// The final '=2' initialise the register with the value 2 i.e.

// Q=0 and Q!=1

EDGE (WIDTH=2, DELAY=USER[4], HOLD=USER[2], MINCLOCK=USER[3], 	CLOCK=in[1]) DTYPE=2;

// COMB defines a combinational register. This is effectively a

// delay element. These delay the D input (to implement setup

// time) and the set/reset inputs to implement minimum

// set and reset times

COMB (DELAY=USER[0], WIDTH=1) D_DEL ;

COMB (DELAY=USER[1], WIDTH=2) SR_DEL ;

// These assign the combinational registers

SR_DEL  = SR ;

D_DEL   = D ;

// asynchronous action

DTYPE   := SR_DEL==1||SR_DEL==2 ?  (SR_DEL==2 ? 1 : 2) ;

// synchronous action

DTYPE   = D_DEL ? 1 : 2 ;

// Both outputs are forced high if S and R are both active

// Output will be restored to previous value when one of S and R

// becomes inactive

out     = SR_DEL==0 ? 3 : DTYPE  ;


ALB - Language definition
Arbitrary logic block - Language definition

Arbitrary logic block overview

All logic definitions are divided into two sections. The first contains the ports and register definitions and the second section consists of the assignment statements. (The first section can be empty in very simple cases).

The following topics provide a full description of the language definition.

Constants and Names

Ports

Registers and variables

Assignments

USER and DEVICE values

Diagnostics: Trace file


ALB - Level Triggered Register Declaration
Level Triggered Register Declaration

Arbitrary logic block langauge definition -  Registers and variables

LEVEL (	CLOCK=input_pin_spec
[, DELAY=reg_delay]
[, WIDTH=reg_width]
[, SETUP=reg_setup_time]
[, ASYNCDELAY=reg_asyncdelay]
[, BITWISE=0|1 ]  name [[array_size]]
[ = initial_condition  *[, initial_condition]] ;

input_pin_spec	This specifies which input pin is the enable and must be of the form: IN[n] where n is a pin number. See Language definition - Ports for details on how pin numbers relate to netlist entries and symbol definitions.

reg_delay	Register delay in seconds. If the enable is already high, this is the time taken for the register to acquire new data. Otherwise it is the delay between enable rising edge and the register value changing. You can use engineering units in the normal way.
Default: REG_DELAY parameter in .MODEL control defines default value. This is turn has a default value of 1nS.

reg_width	Register width in bits. This has a maximum of 32.
Default: 32

reg_setup_time	Register hold time. This is the time that the input data (i.e. assignment value) must remain stable prior to an  enable falling edge, for the new value to be accepted. If the BITWISE parameter is set to '1' (which it is by default) the setup time is applied on a bit by bit basis. That is any individual bit in the register that remains stable during the setup period will attain the new value even if other bits violate the setup time. If BITWISE is '0' then if a single bit violates the setup time, the whole register will remain unchanged even if some bits remain stable during the setup period. Setting BITWISE to '0' saves system memory which can be important for large arrays (i.e. RAMs).
Default: SETUP_TIME parameter in .MODEL control defines default value. This in turn has a default of 0.

reg_asysncdelay	Time the register takes to acquire a value set by an asynchronous assignment. This must be less than or equal to reg_delay.
Default: reg_delay

BITWISE value	See reg_setup_time
Default:  '1' for single registers, '0' for arrays.

name	Register name.

array_size	If specified, the register is arranged as an addressable array of size array_size.
Default: 1

initial_condition	Value assigned to register when simulation starts.
Default: 0


ALB - Read-only Register Declaration
Read-only Register Declaration

Arbitrary logic block langauge definition -  Registers and variables

READONLY ([, WIDTH=reg_width]  name[[array_size]]
[ = initial_condition  *[, initial_condition]] ;

reg_width	Register width in bits. This has a maximum of 32.
Default: 32

array_size	If specified, the register is arranged as an addressable array of size array_size.
Default: 1

name	Register name.

initial_condition	Value assigned to register when simulation starts.
Default: 0

Read-only registers are usually arranged as an addressable array. When reading a read-only register, the value returned is the value defined by the initial conditions. As the name implies it is not possible to assign read-only registers.


ALB Def Constants and Names
Arbitrary logic block langauge definition -  Constants and Names

ALB language definition overview

Constants follow the usual rules. Any decimal number with optional sign and exponent or engineering suffix is permitted. In addition, numbers in hexadecimal are also allowed. The format is the same as for the 'C' programming language i.e. prefixed with '0X'. E.g.:

0X10 = 10 hex = 16.

Identifiers used for register, port and variable names must begin with an alphabetic character or underscore and consist of alphanumeric characters and underscores.


ALB MODEL parameters
Arbitrary logic block - Netlist entry and .MODEL parameters

Arbitrary logic block overview

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] [ out_0 out_1 .. out_n ] model_name : parameters

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	none
out	Output	out	d	d	none
Instance parameters:

Name	Description	Type	Array?
trace_file	Trace file	string	No
user	User device params	real	Yes
Model format:

.MODEL model_name d_logic_block parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
file	Definition file name	string	none	none	No	n/a
def	Definition	string	none	none	No	n/a
out_delay	Default output delay	real	1.00E-09	1e-12 - INF	No	n/a
reg_delay	Default internal register delay	real	1.00E-09	0 - INF	No	n/a
setup_time	Default level triggered setup time	real	0	0 - INF	No	n/a
hold_time	Default edge triggered hold time	real	0	0 - INF	No	n/a
min_clock	Default minimum clock width	real	0	0 - INF	No	n/a
trace_file	Trace log file	string		none	No	n/a
user	User defined parameters	real	none	none	Yes	none
user_scale	Scale of user vals	real	1	0 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Notes

Usually the logic block definition would be placed in a file referred in the FILE parameter. Alternatively the definition may be placed directly in the .MODEL control as the value of the DEF parameter. In this case the definition must be enclosed in quotation marks (").

The USER_SCALE parameter scales all values found in the USER parameter.


ALB def - Assignments
Arbitrary logic block langauge definition -  Assignments

ALB language definition overview

Registers and output ports can be assigned using the assignment operator '='. Assignment values can be constants, input ports, other registers, local variables or expressions of any or all of these. Assignments are of the form:

register | output_port | OUT[pin1:pin2] | OUT[pin1] | local_variable = expression ;

or

clocked_register[index] = expression ;

register	Combinational, edge triggered or level triggered register name.

output_port	Output port name

pin1, pin2	Output pin numbers. OUT[pin1:pin2] and OUT[pin1] allow outputs to be assigned with having to declare them in a PORT statement.

local_variable	Any name not already used for a port or register. This defines the value for a local variable that can be used in subsequent expressions. A local variable may not be used in an expression that precedes its definition.

expression	Local variables, input ports, registers and constant values combined using arithmetic, boolean, bitwise boolean, shift, conditional and relational operators. See below for detailed documentation on all operators.

clocked_register	Edge or level triggered register.

index	Array index. This must be smaller than the array size. Arrays are based at 0. That is the first element is zero and the last is (array length-1).

Expression operators

The following table lists all operators available. These are listed in order of precedence. Precedence determines the order of evaluation. For example in the expression:

var1<var2 && var3<var4

The sub-expressions var1<var2 and var3<var4 are evaluated first and the result of that those evaluations combined using && to yield the final result. This is because < has higher precedence than &&. The precedence can be altered using parentheses in the usual way.

Class	Operators	Description
Index	[]	E.g. var1[4]. Index operator to access array element.
Unary	+ -	Operator to single value e.g. -5
Arithmetic multiplicative	* / %	Arithmetic multiply/divide/modulus treating all values as unsigned integers. % returns remainder after division
Arithmetic additive	+ -	Arithmetic operation treating all values as unsigned integers
Shift	<<  >>	Shift-left and shift right. E.g. reg1 << 2 will shift reg1 left by two bits
Relational	< > <= >=	If condition met result is 1 (=TRUE) otherwise result is zero (=FALSE)
Equality	== <> !=	== means EQUAL <> and != both mean NOT EQUAL Return 1 when condition met and 0 when condition is not met
Bitwise AND	&	Performs a boolean AND bit by bit
Bitwise XOR	^	Performs a boolean exclusive OR bit by bit
Bitwise OR	|	Performs a boolean OR bit by bit
Logical AND	&&	Returns 1 if both values are non-zero (TRUE) otherwise returns zero (FALSE)
Logical OR	||	Returns 1 if either value is non-zero (TRUE) otherwise return zero (FALSE)
Conditional expression	cond ? res1 : res2	Returns res1 if cond is non-zero (TRUE) otherwise returns res2 Example A<B ? 16 : 0 returns 16 if A is less than B otherwise returns 0
Note that the operators and their precedence are a subset of those used in the 'C' programming language with the exception of <>.

Controlling Output Enables

An output can be set into a high impedance state using a modification to an output port variable. Use the suffix .EN after the output port or port identifier to signify that the result of the expression should control the output enable. E.g. the following is extracted from the 74XX244 definition:

PORT (DELAY=USER[0]) Output out[0:3] ;

Output.En = Out_En_Del ? 0 : 0xf ;

Examples

Y = !Enable ? A_Del != B_Del : 1 ;

If  Enable is 0 then Y will be the result of  A_Del != B_Del otherwise the result will be 1.

Shift = !Par_En_Del ? Par_Data_Del : (Shift<<1) | Ser_Data_Del ;

This describes the action of a parallel loadable shift register.

out[0]= !in[1]&!in[2] | in[1]&!in[2]&in[0] | !in[1]&in[2]&in[0]

An example of referencing inputs and outputs directly without needing PORT statements.


ALB def - Diagnostics: Trace file
Arbitrary logic block langauge definition -  Diagnostics: Trace file

ALB language definition overview

In order to debug models, a tracing facility is provided. If the .MODEL TRACE_FILE parameter or instance parameter of the same name is specified, a file will be created which lists the values of all internal registers at each time point.

The file will usually have a number of lines of the form:

Roll back to <time>

For example the following is an extract from an actual trace file

    5.00022e-05	2696	9	2696	0

    5.09397e-05	2696	9	2696	0

    5.09407e-05	2692	10	2692	0

Roll back to     5.08599e-05

    5.09397e-05	2696	9	2696	0

    5.09407e-05	2692	10	2692	0

    5.09657e-05	2692	10	2692	0

Roll-back occurs when an analog time step is rejected but the digital simulation has already advanced past the new analog time. In this case the digital simulator has to back-track events. This mechanism is central to the operation of the mixed-mode system and is explained in more detail in Mixed-mode Simulator - How it Works.


ALB def - Edge Triggered Register Declaration
Edge Triggered Register Declaration

Arbitrary logic block langauge definition -  Registers and variables

EDGE (	CLOCK=input_pin_spec
[, DELAY=reg_delay]
[, WIDTH=reg_width]
[, MINCLOCK=reg_minclock]
[, HOLD=reg_hold_time]
[, ASYNCDELAY=reg_asyncdelay]
[, BITWISE=0|1 ] ) name [[array_size]]
[ = initial_condition *[, initial_condition] ] ;

input_pin_spec	This specifies which input pin is the clock and must be of the form: IN[n] where n is a pin number. See Language definition - Ports for details on how pin numbers relate to netlist entries and symbol definitions.

reg_delay	Register delay in seconds. This is the delay between the clock rising edge and the register value changing. You can use engineering units in the normal way.
Default: REG_DELAY parameter in .MODEL control defines default value. This is turn has a default value of 1nS.

reg_width	Register width in bits. This has a maximum of 32.
Default: 32

reg_minclock	Minimum clock width. This must be less than or equal to reg_delay. The register value will not update if the clock width is less than this value.
Default: MIN_CLOCK parameter in .MODEL control defines default value. This in turn has a default value of 0.

reg_hold_time	Register hold time. This is the time that the input data (i.e. assignment value) must remain stable after the clock edge, for the new value to be accepted. If the BITWISE parameter is set to '1' (which it is by default) the hold time is applied on a bit by bit basis. That is any individual bit in the register that remains stable during the hold period will attain the new value even if other bits violate the hold time. If BITWISE is '0' then if a single bit violates the hold time, the whole register will remain unchanged even if some bits remain stable during the hold period. Setting BITWISE to '0' saves system memory which can be important for large arrays (i.e. RAMs).
Default:  HOLD_TIME parameter in .MODEL control defines default value. This in turn has a default of 0.

reg_asysncdelay	Time the register takes to acquire a value set by an asynchronous assignment. This must be less than or equal to reg_delay.
Default: reg_delay

BITWISE value	See reg_hold_time
Default:  '1' for single registers, '0' for arrays.

name	Register name.

array_size	If specified, the register is arranged as an addressable array of size array_size.
Default: 1

initial_condition	Value assigned to register when simulation starts.
Default: 0

Notes:

To implement register setup time, assign a value to reg_hold_time equal to the sum of the register setup and hold times then delay the input data by a period equal to the setup time.


ALB def - Ports
Arbitrary logic block langauge definition -  Ports

ALB language definition overview

?

Port statements define the inputs and outputs to the logic device. They are of the form

PORT ( DELAY=output_delay)  port_name OUT [ pin1| pin1:pin2 ]

or

PORT port_name IN|OUT [ pin1| pin1:pin2 ]

Ports define a label to a single pin or sequence of pins so that they can be treated as a single entity in the remainder of the logic definition. In the case of outputs they can optionally also define an output delay. (If this is not specified a default output delay defined in the devices .MODEL control is used).

port_name	Any name to reference the port. Must start with a letter or underscore and consist only of letters numbers and underscores. Names are not case sensitive.

pin1,pin2	Identifies pin or range of pins that port accesses. See below for more details.

output_delay	Output delay in seconds. When an output port is assigned a value, the actual output is updated after this delay has elapsed (+ any loading delay). You may use engineering units in the normal way. E.g. 10n is 10e-9.

Relationship between ports, netlist entry and symbol definition

The netlist entry for an arbitrary logic block is of the form:

Axxx [ input_node_list ] [ output_node_list ] model_name

The pin numbers in the port statements above, i.e. pin1 and pin2 are the positions within the input_node_list for input ports and output_node_list for output ports.

So if the netlist entry is:

A12 [ 1 2 3 4 ] [ A B C D ] ARB1

the port definition:

PORT  output OUT[0:3] ;

assigns the label output to the netlist pins A B C and D. If, for example, the value 7 is evaluated and assigned to output, pins A B and C would be set to a logic '1' and pin D would be set to a logic '0'. Pins 1 2 3 & 4 would be used for input ports in a similar way.

The netlist entry relates directly to a symbol definition for an arbitrary logic block. When defining a symbol to be used with an ALB you should observe the following rules

The first input pin's name and the first output pin's name should both be prefixed with a '['.

The last input pin's name and the last output pin's name should both be suffixed with a ']'.

Use Property/Pin|Edit Pin Order... to define the pin order with input pins first then output pins.

You should assign a MODEL property with the value 'A'.


ALB def - Registers and variables
Arbitrary logic block langauge definition -  Registers and variables

ALB language definition overview

Registers are the main working elements of the arbitrary logic block. There are four main types. These are:

Edge triggered. The value of these change on the rising edge of an assigned clock.

Level triggered. The value of these change when an assigned enable is at a logic '1' level.

Combinational. The value of these change after a specified delay.

Read-only. These are given a fixed value which cannot be changed. These would usually be arranged in indexable arrays to implement a read only memory.

Edge and level triggered registers may be arranged in indexable arrays. Level or edge triggered arrays form a read-write memory or RAM.

In addition to registers there are also local variables. These can be assigned a value that can later be used in a register assignment.

All registers must be declared. Local variables are declared by simply assigning a value to them.

Refer to the following topics for full syntax for the register declarations:

Edge Triggered Register Declaration

Level Triggered Register Declaration

Combinational Register Declaration

Read-only Register Declaration


ALB def - USER and DEVICE values
Arbitrary logic block langauge definition -  USER and DEVICE values

ALB language definition overview

Sometimes it is convenient to use the logic description to define the functionality of a block but have the timing and other specifications specified separately. This is achieved by USER and DEVICE values. USER values are specified in the .MODEL control while DEVICE values are specified on the device at the netlist or schematic level. The values are referenced in the logic definition in the form:

USER[index]

and

DEVICE[index]

These can replace any constant value in an expression, register qualifier or port qualifier. (Register and port qualifiers are the values in parentheses after the register/port keyword. E.g. DELAY, HOLD,  SETUP etc.).

To set USER values in a .MODEL control, assign the parameter USER. This is a vector parameter, that is it can have any number of values and these must be enclosed in square brackets '[' and ']'. For example:

.MODEL Counter8 d_logic_block file=counter_8.ldf user=[10n, 5n]

The logic definition to which this model refers - counter_8.ldf - can use USER[0] and USER[1] to refer to the values 10n and 5n respectively.

To set DEVICE values in a netlist, the netlist entry for the device must be appended with :

: USER=[ values ]

For example:

A$U3 [clock] [Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7] Counter8 : USER=[10n, 5n]

The logic definition for this device can use DEVICE[0] and DEVICE[1] to access the USER values in the netlist i.e. 10n and 5n respectively. Always remember to include the colon. This acts as a separator between the device name and any parameters.


Adding Model Libraries
Installing Model Libraries

Device Library and Parts Management - Overview

Easy-SPICE needs to know where to look for these library files. In the case of the libraries supplied the necessary mechanism will have already been set up and no further action is necessary.

The following is the full procedure for installing libraries that can be an any location on your system. There is an easier method with some limitations. See Installing model libraries the easy way

If the models are on diskette(s), copy the files to a suitable directory on a fixed or remote drive. If the files are arranged in different directories, they may stay that way. Easy-SPICE can handle any file structure.

Select the command shell menu File|Model Library|Add Libraries...

A dialog box will be displayed providing the means to select a directory. When you close this dialog box Easy-SPICE will search the directory you specify and recurse through all subdirectories below for files containing compatible models. You can specify the root of a whole disk if you wish but note that the searching operation will take several minutes if you do. Select the lowest level directory under which all models are known to reside. You must double click the directory you want.

After the searching operation is complete another dialog will be displayed:

The top window shows pathnames of model libraries that are currently installed. The lower window contains additional libraries that are available. Use the Add button to transfer files in the lower window to the top window. You may use the shift and control keys to make multiple selections in each window. If you wish to remove installed libraries, select them (from top window) the press the Remove

The up and down arrow buttons allow you to change the search order of the libraries. This can be important if the same model name appears in more than one library.


Algorithms used for curve measurements

Some of the measurements algorithms make some assumptions about the wave shape being analysed. These work well in most cases but are not "fool-proof". The following notes describe how the algorithms work and what their limitations are.

"/Cycle" and Frequency measurements

These measurements assume that the curve being analysed is repetitive and of a fixed frequency. The results may not be very meaningful if the waveform is of varying frequency or is of a "burst" nature. The "/cycle" measurements calculate over as many whole cycles as possible.

Each of these measurements use an algorithm to determine the location of x-axis crossings of the waveform. The algorithm is quite sophisticated and works very reliably. The bulk of this algorithm is concerned with finding an optimum base line to use for x-axis crossings.

The per cycle measurements are useful when the simulated span does not cover a whole number of cycles. Measurements such as RMS on a repetitive waveform only have a useful meaning if calculated over a whole number of cycles. If the simulated span does cover a whole number of cycles, then the "Full" version of the measurement will yield an accurate result.

Rise and fall time

These measurements have to determine the waveforms pulse peaks. A histogram method is used to do this. Flat areas of a waveform produce peaks on a histogram. The method is very reliable and is tolerant of a large number of typical pulse artefacts such as ringing and overshoot.For some wave-shapes, the pulse peaks are not well enough defined to give a reliable answer. In these cases the measurement will fail and an error will be reported.

Distortion

This calculates residue after the fundamental has been removed. It uses an FFT to calculate the result. This algorithm needs a reasonable number of cycles to obtain an accurate result. The frequency of the fundamental is displayed in the message window. Note that most frequency components between 0Hz and just before the second harmonic are excluded. The precision of the method can be tested by performing the measurement on a test circuit circuit such as:

The signal on the pos side of V2 has 0.1% distortion. Use V1 as your main test source (assuming you are testing an amplifier) then after the simulation is complete, check that the distortion measurement of V2 is 0.1%. If it is inaccurate, you will need either to increase the number of measurement cycles or reduce the maximum time step or both. You can adjust the amplitude of V2 appropriately if the required resolution is greater or less than 0.1%.

Note, that in general, accuracies of better than around 1% will require tightening of the simulation tolerance parameters. See the topic Convergence and Accuracy.

Frequency response calculations

These must find the passband for their calculations. Like rise and fall a histogram approach is used to find its approximate range and magnitude. Further processing is performed to find its exact magnitude.

Note that the algorithms allow a certain amount of ripple in the passband which will work in most cases but will fail if this in excess of about 3dB.

Note that the frequency response measurements are general purpose and are required to account for a wide variety of responses including those with both high and low pass elements as well as responses with band pass ripple. This requirement compromises accuracy in simpler cases. So, for example, to calculate the -3dB point of a low pass response that extends to DC, the 0dB point is taken to be a point midway between the start frequency and the frequency at which roll-off starts. A better location would be the start frequency but this would be inaccurate if there was a high pass roll off at low frequencies. Taking the middle point is a compromise which produces good - but not necessarily perfect - results in a wide range of cases. To increase accuracy in the case described above, start the analysis at a lower frequency, this will lower the frequency at which the 0dB reference is taken.


Analog Behavioural Modelling
Functional Modelling

Functional modelling is the activity of defining a device in terms of its function or behaviour rather than specifying a device part number for which a model exists. Functional modelling has a number of uses. Here are two examples

System level simulation. You are investigating the viability or characteristics of a complete system before actually considering its implementation detail. Your system may consist of a number of interconnected blocks each with an easily defined function.

Device model implementation. Functional models can be used to actually create device models. Suppose you wish to use an op-amp for which no model is available. The only characteristic that affects the performance of your circuit is its gain bandwidth product. So instead of creating a detailed model you simply use a differential voltage amplifier with the appropriate GBW.

The simulator provides three devices that can be defined in a completely arbitrary manner. These are:

Arbitrary non-linear source or "B" device	Analog non-linear device. Can express single voltage or current in terms of any number of circuit voltages and currents including its own output.

S-domain Transfer Function Block	Linear block with single input and output each of which may be single ended or differential, voltage or current. Specified in terms of its S-domain or Laplace transfer function.

Arbitrary Logic Block	Digital device. Implements any digital device, combinational, synchronous or asynchronous using a descriptive language.

In addition, the simulator also provides a generic digital-analog converter and a generic analog-digital converter for converting between the analog and digital domains.


Analog to digital interfaces

Digital simulation overview

Analog to Digital Interfaces

At the simulator level, there are two types of node namely analog and digital and they cannot be connected together. At the netlist level it is possible to connect analog components to digital outputs and inputs. When Easy-SPICE sees an analog component connected to a digital signal, it automatically interconnects them using an interface bridge. It will use an analog-digital bridge to connect an analog signal to a digital input and a digital-analog bridge to connect to a digital output. If you connect an analog component to a signal which connects to both digital inputs and outputs both types of bridge will be used and the digital inputs and outputs will be separated from each other as illustrated in the following diagrams.

Circuit entered in schematic editor

Circuit that is actually simulated

One problem with the above approach is that the A-D and D-A bridges introduce an additional delay to the signal path which would therefore alter the performance of the digital system even if the analog node does not present any significant load. This is overcome by assigning a negative load to the input of  the digital bridge which in effect reduces the delay of the driving gate. In the above example U2 has a negative input load which reduces the delay of U3.

How A-D Bridges are Selected

When Easy-SPICE implicitly places an AD bridge in a circuit, it must choose an appropriate model for the bridge. All AD bridges are based on DAC_BRDIGE and ADC_BRIDGE models. The model is chosen according to the "FAMILY" parameter assigned to the digital device to which the bridge is connected. Full information can be found in the logic families topic. Basically the FAMILY parameter specifies the logic family to which the device belongs e.g. "HC" for high speed CMOS.

The name of the model used to interconnect digital to analog is always of the form:

family_name_dac

and to interconnect analog to digital

family_name_adc

For example if the family name is "HC" the D-A bridge is called HC_DAC. There is a selection of A-D and D-A bridges in the model library supplied with Easy-SPICE. (In BRIDGES.LB).


Analog-Digital Interface Bridge

Netlist entry:

Axxxx in out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	inout	g	g	n/a
out	Output	out	d	d	n/a
Model format:

.MODEL model_name adc_bridge parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
in_low	Maximum 0-valued analog input	real	0.1	none	No	n/a
in_high	Minimum 1-valued analog input	real	0.9	none	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
time_tol	Threshold time tolerance	real	1.00E-10	1e-12 - INF	No	n/a
out_low	Used to calculate reflected static load. See text	real	0	none	No	n/a
out_high	Used to calculate reflected static load. See text	real	5	none	No	n/a
clamp_low	Clamp threshold 'ZERO' digital input. Default to out_low	real	out_low	none	No	n/a
clamp_high	Clamp threshold 'ONE' digital input. Default to out_high	real	out_high	none	No	n/a
clamp_res	Clamp min resistance	real	1	1e-06 - INF	No	n/a
clamp_bias	Clamp voltage	real	0.8	0.2 - 2	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
Device Operation

The analog-digital interface bridge is the main device used to connect analog signals to digital inputs. The device produces a digital signal that is in the logic '1' state when the analog input is above the high threshold (IN_HIGH) and a logic '0' state when it is below the low threshold (IN_LOW). When the analog input is in between these two states the output will be in the UNKNOWN state. The changes in state will be delayed according to the RISE_DELAY and FALL_DELAY parameters.

Analog input load

The analog input presents a load to its driving circuit according to the digital load that is being driven. In other words the digital load is reflected to the analog input. Both static (i.e. DC) and dynamic (i.e. capacitance) elements of the load are reflected. To accurately reflect the sink and source currents, the interface bridge needs to know the voltage levels of the device it is driving. The digital device will (usually) have a SINK_CURRENT and a SOURCE_CURRENT model parameter each of which apply at defined logic voltage levels. These levels must be specified in the OUT_LOW and OUT_HIGH parameters of the AD interface bridge model. The input is modelled by a current source in parallel with a resistor. The values of these components are calculated from the above mentioned parameters and the digital load.

Input clamp

The analog input is clamped at the voltages specified by CLAMP_LOW and CLAMP_HIGH. The clamping device has a characteristic similar but not identical to a junction diode in series with a resistance. Basically it has the characteristic of a diode up to a voltage excess of CLAMP_BIAS after which it becomes resistive with a dynamic resistance of CLAMP_RES. The diode characteristics are calculated so that the transition between the two regions is smooth.

Time Step Control - TIME_TOL parameter

Consider the following circuit and waveform

The graph shows  the input and output of the NAND gate. Because the input is analog an implicit AD interface bridge will have been connected by the simulator. In the above example the parameters for this bridge have been set to:

.model HC_adc adc_bridge

+ in_low=2.1

+ in_high=2.2

+ rise_delay=1e-12

+ fall_delay=1e-12

+ out_family = "HC"

+ out_low = 0

+ out_high = 5

+ clamp_bias=0.5

+ clamp_res=10

+ time_tol=10u

The last parameter, TIME_TOL has been deliberately set ridiculously high to demonstrate what happens without time step control on the input. The input thresholds of the HC gate are 2.1 and 2.2 volts yet the output in the above example doesn't switch until the input has reached 0V. Because there is little activity in the analog circuit, the time steps are quite large. In fact in the above example the transient timepoints are at 55uS, 55.04uS, 56.2uS, 57.8uS and 60uS. The timepoint at 57.8u is just before the 2.2 volt threshold is reached and it isn't until the next time point, 2.2uS later that the lower threshold is broken. The result is the location of the negative edge at the output is delayed by approx. 2.2uS from where it should be. The problem is that the analog system knows nothing of what is happening in the digital domain so carries on with large timesteps oblivious to the errors in the digital system.

To overcome this problem. Easy-SPICE features a mechanism (not in the original XSPICE system) that detects that the threshold has been passed and cuts back the time step to ensure that the digital edge occurs at an accurate point. The accuracy of this mechanism is controlled by the TIME_TOL parameter. The smaller this parameter, the more accurately the exact threshold will be hit at the expense of short time steps and longer simulation runs. TIME_TOL defaults to 100pS and in most applications this is a good choice. The following shows the result when TIME_TOL is set to the default.

Here you can see the edge at the correct time.

The effect of not correctly simulating the threshold point has serious consequences when attempting to simulate relaxation oscillators constructed with digital inverters as the following graphs illustrate:

The top trace is without threshold control and the bottom trace is with it.


Analog-Digital Schmitt Trigger

Netlist entry:

Axxxx in out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	inout	g	g	n/a
out	Output	out	d	d	n/a
Model format:

.MODEL model_name adc_schmitt parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
in_low	Maximum 0-valued analog input	real	0.1	none	No	n/a
in_high	Minimum 1-valued analog input	real	0.9	none	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
time_tol	Threshold time tolerance	real	1.00E-10	1e-12 - INF	No	n/a
out_low	Analog output for 'ZERO' digital input	real	0	none	No	n/a
out_high	Analog output for 'ONE' digital input	real	5	none	No	n/a
clamp_res	Clamp min resistance	real	1	1e-06 - INF	No	n/a
clamp_bias	Clamp voltage	real	0.8	0.2 - 2	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
Device Operation

This device is basically identical to the Analog-Digital Interface Bridge. The only difference is the behaviour of the device when the analog input lies between the threshold voltages. With the interface bridge, the output is UNKNOWN under these circumstances but with this Schmitt Trigger, the output retains its previous value and so is always in a known state. In summary, the output will only switch from low to high when the input exceeds the higher threshold (IN_HIGH) and will only switch from high to low when the input descends below the lower threshold (IN_LOW).


And Gate

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	2 - no upper bound
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_and parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device operation

If the model parameter OPEN_C is false, The output will be at logic '0' if either input is at logic '0'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '1'.

If the model parameter OPEN_C is true the device will be open collector.  In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '0' the output strength will be STRONG. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state.


Arb Source Netlist entry
Voltage source

BXXXX N+ N- V=EXPRESSION

Current source

BXXXX N+ N- I=EXPRESSION


Arbitary Source Examples
Arbitrary Source Examples

Example 1 - Voltage Multiplier

The expression for an arbitrary source must refer to other voltages and/or currents on the schematic or in the netlist. Currents are referenced to voltage sources and voltages to netnames. Netnames are usually assigned by the schematic editor. Refer to the schematic editor's documentation for information on how to assign user names to nets.

An example is shown below. The junction R4/R1 and R1/R3 have been explicitly named n1 and n2.

In the above circuit the voltage across B1 will be equal to the product of the voltages at nodes n1 and n2.

An alternative approach is to define the arbitrary source within a subcircuit. E.g.

.subckt MULT out in1 in2

B1 out 0 V=V(in1)*V(in2)

.ends

This sub-circuit definition could be placed in a separate file and referenced with a .lib control, .inc control or installed as a global library part. The multiplier subcircuit can now be placed on the schematic using a user defined symbol The above circuit becomes:

Example 2 - Voltage comparator

B3 q3_b 0 V=atan(V(n1,n2)*1000)

This can also be added to the schematic in the same way as for the multiplier described above.

Example 3 - Ideal Power Converter

This examples also demonstrates the use of expressions within subcircuits. (See Using expressions for circuits parameters)

The following subcircuit implements an idealised power converter with an efficiency of eff and whose output voltage is proportional to the input voltage (vinn,vinp) multiplied by the control voltage (vcp,vcn). It is intended to simulate the voltage/current characteristics of a switching power converter.

.subckt powerconv voutp voutn vinp vinn vcp vcn

biin1 	vinp 	vinn	i=-v(voutp,voutn)/v(vinp,vinn)*i(vout1)/{eff}

vout1	bmult1_n	voutn	0

bmult1	voutp	bmult1_n	v=v(vinp,vinn)*v(vcp,vcn)

r1	vcp	vcn	1meg

.ends


Arbitrary Source Look-up Tables

Easy-SPICE arbitrary source expressions may contain any number of look-up tables. This allows a transfer function of a device to specified according to - say - measured values without having to obtain a mathematical equation. Look-up tables are specified in terms of x, y value pairs which describe a piece-wise linear transfer function.

Example

The following circuit implements a soft limiting function

The look up table is defined as:

V=table[-10, -5, -5, -4, -4, -3.5, -3, -3, 3, 3, 4, 3.5, 5, 4, 10, 5](v(N1))

and has the following transfer function:

Note that the values inside the square brackets must be constants.


Arbitrary logic block

Digital simulation overview

The arbitrary logic block is an internal component that can be defined to perform any logic function. Using a simple descriptive language it is possible to define combinational logic elements, synchronous and asynchronous registers as well as look-up table (ROMs) and arrays (RAMs).

Each ALB device is defined as a normal .MODEL control which refers to a separate file containing the logic description.

Refer to the following topics for a full description of this device

Example 1 - A simple counter

Example 2 - A multiplier

Example 3 - A ROM lookup table

Example 4 - D-type flip-flop

Netlist entry and .MODEL parameters

Language definition


Arbitrary source

Examples	Netlist Entry

Netlist Entry

Voltage source

BXXXX N+ N- V=EXPRESSION

Current source

BXXXX N+ N- I=EXPRESSION

An arbitrary source is a voltage or current source whose output can be expressed as an arbitrary relationship to other circuit voltages or currents.

EXPRESSION	Algebraic expression describing voltage or current output in terms of circuit nodes or sources.

Circuit voltages are expressed in the form:
V( nodename ) voltage at nodename referred to ground
V( nodename1, nodename2 ) voltage at nodename1-nodename2

Currents must be sensed with a voltage source as follows:
I( voltagesourcename )

The expression may contain the algebraic operators:
+ - * / ^ ( )

and the functions:
acos() asin() atan() cos() cosh() exp() ln() log() sin() sinh() sqrt() tan() which are self-explanatory

and

abs() returns magnitude i.e. always positive
atan2(x, y) = atan(x/y) (y=0 is legal)
limit(x, l, h)  result = l if x<l, result = h if x>h else result = x
max(x, y) result = x if x>y else result = y
min(x, y) result = x if x<y else result = y
pwr(x, y) result = abs(x)y
pwrs(x, y) result = xy if x>0 else result = -(-x)y
sgn() returns 1 if arg>0, -1 if arg<0, 0 if arg=0
u() returns 1 if arg>0, 0 if arg<0, 0.5 if arg=0
uramp() return 0 if arg<0 arg if arg>0

and
look up tables of the form:
table[x1, y1, x2, y2, x3, y3, .... xn, yn](expression)

See Arbitrary Source Look-up Tables

The expression may also refer to any parameters defined by .PARAM and also the two special parameters TIME and TEMP. TIME is the analysis time for a transient simulation and zero for any other analysis mode. TEMP is the temperature in °C

BXXXX	Component reference

N+	Positive output node.

N-	Negative output node.

The small-signal AC behaviour of the non-linear source is a linear dependent source with a proportionality constant equal to the derivative (or derivatives) of the source at the DC operating point.

If the argument of log, ln or sqrt becomes negative, the absolute value of the argument is used. If a divisor or argument of log or ln becomes zero an error will result. In general, care should be exercised in the use of ln, log, sqrt and division. Even if the circuit being simulated would not normally exercise these functions with their undefined values, the simulator may do so in the attempt to converge to a solution.

If the source is a current, the direction of flow is into the positive node (OUTPOS).

To use circuit voltages in the expression it is necessary to explicitly refer to nodenames. These are normally allocated by the schematic editor but may be overridden with user defined labels. Refer to the schematic editor's documentation.


AutoAxis
"AutoAxis"

Multiple Y-axis overview

When you plot a new curve on an existing graph, Easy-SPICE will select - or if necessary create - a compatible axis for that curve. The decision is made on the basis of the curves Units i.e Voltage, Current etc. The rules it follows are:

If the currently selected axis or grid (shown by black axis line) has the same units as curve to be plotted or if it has undefined units (designated by a '?' on label), that axis will be used.

If any other axis or grid has compatible units (i.e same as curve or undefined) that axis will be used.

If no axes exist with compatible units, a new axis (not grid) will be created to accommodate the curve.

The above works for all plots made via the menu system. For plots created using the "Curve" command at the command line, the "AutoAxis" switch must be specified e.g "Curve /AutoAxis L3#P"


Axis Labels Sheet

Plotting arbitrary expressions

This sheet has four edit boxes allowing you to specify, x and y axis labels as well as their units. If any box is left blank, a default value will be used or will remain unchanged if the axis already has a defined label.


Axis Scales Sheet

Plotting arbitrary expressions

Allows you to specify limits for x and y axes.

X-Axis/Y-Axis

Lin/Log/Auto	Specify whether you want X-Axis to be linear or logarithmic. If "Auto" is selected, the axis (X or Y) will be set to log if the x values are logarithmically spaced. For the Y-axis it is also necessary that the curve values are positive for a log axis to be selected.

Note that the log/lin setting will have no effect when adding a curve to an existing graph.

No Change	Keep axis scales how they are. Only relevant if adding to an existing graph.

Auto scale	Set axis scales to fit curve limits.

Defined	Set axis to scales defined in Min and Max boxes


Axis/Graph Options Sheet

Plotting arbitrary expressions

Allows you to control where the curve for the probed signal will be placed.

Axis Type

Auto select	If adding a curve to an existing graph, the curve will use the currently selected y-axis provided that it has compatible units (volts, amps etc). If the units are incompatible and another axis or grid within the same graph sheet does have compatible units, that axis will be used. Otherwise a new y-axis will be created. Note that you can move a curve to a new axis or grid after it has been plotted.

Use Selected	Use currently selected y-axis

Use New Y-axis	Create a new y-axis alongside main one

Use New Grid	Create a new grid stacked on top of main axis

Digital Axis	Create a new digital axis. Digital axes are placed at the top of the window and are stacked. Each one may only take a single curve. As their name suggests, they are intended for digital traces but can be used for analog signals if required.

Graph Options

Add To Selected	Add curve to currently selected and displayed graph sheet

New Graph Sheet	Create a new graph sheet within current graph window

New Graph Window	Create a new graph window.


BJT Netlist Entry
Qxxxx collector base emitter [substrate] modelname [area] [OFF] [IC=vbe,vce] [TEMP=local_temp]

collector	Collector node name

base	Base node name

emitter	Emitter node name

substrate	Substrate node name


BJT param Notes
The bipolar junction transistor model in SPICE is an adaptation of the integral charge control model of Gummel and Poon.

This modified Gummel-Poon model extends the original model to include several effects at high bias levels. The model will automatically simplify to the simpler Ebers-Moll model when certain parameters are not specified.

The dc model is defined by the parameters IS, BF, NF, ISE, IKF, and NE which determine the forward current gain characteristics, IS, BR, NR, ISC, IKR, and NC which determine the reverse current gain characteristics, and VAF and VAR which determine the output conductance for forward and reverse regions. Three ohmic resistances RB, RC, and RE are included, where RB can be high current dependent. Base charge storage is modeled by forward and reverse transit times, TF and TR, the forward transit time TF being bias dependent if desired, and nonlinear depletion layer capacitances which are determined by CJE, VJE, and MJE for the B-E junction , CJC, VJC, and MJC for the B-C junction and CJS, VJS, and MJS for the C-S (Collector-Substrate) junction. The temperature dependence of the saturation current, IS, is determined by the energy-gap, EG, and the saturation current temperature exponent, XTI. Additionally base current temperature dependence is modeled by the beta temperature exponent XTB in the new model.


Bipolar junction transistor

Model parameters	Examples	Netlist Entry

Netlist Entry

Qxxxx collector base emitter [substrate] modelname [area] [OFF] [IC=vbe,vce] [TEMP=local_temp]

collector	Collector node name

base	Base node name

emitter	Emitter node name

substrate	Substrate node name

modelname	Name of model, see Device Library and Parts Management. Must begin with a letter but can contain any character except whitespace and ' . ' . Models with names OFF, IC or TEMP should not be used for four terminal devices. (This restriction is a consequence of the optional substrate node.)

area	Area multiplying factor. Area scales up the device. E.g an area of 3 would make the device behave like 3 transistors in parallel. Default is 1.

OFF	Forces the device to be initially off. The affects the initial guess prior to commencing the DC operating point analysis and is useful to force a particular state for a bistable circuit. See .nodeset for more information.

vbe,vce	Initial conditions for base-emitter and collector-emitter junctions respectively. These only have an effect if the UIC parameter is specified on the .tran control.

local_temp	Local temperature. Overrides specification in .options or .temp control.


Bjt Model parameters
BJT Model Parameters:

Notes

Model syntax:

NPN:

.model modelname NPN ( parameters )

PNP:

.model modelname PNP ( parameters )

Parameters:

The symbols ' × ' and ' ÷ ' in the Area column means that that parameter should be multiplied or divided by the area factor respectively.

Name	Description	Units	Default	Area

IS	Transport saturation current	A	1e-16	×

BF	Ideal maximum forward beta	100

NF	Forward current emission coefficient	1.0

VAF	Forward Early voltage	V	∞

IKF	Corner for forward beta high current
roll-off	A	∞	×

ISE	B-E leakage saturation current	A	0	×

NE	B-E leakage emission coefficient	1.5

BR	Ideal maximum reverse beta	1

NR	Reverse current emission coefficient	1

VAR	Reverse Early voltage	V	∞

IKR	Corner for reverse beta high current
roll-off	A	∞	×

ISC	B-C leakage saturation current	A	0	×

NC	B-C leakage emission coefficient	2

RB	Zero bias base resistance	Ω	0	÷

IRB	Current at which base resistance
falls halfway to its minimum value	A	∞	×

RBM	Minimum base resistance at high
currents	Ω	RB	÷

RE	Emitter resistance	Ω	0	÷

RC	Collector resistance	Ω	0	÷

CJE	B-E zero-bias depletion capacitance	F	0	×

VJE	B-E built in potential	V	0.75

MJE	B-E junction exponential factor	0.33

TF	Ideal forward transit time	Sec.	0

XTF	Coefficient for bias dependence of TF	0

VTF	Voltage describing VBC
dependence of TF	V	∞

ITF	High-current parameter for effect on TF	A	0	×

PTF	Excess phase at freq=1.0/(TF×2π) Hz	degree	0

CJC	B-C zero-bias depletion capacitance	F	0	×

VJC	B-C built-in potential	V	0.75

MJC	B-C junction exponential factor	0.33

XCJC	Fraction of B-C depletion capacitance
connected to internal base node	1

TR	Ideal reverse transit time	Sec.	0

CJS	Zero-bias collector substrate
capacitance	F	0	×

VJS	Substrate junction built-in potential	V	0.75

MJS	Substrate junction exponential factor	0

XTB	Forward and reverse beta temperature
exponent	0

EG	Energy gap	eV	1.11

XTI	Temperature exponent for effect on IS	3

KF	Flicker noise coefficient	0

AF	Flicker noise exponent	1

FC	Coefficient for forward-bias depletion
capacitance formula	0.5


Buffer

Netlist entry:

Axxxx in out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	n/a
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_buffer parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
stored_delay	Stored delay (overrides rise_delay and fall_delay)	real	0	0 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
open_e	Open emitter output	boolean	FALSE	none	No	n/a
Device Operation

This device is a simple buffer with a single input and output. It can optionally be specified to have an open collector (open_c parameter) or open emitter (open_e parameter) output. Further, if the stored_delay parameter is specified, the device will act as a pure delay. This means that it will pass pulses that are shorter than the delay time whereas normally (delay specified by rise_delay and fall_delay) such pulse would be swallowed.

The following table describes the device operation in detail

OPEN_C parameter	OPEN_E parameter	Input	Output state	Output strength
FALSE	FALSE	0	0	STRONG
FALSE	FALSE	1	1	STRONG
FALSE	FALSE	UNKNOWN	UNKNOWN	STRONG
FALSE	TRUE	0	0	HI-IMPEDANCE
FALSE	TRUE	1	1	STRONG
FALSE	TRUE	UNKNOWN	UNKNOWN	UNDETERMINED
TRUE	FALSE	0	0	STRONG
TRUE	FALSE	1	0	HI-IMPEDANCE
TRUE	FALSE	UNKNOWN	0	UNDETERMINED
TRUE	TRUE	0	1	HI-IMPEDANCE
TRUE	TRUE	1	0	HI-IMPEDANCE
TRUE	TRUE	UNKNOWN	UNKNOWN	UNDETERMINED

Note the difference between open emitter and open collector operation. These modes have been designed to be as close to as possible to real devices, in particular their behaviour into an open circuit. An open emitter output, when switching from high to low is likely to follow the voltage on the device's base due to the base-emitter capacitance so the output state follows the input state. An open collector (or open drain) output on the other hand will remain in the low state when its input switches


CCCS Example
Example:

In the above circuit, the current in the output of F1 (flowing from top to bottom) will be 0.1 times the current in R2.


CCVS Example
Example:

In the above circuit at the output of H1 is 1000 times the current in R2.


Calling a sub-circuit from a netlist

Overview

To call a subcircuit from a netlist, the line must be of the form:

Xxxxx nodelist sub_circuitname [: parameters]

Each node in nodelist will connect to its corresponding node in the sub-circuit's definition.

parameters is a list of parameter names and their values which may be referenced in the subcircuit definition. Sub-circuit parameters are explained in Using expressions for circuit parameters.


Capacitor

Model Parameters	Examples

Netlist Entry

Cxxxx N1 N2 [model_name] value [IC=initial_condition] [TEMP=local_temp] [TC1=tc1] [TC2=tc2] [VC1=vc1] [VC2=vc2]

N1	Node 1

N2	Node 2

model_name	(Optional) Name of model, see Device Library and Parts Management. Must begin with a letter but can contain any character except whitespace and ' . '

value	Capacitance (Farads)

initial_condition	Initial voltage if UIC specified on .tran control.

local_temp	Capacitor temperature (°C)

tc1	First order temperature coefficient

tc2	Second order temperature coefficient

vc1	First order voltage coefficient

vc2	Second order voltage coefficient


Capacitor Examples popup

C1 has a capacitance of 1 nano farad.

C2's characteristics are determined by the model X7R with a nominal capacitance 1 nano farad.

C3 has a capacitance of 100p at 27°C and a temperature coefficient of 1e-4 (=100ppm/°C).


Capacitor Model Parameters

Notes

Model syntax:

.model modelname CAP ( parameters )

Parameters:

Name	Description	Units	Default

C	Capacitor multiplier	1

TC1	First order temperature coefficient	1/°C	0

TC2	Second order temperature coefficient	1/°C^2	0

VC1	First order voltage coefficient	Volt^-1	0

VC2	Second order voltage coefficient	Volt^-2	0


Capacitor param Notes
The capacitor model is optional as all parameters can be specified as part of the device in which case they override parameters specified in the model.

Capacitor models are most useful for specifying dielectric characteristics.


Capacitor with voltage initial condition

Netlist entry:

Axxxx cap_p cap_n model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
cap	Capacitor terminals	inout	hd	hd	n/a
Model format:

.MODEL model_name cm_cap parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
c	Capacitance	real	none	1E-21 - INF	No	n/a
ic	Voltage initial condition	real	0	none	No	n/a
Description

This is like a standard capacitor but the internal implementation is different and permits the specification of an initial condition which works without having to specify the transient UIC switch. Also, unlike normal initial conditions, the initial voltage is applied with a zero source resistance.

In some circumstances, large value capacitors are better implemented using this device than the standard capacitor but note that during the DC operating point solution, the device looks like a short circuit, not an open circuit as is the case with the normal SPICE device.


Circuit Definition - Overview

There are two basic methods of defining a circuit to be simulated. For most the preferred method is to use a schematic editor. The second method is to enter a netlist directly. Such a netlist may be created manually or perhaps by another tool that generates a SPICE compatible netlist.

Refer to the schematic editor's documentation for information on schematic entry.

For direct netlist entry see Direct netlist entry

Notes:

Be sure to observe the simulator's Circuit rules


Circuit Rules

The following design rules must be observed for the simulation to run correctly. Note that most circuits obey them anyway and they do not impose serious limitations on the capability of the simulator.

•	There must always be at least one ground symbol on every circuit.

•	Every node on the circuit must have a dc path to ground. If you do have a floating node, connect a high value resistor (e.g. 1G ) between it and ground.

•	There must not be any zero resistance loops constructed from voltage sources and or inductors. If you do have such loops. insert a low value resistor. It is best to make the resistance as low as is needed to have a negligible effect on your circuit but no lower.

•	There should be at least two connections at every node.

Failure to observe the above usually leads to a Singular Matrix error.


Colours and Fonts

Colours

Colours for graph curves and graph grids may be customised using the colour dialog box. This is opened using the File|Options|Colour menu item.

Select the object whose colour you wish to change then select Edit button to change it.

Fonts

Fonts for various components of Easy-SPICE may be selected using the font selection dialog box. This is opened using the File|Options|Font... menu item.

Select the item whose font you wish to change the press Edit to select new font. Items available are:

Print Caption	Font used at base of printed graph
Graph	Graph windows
Command Line	Command line at top of command shell
Message Window	Bottom part of command shell


Command ref Notation
Command Reference Notation

Symbols used:

Square brackets: [ ]

These signify a command line parameter or switch which is optional.

Pipe symbol: |

This signifies either/or.

Ellipsis: ...

This signifies one or more entries.

Fonts:

Anything that would be typed in is displayed in courier font.

Command line parameters are in italics.

Case:

Although upper and lower cases are used for the descriptions of commands, they are NOT in fact case sensitive.

Examples:

OpenGroup [ /text ] [ filename ]

Both /text (a switch) and filename (a parameter) are optional in the above example.

So the following are all legitimate:

OpenGroup

OpenGroup /text

OpenGroup run23.dat

OpenGroup /text output.txt

DelCrv curve_number ...

1 or more curve_number parameters may be given.

So the following are all legitimate:

DelCrv 1 2 3

DelCrv 1


Controlled Digital Oscillator

Netlist entry:

Axxxx cntl_in out model_name : parameters

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
cntl_in	Control input	in	v	v, vd, i, id	n/a
out	Output	out	d	d	n/a
Instance Parameters

Name	Description	Type	Array?
init_phase	Initial phase	real	No
Model format:

.MODEL model_name d_osc parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
cntl_array	Control array	real	0	none	Yes	2 - INF
freq_array	Frequency array	real	1.00E+06	0 - INF	Yes	2 - INF
duty_cycle	Output duty cycle	real	0.5	1e-06 - 0.999999	No	n/a
init_phase	Initial phase of output	real	0	-180 - +360	No	n/a
rise_delay	Rise delay	real	1.00E-09	0 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	0 - INF	No	n/a
phase_tol	Phase tolerance/degrees	real	10	0 - 45	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
Device Operation

This device produces an output frequency controlled by an analog input signal following an arbitrary piece-wise linear law. The input to output frequency characteristic is defined by two parameters CNTL_ARRAY and FREQ_ARRAY. The following is an example of a .MODEL control:

.model vco d_osc

+ cntl_array=[-1,0,1,2,3,4,5]

+ freq_array=[0,10000,40000,90000,160000,250000,360000]

The frequency characteristic described by the above example follows a square law. The two arrays CNTL_ARRAY and FREQ_ARRAY must be the same length. These define the frequency output for a given analog input.

Time Step Control

In order to control the accuracy of the phase of the output signal, this model may cut back the analog time step. At each analog time point, the required frequency is calculated and the digital output is set at that frequency. If the analog input changes by too large an amount between time points, the digital output phase could be substantially in error as the frequency is constant between analog time points. The actual error is calculated and if this exceeds PHASE_TOL, the time point is rejected and a time point at which the error will be in tolerance is estimated.

Note: This model was included with the original XSPICE code but the Easy-SPICE version has been completely re-written. The original did not have any phase error control and could not give accurate results unless the analog time step was artificially kept small.


Convergence and accuracy issues

Please refer to the user manual for information on this subject.


Creating a sub-circuit manually

Overview

You can create a subcircuit manually using a text editor. Subcircuits consist of normal netlist device lines with - if applicable - any models enclosed with .SUBCKT and .ENDS lines. For example, the following is a fragment of an opamp definition:

.subckt SXOA1000 INP INN OUT VSP VSN

I2 D2_N VSN 100u

I1 Q3_E VSN 100u

C1 OUT R1_P 10p

...

...

.ends

.SUBCKT line is of the form

.SUBCKT subcircuit_name nodelist [params: default_parameter_list]

subcircuit_name is the name of the subcircuit and is used to reference it in the main netlist. nodelist may be any number of node names and are used for external connections. The subcircuit call (using an "X" device) would use a matching number of nodes in the same order.

default_parameter_list is a list of sub-circuit parameters and their default values.


Current Source Examples
Examples:

In the above circuit:

I3 has a fixed DC value of 1mA

I2 has a DC value of 0 and an AC analysis magnitude of 10mA

I1 gives a pulsed current from -1mA to 1mA with rise and fall times of 100nS, a duration of 4.9μS and a period of 10μS. AC analysis magnitude is 10mA. Value for dc operating point will be -1mA (pulse value at t=0).


Current controlled current source

Example

Netlist Entry

Current controlled current sources actually require two lines in the netlist. One for the source itself and the other for a voltage source through which the controlling current flows.

The netlist format for a linear source is:

Fxxxx NOUT+ NOUT- VC current_gain

NOUT+	Positive output node

NOUT-	Negative output node

VC	Controlling voltage source

current_gain	Output current/Input current

SPICE2 polynomial sources are also supported in order to maintain compatibility with commercially available libraries for IC's. (Most Op-amp models for example use several polynomial sources). In general, however the arbitrary source is more flexible and easier to use.

The netlist format for a polynomial source is:

Fxxxx NOUT+ NOUT- poly( num_inputs ) VC1 VC2 ... polynomial_specification

VC1, VC2	Controlling voltage sources

num_inputs	Number of controlling currents for source.

Current flows from the positive node through the source to the negative node.


Current controlled voltage source

Example

Netlist Entry

Current controlled voltage sources actually require two lines in the netlist. One for the source itself and the other for a voltage source through which the controlling current flows.

The netlist format for a linear source is:

Hxxxx NOUT+ NOUT- VC current_gain

NOUT+	Positive output node

NOUT-	Negative output node

VC	Controlling voltage source

current_gain	Output current/Input current

SPICE2 polynomial sources are also supported in order to maintain compatibility with commercially available libraries for IC's. (Most Op-amp models for example use several polynomial sources). In general, however the arbitrary source is more flexible and easier to use.

The netlist format for a polynomial source is:

Hxxxx NOUT+ NOUT- poly( num_inputs ) VC1 VC2 ... polynomial_specification

VC1, VC2	Controlling voltage sources

num_inputs	Number of controlling currents for source.


Current source

Examples

Netlist Entry

Ixxxx N+ N- [DC dcvalue] [AC magnitude [phase]] [transient_spec]

N+	Positive node

N-	Negative node

dcvalue	Value of source for dc operating point analysis

magnitude	AC magnitude for AC sweep analysis.

phase	phase for AC sweep analysis

transient_spec	Specification for time varying source. Can be one of following:

Pulse
Piece wise linear
Sine
Exponential
Single frequency FM
PWL File
Noise


Curve Measurements

Graphs and Probes

A number of measurements can be applied to selected curves. The results of these measurements are displayed below the curve legend and are also printed. Some of these measurements can be selected from the tool bar and more can be found in the Legend Panel pop-up menu.The remainder are listed in a tree structured list that is opened with the legend panel menu More Functions... or by pressing F3.

In general to perform a measurement, select the curve or curves then select measurement from tool bar or legend panel popup menu.

Curve measurement functions

Algorithms used for curve measurements


Curve measurement functions

Curve measurement overview

The following table list all the measurements available and how they may be accessed:

Transient measurements:	Access from	Description
RMS/Full	menu - RMS menu - More Functions...	RMS for full span
RMS/Per Cycle	Toolbar menu - RMS/cycle menu - More Functions...	RMS for each cycle
RMS/Cursor span	menu - More Functions...	RMS over span defined by cursor positions
RMS - AC coupled/Full	menu - More Functions...	RMS of AC component only for full span
RMS - AC coupled/Per Cycle	menu - More Functions...	RMS of AC component only for each cycle
RMS - AC coupled/Cursor span	menu - More Functions...	RMS of AC component only over span defined by cursor positions
Mean/Full	menu - Mean menu - More Functions...	Mean for full span
Mean/Per Cycle	Toolbar menu - Mean/cycle menu - More Functions...	Mean for each cycle
Mean/Cursor span	menu - More Functions...	Mean over span defined by cursor positions
Peak/Full	menu - Peak menu - More Functions...	Magnitude and location of peak for full span
Peak/Cursor span	menu - More Functions...	Magnitude and location of peak over span defined by cursor positions
Trough/Full	menu - Trough menu - More Functions...	Magnitude and location of trough for full span
Trough/Cursor span	menu - More Functions...	Magnitude and location of trough over span defined by cursor positions
Peak-Peak/Full	menu - More Functions...	Peak-peak for full span
Peak-Peak/Cursor span	menu - More Functions...	Peak-peak over span defined by cursor positions
Rise Time/First edge/10-90%	Toolbar menu - Rise Time menu - More Functions...	Rise time of first rising edge in waveform, measured at 10% and 90% points
Rise Time/First edge/20-80%	menu - More Functions...	Rise time of first rising edge in waveform, measured at 20% and 80% points
Rise Time/First edge/Custom	menu - More Functions...	Rise time of first rising edge in waveform, measured at user defined points
Rise Time/Cursors define edge/10-90%	menu - More Functions...	Rise time of edge defined by cursor positions, measured at 10% and 90% points
Rise Time/Cursors define edge/20-80%	menu - More Functions...	Rise time of edge defined by cursor positions measured at 20% and 80% points
Rise Time/Cursors define edge/Custom	menu - More Functions...	Rise time of edge defined by cursor positions, measured at user defined points
Fall Time/First edge/10-90%	Toolbar menu - Fall Time menu - More Functions...	Fall time of first falling edge in waveform, measured at 10% and 90% points
Fall Time/First edge/20-80%	menu - More Functions...	Fall time of first falling edge in waveform, measured at 20% and 80% points
Fall Time/First edge/Custom	menu - More Functions...	Fall time of first falling edge in waveform, measured at user defined points
Fall Time/Cursors define edge/10-90%	menu - More Functions...	Fall time of edge defined by cursor positions, measured at 10% and 90% points
Fall Time/Cursors define edge/20-80%	menu - More Functions...	Fall time of edge defined by cursor positions measured at 20% and 80% points
Fall Time/Cursors define edge/Custom	menu - More Functions...	Fall time of edge defined by cursor positions, measured at user defined points
Duty Cycle/Full	menu - More Functions...	Duty cycle measured over full span
Duty Cycle/Cursor span	menu - More Functions...	Duty cycle measured over span defined by cursor positions
Overshoot/Absolute/Auto	menu - More Functions...	Maximum absolute value of overshoot
Overshoot/Relative/Auto	menu - More Functions...	Maximum value of overshoot relative to pulse amplitude
Overshoot/Absolute/Cursors define edge	menu - More Functions...	Absolute value of overshoot measured at pulse defined by cursor positions
Overshoot/Relative/Cursors define edge	menu - More Functions...	Value of overshoot relative to pulse amplitude measured at pulse defined by cursor positions
Settling time/1%	menu - More Functions...	Settling time to 1%. Pulse defined by cursor positions
Settling time/0.1%	menu - More Functions...	Settling time to 0.1%. Pulse defined by cursor positions
Settling time/0.01%	menu - More Functions...	Settling time to 0.01%. Pulse defined by cursor positions
Settling time/Custom	menu - More Functions...	Settling time to user defined specification. Pulse defined by cursor positions
Frequency/Full	menu - Frequency menu - More Functions...	Frequency measured over full span.
Frequency/Cursor span	menu - More Functions...	Frequency measured over span defined by cursor positions
Distortion/Full	menu - More Functions...	Distortion measured over full span
Distortion/Cursor span	menu - More Functions...	Distortion measured over span defined by cursor positions
AC measurements
-3dB Lowpass	Toolbar menu - More Functions...	-3dB point assuming a low pass roll off
-3dB Highpass	Toolbar menu - More Functions...	-3dB point assuming a high pass roll off
+3dB Lowpass	menu - More Functions...	+3dB point assuming a response with low frequency lift
+3dB Highpass	menu - More Functions...	+3dB point assuming a response with high frequency lift
Other Measurements
Temperature coefficient	menu - More Functions...	Average temperature coefficient for temperature sweep only
Total Noise	menu - More Functions...	Integrated noise for noise analysis only


Curve operations

Graphs and Probes

Selecting curves

Deleting curves

Hiding and showing curves

Re-titling curves


D-type flip flop

Netlist entry:

Axxxx data clk set reset out nout model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
data	Input data	in	d	d	n/a
clk	Clock	in	d	d	n/a
set	Asynch. set	in	d	d	n/a
reset	Asynch. reset	in	d	d	n/a
out	Data output	out	d	d	n/a
nout	Inverted data output	out	d	d	n/a
Model format:

.MODEL model_name d_dff parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
clk_delay	Delay from clk	real	1.00E-09	1e-12 - INF	No	n/a
set_delay	Delay from set	real	1.00E-09	1e-12 - INF	No	n/a
reset_delay	Delay from reset	real	1.00E-09	1e-12 - INF	No	n/a
ic	Output initial state 0: logic '0' 1: logic '1' 2 : UNKNOWN	integer	0	0 - 2	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
data_load	Data load value (F)	real	1.00E-12	none	No	n/a
clk_load	Clk load value (F)	real	1.00E-12	none	No	n/a
set_load	Set load value (F)	real	1.00E-12	none	No	n/a
reset_load	Reset load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

The device is an edge triggered D-type flip flop with active high asynchronous set and reset. The operation of the device is illustrated by the following diagram


D-type latch

Netlist entry:

Axxxx data enable set reset out nout model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
data	Input data	in	d	d	n/a
enable	Enable	in	d	d	n/a
set	Asynch. set	in	d	d	n/a
reset	Asynch. reset	in	d	d	n/a
out	Data output	out	d	d	n/a
nout	Inverted data output	out	d	d	n/a
Model format:

.MODEL model_name d_dlatch parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
data_delay	Delay from data	real	1.00E-09	1e-12 - INF	No	n/a
enable_delay	Delay from clk	real	1.00E-09	1e-12 - INF	No	n/a
set_delay	Delay from set	real	1.00E-09	1e-12 - INF	No	n/a
reset_delay	Delay from reset	real	1.00E-09	1e-12 - INF	No	n/a
ic	Output initial state 0: logic '0' 1: logic '1' 2 : UNKNOWN	integer	0	0 - 2	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
data_load	Data load value (F)	real	1.00E-12	none	No	n/a
enable_load	Clk load value (F)	real	1.00E-12	none	No	n/a
set_load	Set load value (F)	real	1.00E-12	none	No	n/a
reset_load	Reset load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

The device is a level triggered latch with a single data input, complimentary outputs and active high asynchronous set and reset. The operation of the device is illustrated in the following diagram:

The asynchronous inputs (set and reset) override the action of the enable and data lines.


DAC

Netlist entry:

Axxxx [ digital_in_0 digital_in_1 .. digital_in_n ] analog_out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
digital_in	Data output	in	d	d	1 - 32
analog_out	Analog output	out	v	v, vd, i, id	n/a
Model format:

.MODEL model_name da_converter parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
output_offset	Offset voltage	real	0	none	No	n/a
output_range	Input signal range	real	1	none	No	n/a
twos_complement	Use 2's complement input. (Default is offset binary)	boolean	FALSE	none	No	n/a
output_slew_time	Output slew time	real	1.00E-08	1e-12 - INF	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
input_load	Input load	real	1.00E-12	0 - INF	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a

Device Operation

This device is a 1-32 bit digital to analog converter. Its operation is illustrated by the following diagrams.

DAC waveforms

DAC waveforms expanded to show output slew

The device illustrated above has the following model definition:

.model DAC_4 da_converter

+ output_slew_time 1e-08

+ output_range 5

+ output_offset 0

In offset binary mode the D-A converter produce an output voltage equal to:

-OUTPUT_RANGE/2 + OUTPUT_OFFSET + code * OUTPUT_RANGE/2n

where n is the number of bits and code is the digital input code represented as an unsigned number between 0 and 2n-1.

In 2's complement mode the output is:

OUTPUT_OFFSET + code * OUTPUT_RANGE/2n

where n is the number of bits and code is the digital input code represented as a signed number between -2n/2 and 2n/2-1.

Whenever the input code changes, the output is set on a trajectory to reach the target value in the time specified by OUTPUT_SLEW_TIME. UNKNOWN states are ignored. That is the input will be assumed to be at the most recent known state.


Define Curve Sheet

Plotting arbitrary expressions

Define Curve Sheet

Expression

Y	Enter arithmetic expression. This can use operators + - * / and ^  as well as any function. Both voltages and currents may be selected from the "Available Vectors" box.

X	Expression for X data. Only required for X-Y plot and you must check X-Y Plot box. Expression entered in the same way as for Y data

Available Vectors	Lists values available for plotting.Press "Edit Filter" to alter selection that is displayed. See below.

The names displayed are the names of the vectors created by the simulator. The names of node voltages are the same as the names of the nodes themselves. The names for device currents are composed of device name followed by a '#' followed by the pin name. Note that some devices output internal node voltages which could get confused with pin currents. E.g. q1#base is the internal base voltage of q1 not the base current. The base current would be q1#b. For the vector names output by a noise analysis see .NOISE.

Curve Label	Enter text string to label curve

Pressing the "Edit Filter..." button brings up:

This allows you to select what is displayed in the available vectors dialog. This is useful when simulating large circuits and the number of vectors is very large.

Sub-circuit Filter

All	Vectors at all levels are displayed

Top-level	Only vectors for the top-level are displayed

Select sub-circuit	All sub-circuit references will be displayed in the list box. Select one of these. Only vectors local to that sub-circuit will be displayed in Available Vector list.

Signal Type

All	List all signal types

Voltages Only	Only voltages will be listed

Currents Only	Only currents will be listed

Digital Only	Only digital vectors will be listed


Deleting Axes

Multiple Y-axis overview

To delete an axis, select it then press "Erase axis" button. Note that you cannot erase an axis or grid that has curves attached to it nor can you erase the "Main" axis. The main axis is the first axis that is created on a graph. For example with the following graph

If you attempt to delete the selected axis (the lower one), nothing will happen. Instead you should move the two curves in the top axis to the lower one. See Moving curves.


Deleting curves

To delete a curve (or curves), select it (or them) then press "Erase selected curves" button. Any axes or grids other than "Main" axis left empty by this operation will also be deleted.


Device Library and Parts Management
Device Library and Parts Management - Overview

The definitions for semiconductor devices such as transistors and for more complex devices such as op-amps are not built in to the simulator program but are defined in separate library files. These are text files containing .model and .subckt controls. Some libraries have been supplied with Easy-SPICE but you can obtain others from device manufacturers (usually at no cost) and other model vendors. You can also create them yourself using a text editor.

Many vendor libraries may be downloaded from the Internet. Our World Wide Web site carries a page with links to vendor sites. URL is

http://www.newburytech.co.uk

View the following topics for details on managing and using the model library.

Installing Model Libraries

Removing Model Libraries

.lib Control

Library Diagnostics

Library Indexing Mechanism

Duplicate Model Names


Device Reference

The following is a list of all devices supported by the simulator.

SPICE devices

Arbitrary Source

Bipolar junction transistor	Model Parameters

Capacitor	Model Parameters (optional)

Current controlled current source

Current controlled voltage source

Current source

Diode	Model Parameters

GaAsFET	Model Parameters

Inductor

Junction FET	Model Parameters

Lossy Transmission line	Model Parameters

MOSFET	Model Parameters

Mutual inductor

Resistor	Model Parameters (optional)

Subcircuit instance

Transmission line

Voltage controlled current source

Voltage controlled switch	Model Parameters

Voltage controlled voltage source

Voltage source

XSPICE devices - general info

XSPICE vector connections

XSPICE connection types

XSPICE analog devices

Capacitor with voltage initial condition

Inductor with voltage initial condition

S-domain transfer block

XSPICE digital devices

Common parameters

Delays

And Gate

D-type latch

D-type flip flop

Buffer

Digital Capacitor

Frequency Divider

Digital Initial Condition

Digital Pulse

Digital Resistor

Digital Signal Source

Inverter

JK Flip Flop

Arbitrary Logic Block

Nand Gate

Nor Gate

Open-Collector Buffer

Open-Emitter Buffer

Or Gate

Pulldown Resistor

Pullup Resistor

Random Access Memory

Set-Reset Flip-Flop

SR Latch

State Machine

Toggle Flip Flop

Tri-State Buffer

Exclusive NOR Gate

Exclusive OR Gate

XSPICE mixed signal model

Analog-Digital Converter

Analog-Digital Interface Bridge

Digital-Analog Converter

Digital-Analog Interface Bridge

Controlled Digital Oscillator

Analog-Digital Schmitt Trigger


Digital Capacitor

Netlist entry:

Axxxx ina inb outa outb model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
ina	Input A	in	d	d	n/a
inb	Input B	in	d	d	n/a
outa	Output A	out	d	d	n/a
outb	Output B	out	d	d	n/a
Model format:

.MODEL model_name d_cap parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
hold	Hold time	real	1.00E-09	1e-12 - INF	No	n/a
capacitance	Capacitance (F)	real	1.00E-12	none	No	n/a
ic	Initial state 0 initialise with input = output 1 initialise with input = inverse of output default: starts according to circuit conditions	integer		none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
Device Operation

The digital capacitor may be used in conjunction with a digital resistor to create an RC time delay or pulse implemented entirely in the digital domain. Although it is a four terminal device, it is intended to be used with each input connected to its corresponding output thus making a two terminal component.

The following circuits and waveforms illustrate the operation of this device.

Waveforms from above:

OUT 1 and OUT 4 demonstrate the use of the digital capacitor and resistor to create a single pulse. OUT 2 is the output of a delay circuit.

OUT 3 shows what happens when a single digital capacitor is connected to a pull down resistor. When one side of a digital capacitor changes state, the other side switches to the same state with a force of STRONG (See Logic States). It only stays STRONG for a short time determined by the HOLD parameter. The result in the above example is a narrow spike with a period equal to the HOLD parameter. The HOLD parameter defaults to 1n and generally should be kept short.

The following circuits show the digital capacitor and resistor being used in oscillator circuits.

The first circuit would usually have a resistor in the input of U2. This does not work when using the digital R's and C's.

The second circuit show a schmitt trigger as this would be required if the passive components were analog. However, the circuit will work just as well with a non-schmitt inverter.

The digital capacitor and resistor models were developed to provide improvements in simulation speed where analog timing components are required. In some cases the speed improvement can be dramatic. For example the second oscillator above took 0.4 seconds to run 2250 cycles using a Pentium III - 500MHz. The same number of cycles using analog R's and C's took about 17seconds. Note, however, that these components only approximate the behaviour of real analog components and should only be connected to other digital devices. Only the configurations shown in the above examples have been tested. They may provide a useful function in other arrangements but no guarantees are offered. Also note that the time delays created by digital R's and C's are not identical to their analog counterparts. The oscillator above, for example, runs at about half the frequency of the analog equivalent.


Digital Initial Condition

Netlist entry:

Axxxx out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_init parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
ic	Initial state	integer	0	none	No	n/a
is	Initial strength 1 = STRONG 0 = RESISTIVE	integer	1	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
Device Operation

This device has the defined initial state (IC parameter) and initial strength (IS parameter) during the DC operating point solution, then reverts to HI-IMPEDANCE for the remainder of the analysis.


Digital Pulse

Netlist entry:

Axxxx out model_name : parameters

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
out	Output	out	d	d	n/a
Instance parameters:

Name	Description	Type	Array?
period	Pulse period	real	No
delay	Delay	real	No
duty	Duty cycle	real	No
width	Pulse width	real	No
open_out	Open emitter output	boolean	No
Model format:

.MODEL model_name d_pulse parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
duty	Duty cycle	real	0.5	1e-06 - 0.999999	No	n/a
delay	Initial delay	real	0	0 - INF	No	n/a
period	Period If zero, a single pulse will be output	real	1.00E-06	1e-12 - INF	No	n/a
width	Pulse width (overrides duty if specified)	real	period * duty	0 - INF	No	n/a
open_out	Open emitter output	boolean	FALSE	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
Device Operation

This device supplies a repetitive or single pulse of defined period, delay and width. Optionally, the device may be specified to have an open emitter output allowing several pulse sources to be wire OR'ed to create complex pulses. All 5 main .MODEL parameters may also be specified on the device line as instance parameters in which case they override any values specified in the .MODEL control.

If OPEN_OUT is specified and true, a pull down resistor must be connected to the output.


Digital Resistor

Netlist entry:

Axxxx ina inb outa outb model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
ina	Input A	in	d	d	n/a
inb	Input B	in	d	d	n/a
outa	Output A	out	d	d	n/a
outb	Output B	out	d	d	n/a
Model format:

.MODEL model_name d_res parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
resistance	Resistance (Ohms)	real	1000	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
Device Operation

The digital resistor may be used in conjunction with a digital capacitor to create an RC time delay or pulse implemented entirely in the digital domain. Although it is a four terminal device, it is intended to be used with each input connected to its corresponding output thus making a two terminal component.

Full details on how to use this device is given in the digital capacitor.topic.

The digital resistor may also be used as a pull down or pull up resistor for open emitter and open collector outputs.


Digital Signal Source

Netlist entry:

Axxxx [ out_0 out_1 .. out_n ] model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
out	Output	out	d	d	none
Model format:

.MODEL model_name d_source parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
input_file	Digital input vector filename	string	none	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
Device Operation

The digital signal source provides a multi bit arbitrary digital signal defined in a file.

File Format

The file is in ASCII format and is in the form of a table each row being on a new line. The first column defines the time values while the entries in the remaining columns define the output value for each of the outputs. So the total number of columns must be the number of outputs plus one. The output values must appear in the same order as the outputs in the netlist entry. So, the values for out_0 will be in column 2, out_1 in column 3 etc.

The file may include blank lines and comment lines beginning with a '*'.

The output values must specify the state as well as the strength using the following codes:

0S	LOW-STRONG
1S	HIGH-STRONG
US	UNKNOWN-STRONG
0R	LOW-RESISTIVE
1R	HIGH-RESISTIVE
UR	UNKNOWN-RESISTIVE
0Z	LOW-HI-Z
1Z	HIGH-HI-Z
UZ	UNKNOWN-HI-Z
0U	LOW-UNDETERMINED
1U	HIGH-UNDETERMINED
UU	UNKNOWN-UNDETERMINED

Note, these codes are not case sensitive.

Example:

The following file:

* This is an example source file

0.0    0s  0s  0r  1s

1u     0s  0s  0r  0z

2u     0s  0s  1r  0z

5u     1s  0s  1r  0z

22e-6  1s  1s  1r  0z

50u    0s  1s  1r  0z

60u    0s  1s  1r  0z

70u    0s  1s  1r  0z

80u    0s  1s  1r  0z

90u    Us  Us  Ur  0s

and this circuit:

Produces the following waveforms

An error will result if the file fails in any way to comply with the format. There must be the exact number of entries in each row and the time values must be monotonic. Totally blank lines or lines containing only white space are permitted but any other non-comment line not complying with the format will fail.


Digital Simulation

As well as an analog simulator, Easy-SPICE incorporates an event driven digital simulator tightly coupled to the analog portion. This system can rapidly and accurately simulate mixed signal circuits containing both analog and digital components. Of course, an analog only simulator can simulate a mixed signal circuit using digital models constructed from analog components, but this approach is slow. The advantage of this "mixed-mode" approach is that it is dramatically faster, typically in the order of 100 times for pure digital circuits.

The Easy-SPICE mixed mode simulator is based on the XSPICE system developed by the Georgia Technical Research Institute. Although based on XSPICE, Easy-SPICE features many enhancements over the original system.

If you only use digital models supplied in the device library, then you don't need to know much about the digital simulator in order to use it. Just select the devices you need from the parts browser and simulate in the normal way. This chapter describes some of the inner workings of the simulator including how it interfaces to the analog system. More importantly, perhaps, this chapter also describes how you can design your own digital models.

Refer to these topics for full details of digital simulation

Logic states

Analog to digital interfaces

Logic families

Digital model libraries

Arbitrary logic block

Mixed-mode simulator - how it works

Enhancements over XSPICE


Digital model libraries

Digital simulation overview

Using Third Party Libraries

The Easy-SPICE digital simulator is based on XSPICE and all the XSPICE digital devices have been implemented. Virtually all of these have been enhanced in a number of ways but all remain backward compatible with the original XSPICE. Consequently any 100% XSPICE compatible digital model will work with Easy-SPICE.

Designing New Models

You can design new digital models either by creating a subcircuit using primitive components, using the arbitrary logic block or a combination of both. See Devices Reference for documentation on available digital primitive devices.


Digital-Analog Interface Bridge

Netlist entry:

Axxxx in out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	n/a
out	Output	inout	g	g	n/a
Model format:

.MODEL model_name dac_bridge parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
out_low	Analog output for 'ZERO' digital input	real	0	none	No	n/a
out_high	Analog output for 'ONE' digital input	real	5	none	No	n/a
g_resistive	Output conductance for 'RESISTIVE' digital input	real	0.001	none	No	n/a
g_pullup	Output conductance for 'STRONG' digital high input	real	0.01	none	No	n/a
g_pulldown	Output conductance for 'STRONG' digital low input	real	0.01	none	No	n/a
g_hiz	Output conductance for 'HI_IMPEDANCE' strength	real	1.00E-09	none	No	n/a
input_load	Capacitive input load (F)	real	1.00E-12	none	No	n/a
t_rise	Rise time 0 -> 1	real	1.00E-09	1e-12 - INF	No	n/a
t_fall	Fall time 1 -> 0	real	1.00E-09	1e-12 - INF	No	n/a
knee_high	Knee voltage logic high state	real	3	none	No	n/a
knee_low	Knee voltage logic low	real	2	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
v_smooth	Smoothing func offset voltage	real	0	0 - INF	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
DC characteristics

This digital to analog interface bridge is the main device used to connect digital signals to analog devices. The output provides an analog voltage and source resistance according to the state and strength of the driving digital input. The output has a non-linear characteristic that is a simplified model of a typical digital output stage. The following graphs show the output characteristics for the supplied high speed CMOS DA bridge. This has the following model parameters:

.model HC_dac dac_bridge

+ out_high=5       ; Logic high voltage

+ input_load=-31p  ; Compensates for added rise and fall time

+ t_rise=2n        ; Output rise time

+ t_fall=2n        ; Output fall time

+ g_pullup=0.024   ; 1/(logic high output resistance)

+ g_pulldown=0.034 ; 1/(logic low output resistance)

+ g_hiz=1e-9       ; 1/(high impedance output res)

+ knee_low = 2.0   ; voltage at resistive/constant current knee logic low

+ knee_high =2.75  ; voltage at resistive/constant current knee logic high

+ v_smooth = 0.5   ; Knee smoothing band

+ in_family="HC"

Logic '0' state - strength = STRONG

In the above graph, the slope of the curve at V=0 is determined by the G_PULLDOWN parameter.  The "knee smoothing band" is a transitional area where the output switches from a constant resistance to a constant current. The smoothing characteristic is a quadratic and is calculated to be smooth at all points. This is required for good convergence behaviour. The knee smoothing band starts at KNEE_LOW-V_SMOOTH and finishes at KNEE_LOW+V_SMOOTH.

Logic '1' state - strength = STRONG

If a state with RESISTIVE strength is applied to the input of a digital to analog interface bridge, the output has the characteristic of a pure resistor connected to the voltage associated with the input's state. In the example given above, this would be a 1k resistor connected to 0V for the logic '0' state and a 1k resistor connected to +5V for the logic '1' state. (1k is 1/G_RESISTIVE)

For the HI-IMPEDANCE strength, the output will look like a resistor of value 1/G_HIZ connected to a voltage half way between the two analog output states. (1G connected to 2.5V in the above example.)

When the input state is UNKNOWN the output will be as if it were half way between the two known states. This is a compromise solution. The UNKNOWN state does not have a parallel in the analog domain so instead it is treated as a transitional state. In some cases the UNKNOWN state occurs in transitional cases although this is not the correct meaning of UNKNOWN.

Switching Characteristics

When the logic state at the input changes, the output will transition from the current state to the target state in a time determined by T_RISE or T_FALL according to the direction of the state change.


Diode

Model Parameters	Examples

Netlist Entry

Dxxxx N+ N- model_name [area] [OFF] [IC=vd] [TEMP=local_temp]

N+	Anode

N-	Cathode

model_name	Name of model defined in a .model control. Must begin with a letter but can contain any character except whitespace and ' . ' .

area	Area multiplying factor. Area scales up the device. E.g an area of 3 would make the device behave like 3 diodes in parallel. Default is 1.

OFF	Forces the device to be initially off. The affects the initial guess prior to commencing the DC operating point analysis and is useful to force a particular state for a bistable circuit. See .nodeset for more information.

vd	Initial condition for diode voltage. This only has an effect if the UIC parameter is specified on the .tran control.

local_temp	Local temperature. Overrides specification in .options or .temp control.


Diode Examples
Examples:


Diode Model Parameters

Notes

Model syntax:

.model modelname D ( parameters )

Parameters:

The symbols ' × ' and ' ÷ ' in the Area column means that that parameter should be multiplied or divided by the area factor respectively.

Name	Description	Units	Default	Area

IS	Transport saturation current	A	1e-14	×

ISR	Recombination current parameter	A	0	×

N	Emission coefficient	1

NR	Emission Coefficient for ISR	2

IKF	High injection knee current	A	∞	×

RS	Series resistance	Ω	0	÷

TT	Transit time	sec	0

CJO or CJ0	Zero bias junction capacitance	F	0	×

VJ	Junction potential	V	1

M	Grading coefficient	0.5

EG	Energy gap	eV	1.11

XTI	Saturation current temperature exponent	3

KF	Flicker noise coefficient	0

AF	Flicker noise exponent	1

FC	Forward bias depletion capacitance
coefficient	0.5

BV	Reverse breakdown voltage	V	∞

IBV	Current at breakdown voltage	A	1e-10	×

TNOM	Parameter measurement temperature	°C	27

TRS1	First order tempco RS	/°C	0

TRS2	Second order tempco RS	/°C2	0

TBV1	First order tempco BV	/°C	0

TBV2	Second order tempco BV	/°C2	0


Diode param Notes
The dc characteristics of the diode are determined by the parameters IS, N, ISR, NR and IKF. An ohmic resistance, RS, is included. Charge storage effects are modeled by a transit time, TT, and a nonlinear depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The temperature dependence of the saturation current is defined by the parameters EG, the energy and XTI, the saturation current temperature exponent. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters BV and IBV (both of which are positive numbers).


Direct Netlist Entry

This is the traditional method of entering a circuit to the simulator. Generally entering via the schematic is a superior method as it is easier, less error prone, allows cross-probing of simulation results and is far easier to modify. However, they may be occasions when entering the circuit the "old-fashioned" way may be desirable. This section describes how to simulate a netlist direct and provides information on the netlist format.

Simulating an Existing Netlist

Select the menu Simulator|Run Netlist...

Select a netlist file from the dialog box. Netlist files are assumed to have the extension ".net".

Select Close.

Plotting Results from Netlist Simulation

Use the command shell menus Graphs and Data|Plot Result (New Graph)... or Graphs and Data|Plot Result (Add to Graph)... . These are explained in detail Plotting arbitrary expressions

Netlist Format

The netlist is a text file consisting of a title line followed by a series of device lines and simulator controls. Device lines begin with a letter which signifies the type of device (e.g. Q is a BJT) followed by a list of nodes (or nets) to which that device is connected and some description of that device. Simulator controls always begin with a period ( . ) and are used to provide the simulator with other information such as what simulation to perform and model descriptions.

Nodenames can be any character string but may not contain spaces or the characters '#' or '.'. (But nodenames may begin with a '#' to signify a global node). In addition you should avoid names containing the characters:

 \ " % & + - * / ^ < > [ ] ' . @ { }

These are legal but you will not be able to plot the voltage at node with names containing these characters as they conflict with expression operators and other special characters.

For details of device lines, each entry in the Devices Reference has a description titled "Netlist Entry" which gives the full format for each device.

For details of simulator controls, see Simulator Controls Reference.


Duplicate Model Names

Device Library and Parts Management - Overview

Models of some common parts are available from different sources. Sometimes these have different names, e.g LF356 and LF356/NS - the latter available from the National Semiconductor library. In some cases the model names from different sources are identical. This poses a problem as models have to be uniquely identified by there name.

To overcome this the simulator features a method of specifying a preferred path for the model. The path is placed immediately before the model name and is enclosed with '<' and '>'

E.g.

<d:\spice_models\motorola\rf>BFR92

Note that if the path name contains spaces, the spaces must be replaced with a pipe ('|') symbol. E.g for "d:\sp\spice models\motorola\rf" use "d:\sp\spice|models\motorola\rf"


Easy-SPICE Help

Introduction

What is Easy-SPICE?

Easy-SPICE Philosophy

Why Simulate?

System Requirements

A Note to US and Canadian Users

Easy-SPICE and SPICE

What's New for Release 3.0

What's New for Release 3.1

Upgrade Notes

Tutorials

Tutorials Overview

Tutorial 1

Tutorial 2

Tutorial 3

Basic Steps to Simulate a Circuit:

Schematic Entry

Circuit Stimulus

Define Analysis Mode

Running Simulator

Plotting Results

Hardcopy

Circuit Definition

Overview

Direct Netlist Entry

Schematic Editor

Devices and Models

Device Reference

Non-linear Magnetics

Sub-circuits

Parameters

Functional Modelling

The Simulator

Convergence and Accuracy Issues

Simulator Control Reference

Digital Simulation

Overview

Logic States

Analog to Digital Interfaces

Logic Families

Digital Model Libraries

Mixed-mode simulator - how it works

Enhancements over XSPICE

Arbitrary Logic Block - User Defined Devices

Device Library and Parts Management

Overview

Using Parts Browser

Installing Model Libraries

Removing Model Libraries

Graphs, Probes and Data analysis

Overview

Basic Graph Plotting

Fixed Probes

Random Probes

Curve Measurements

Viewing DC Operating Point Results

The Command Shell

Diagram

Command Line

message window

Menu Reference

Keyboard

Monte Carlo Analysis

Overview

An Example

Tolerance Specification

Running Simulation

Advanced Topics

Component and Parameter Stepping

Options and Preferences

Colours and Fonts

Defining Schematic Symbols

Key And Menu Definitions

Startup Script

Data Import and Export


Easy-SPICE vs SPICE

Easy-SPICE is developed from SPICE version 3e.2 and subsequently upgraded to include 3f.5 enhancements. The original simulator core, however, suffers from a number of problems and, although better than SPICE2, converges poorly for some types of circuit. Over the years we have improved the basic simulator culiminating in the recent development of "pseudo transient analysis" which solves most DC operating point problems.

However, we have modified some of the devices and not implemented others. We have also not implemented all analysis modes available with SPICE 3. Details follow.

Devices

Capacitors:

Easy-SPICE:	Allows two temperature coefficients of capacitance and two voltage coefficients on device line and model. (TC1, TC2, VC1, VC2).

SPICE 2	Allows polynomial voltage coefficients. Temperature coefficients not supported.

SPICE 3	Has capacitor model allowing specification in terms of process parameters. Does not support voltage or temperature coefficients.

Inductors:

Easy-SPICE	Inductance value only

SPICE 2	Allows polynomial current coefficients.

SPICE 3	Inductance value only

MOSFETs

Easy-SPICE	Supports levels 1, 2 & 3 and new proprietary level 7 designed for vertical devices. Supports specification for L and W as model parameters for compatibility with PSPICE®. BSIM3 v3 and Philips MOS level 9 available as add on modules

SPICE 2	Supports levels 1, 2 & 3

SPICE 3	Supports levels 1-6. Levels 4 and 5 are BSIM1 and BSIM2 respectively. Level 6 is a new empirical model

Resistors:

Easy-SPICE	Supports 2 temperature coefficients on device line and in model.

SPICE 2	Supports 2 temperature coefficients on device line only.

SPICE 3	Supports 2 temperature coefficients in model only. Also allows specification of resistance in terms of process parameters.

Voltage Controlled Switches:

Easy-SPICE	Switch specified in terms of model describing on resistance (RON), off resistance (ROFF), turn on voltage (VON) and turn off voltage (VOFF). Resistance between VON and VOFF varies continuously following a cubic law. Switch model is compatible with PSPICE®

SPICE 2	Switches not implemented.

SPICE 3	Switch specified in terms of on resistance, off resistance, threshold voltage and hysteresis voltage. Device switches abruptly at appropriate voltage.

Additional model parameters have been added to some devices for compatibility with other commercial simulators. Devices affected are:

Diodes

BJT's

JFET's

MOSFET's

The following devices are implemented in SPICE 3 but are not available with Easy-SPICE.

Current controlled switch

Uniform Distributed RC Line

Analysis Modes

Easy-SPICE does not support SPICE3 distortion analysis as we believe the work required to test and support this mode is not justified by its usefulness.

SPICE3 Fourier analysis using the .FOUR control is not implemented as an analysis mode. Instead similar functionality is available with the FFT feature.

All other analysis modes are available except AC Sensitivity.


Editing axes

You can edit axis scales, label and units by selecting the graph popup menu Edit Axis.... This brings up the following dialog box:

The function of the Axis scales sheet and axis labels sheet is similar to the sheets of the same name in the define curve dialog box. See Plotting Arbitrary Expressions.


Enhancements over XSPICE

Digital simulation overview

•	Gate delays in XSPICE are "stored" i.e. like a transmission line not like a real gate. Easy-SPICE gate delays are "inertial" so if a pulse shorter than the propagation delay is received, it is swallowed not transmitted.

•	Automatic interface creation. In XSPICE you have to explicitly join digital and analog nodes via interface bridges. In Easy-SPICE this is done automatically.

•	Fan out implemented.  The underlying mechanism for load dependent delay was there but none of the models supported it. Static loading effects (as in bipolar logic) was not supported at all. In Easy-SPICE it is.

•	Input load reflected in analog to digital interfaces. The AD interfaces in XSPICE have infinite input impedance regardless of what the digital output is driving. Easy-SPICE AD interfaces reflect the digital capacitative and static load at their inputs.

•	Output strength reflected in digital to analog interfaces. The DA interfaces in XSPICE have zero output impedance regardless of what is driving them. Easy-SPICE DA interfaces reflect the strength of the digital output driving the input. A hi-z logic state will look like a hi-z logic state when transferred to the analog domain. This is not the case with XSPICE.

•	AD interface threshold detection. All AD interfaces switch at a particular input threshold. In the XSPICE system the output switched at the first analog timepoint that exceeded the threshold. This could be a long way passed the threshold if the analog time steps are large. In Easy-SPICE a mechanism has been implemented that cuts back the time step so that the threshold is hit within a specified time tolerance.

•	Arbitrary logic block device. This allows the definition of any logic device using a simple descriptive language. The language accommodates combinational logic, synchronous and asynchronous registers as well as look up tables (i.e. ROMS) and arrays (i.e. RAMS)

•	Arbitrary analog to digital converter. Up to 32 bits with specified input range and offset, conversion time and max conversion rate. Output may be in two's complement or offset binary.

•	Arbitrary digital to analogue converter. Up to 32 bit with specified input range and offset and output slew time. Input may be in two's complement or offset binary.

•	Voltage controlled oscillator (analog in digital out). There was one of these in the original XSPICE code but it suffered a number of problems and was scrapped. The Easy-SPICE version is all new.


Examples BJT

25 MJE15025's connected in parallel with junction temperature = 85°C


Exclusive NOR Gate

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	2 - no upper bound
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_xnor parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (pF)	real	1	0 - INF	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

If the OPEN_C parameter is FALSE, the output is at logic '1' if an even number of inputs are at logic '1'. If any input is UNKNOWN the output will be UNKNOWN, otherwise the output will be at logic '0'.

If the model parameter OPEN_C is true the device will be open collector.  In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If n even number of inputs are at logic '1' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. If any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.


Exclusive OR Gate

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	2 - no upper bound
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_xor parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

If the OPEN_C parameter is FALSE, the output is at logic '1' if an odd number of inputs are at logic '1'. If any input is UNKNOWN the output will be UNKNOWN, otherwise the output will be at logic '0'.

If the model parameter OPEN_C is true the device will be open collector.  In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If an odd number of inputs are at logic '1' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. If any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.


Exponential Source

This applies to both voltage and current sources

exp ( V1 V2 [TD1 [TAU1 [TD2 [TAU2 ]]]] )

V1	Initial value (Volts or amps)	Compulsory

V2	Pulsed value (Volts or amps)	Compulsory

TD1	Rise delay time	Default if omitted or zero= 0

TAU1	Rise time constant	Default if omitted or zero=  Time step

TD2	Fall delay time	Default if omitted or zero= TD1 +  Time step

TAU2	Fall time constant	Default if omitted or zero=  Time step


FFT notes

The FFT (fast fourier transform) is a mathematical algorithm for calculating a discrete fourier transform extremely efficiently. The discrete fourier transform (DFT) converts sampled time domain data to the frequency domain. In effect a mathematical version of a spectrum analyser.

The data presented to the FFT algorithm must satisfy two criteria. Firstly the data points must be evenly spaced and secondly the number of points must be a binary power.

If you select a value whose points are not evenly spaced, Easy-SPICE will use interpolation to derive a set of evenly spaced points. By default the number of points will be 1024 and the interpolation order is 2. These can both be changed in the "Graph/Probe/Data Analaysis" sheet of the options dialog box. If the points are evenly spaced but not a binary power, Easy-SPICE will use the next highest binary power and fill the excess with zeros.

It is recommended that an understanding of FFT's is gained before using them seriously. There are a number of traps into which the unwary can fall. Almost any text on digital signal processing will offer extensive coverage on the subject. In particular it is useful to gain an understanding of "aliasing" and "windowing".


FIR() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Vector to be filtered

Argument 2	Type:	Real only

Compulsory ?:	Yes

Purpose	Filter coefficients

Argument 3	Type:	Real only

Compulsory ?:	No

Purpose	Initial conditions

Default	All zero

Return value	Type:	Real

Vector allowed:	Yes

Performs "Finite Impulse Response" digital filtering on supplied vector. This function performs the operation:

Where:

x is the input vector (argument 1)

c is the coefficient vector (argument 2)

y is the result (returned value)

The third argument provide the "history" of x i.e.

 ,

etc as required.

The operation of this function (and also the IIR() function) is simple but its application can be the subject of several volumes! Below is the simple case of a four sample rolling average. In principle an almost unlimited range of FIR filtering operations may be performed using this function. Any text on Digital Signal Processing will provide further details.

User's should note that using this function applied to raw transient analysis data will not produce meaningful results as the values are unevenly spaced. If you apply this function to simulation data, you must either specify that the simulator outputs at fixed intervals (see .TRAN) or you must interpolate the results using the Interp() function.

Example

Suppose a vector VOUT exist in the current group (simulation results). The following will plot VOUT with a 4 sample rolling average applied

Plot FIR(vout, [0.25, 0.25, 0.25, 0.25])

Alternatively, the following does the same

Plot FIR(vout, 0.25*unitvec(4))


Features
Simulator Features

The simulator is based on two publicly available programs namely SPICE developed by the CAD/IC group at the department of Electrical Engineering and Computer Sciences, University of California and XSPICE developed by the Georgia Technical Research Institute. XSPICE  itself was developed from SPICE3C1.

Features:

Closely coupled direct matrix analog and event driven digital simulator.

Enhanced transient analysis algorithm to reduce convergence problems.

Incremental graphing of results as simulation proceeds.

Real noise source allowing investigation of noise effects with transient analysis.

Functional modelling with arbitrary non-linear source and arbitrary linear s-domain transfer function.

Arbitrary logic block for definition of any digital device using descriptive language. Supports synchronous, asynchronous and combinational logic as well as ROMS and RAMS.

Models for saturable magnetic components including support for air-gaps.

Built in vertical MOSFET model with non-linear gate-drain capacitance and temperature dependent drain-source resistance.

User definable fixed and popup menus and key definitions.


File Menu
Command Shell File Menu

Load Data...	Restore simulation data saved with File|Save Data... . More info: Saving Results of Simulation.

Save Data...	Save simulation data. More info: Saving Results of Simulation.

Change Directory...	Change current working directory

Model Library|Add/Remove Libraries...	Installs model libraries. More info: Installing Model Libraries

Model Library|Remove Libraries...	Removes model libraries. More info: Removing Model Libraries

Model Library|View Models...	View currently installed models.

Model Library|Re-build Catalog	Re indexes model library.

Model Library|Create Library Dictionary...Create a text file with complete listing of all installed models.

Print ...	Print graph

Options|Font...	Select font styles. More info: Colours and fonts

Options|Colour..	Select colours. More info: Colours and fonts

Options|General...	Opens options dialog box

Windows|Save Desktop	Save current window positions.

Windows|Restore Desktop	Restore window positions saved with File|Save Desktop

Windows|Select Window...	Displays dialog box showing current Easy-SPICE windows. Selected window will receive input focus.

Exit	Exit Easy-SPICE


Floor

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Return value	Type:	Real only

Vector allowed:	No

Returns the the argument truncated to the next lowest integer. Examples

Floor(3.45) = 3

Floor(7.89) = 7

Floor(-3.45) = -4


Frequency Divider

Netlist entry:

Axxxx freq_in freq_out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
freq_in	Frequency input	in	d	d	n/a
freq_out	Frequency output	out	d	d	n/a
Model format:

.MODEL model_name d_fdiv parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
div_factor	Divide factor	integer	2	1 - INF	No	n/a
high_cycles	Number of high clock cycles	integer	1	1 - INF	No	n/a
i_count	Output initial count value	integer	0	0 - INF	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
freq_in_load	Freq_in load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

This device is a positive edge triggered frequency divider. Three model parameters allow arbitrary definition of the divide ratio, output duty cycle, output phase and initial delay. Operation of the frequency divider is illustrated by the following diagram which shows the output of a frequency divider with a DIV_FACTOR of 10 and two alternative values of HIGH_CYCLES.

The above was carried out with I_COUNT=0. I_COUNT is the initial value of the internal counter. The output first goes high when it attains a value of 1 or 1+DIVIDE_RATIO so when I_COUNT is zero (the default) the output first goes high after the first rising edge. If  I_COUNT is set to 5 the output first goes high after the 6th rising edge and if I_COUNT is -20, the 21st rising edge.


Function Reference

abs	Absolute value

AddRemoveDialog	User interface function. Allows selection of a list of items.

atan	Arc tangent

BoolSelect	User interface function. Returns state of up to 6 check boxes

CanOpenFile	Returns TRUE if specified file exists and can be opened for read

ChangeDir	Change current working directory and return value according to success

Char	Returns character from string

ChooseDir	User interface function. Returns user selected pathname.

CollectionName	Returns name of collection attached to current group

cos	Cosine

Date	Return date

db	dB(x) = 20 * log10 ( mag(x) )

diff	Return derivative of argument

EditSelect	User interface function. Returns entries in up to 6 edit controls

ExistDir	Returns value according to existence and write priviledge of directory

ExistVec	Returns TRUE if specified variable name exists.

exp	Exponential

fft	Fast Fourier Transform

FindModel	Returns location of device model given name and type

FIR	Finite Impulse Response digital filter

Floor	Returns argument truncated to next lowest integer

FullPath	Returns full path name of given relative path

GetAllCurves	Returns array of curve indexes for all curves in current graph

GetAllYAxes	Returns array of axis id's for all y axes in current graph

GetAxisCurves	Returns array of curve id's for all curves attached to specified axis

GetAxisLimits	Returns min and max limits and axis type (log or lin) of specified axis

GetAxisType	Returns type (X, Y, Digital etc.) of specified axis

GetAxisUnits	Returns units of specified axis

GetCurDir	Return current working directory

GetCursorCurve	Returns curve id and source group name of curve attached to measurement cursor

GetCurveAxis	Returns axis id of specified curve

GetCurveName	Returns name of specified curve

GetCurves	Returns curve names in selected graph

GetCurveVector	Returns data associated with a graph curve

GetDatumCurve	Returns curve id and source group name of curve attached to reference cursor

GetEnvVar	Return specified system environment variable

GetFile	User interface function. Returns user selected file name

GetFilecd	User interface function. As GetFile but changes directory.

GetFileSave	User interface function. Returns user selected file name for saving

GetLegendProperties	Returns array of graph legend properties

GetNumCurves	Returns number of curves in curve group

GetOption	Returns value of specified option

GetPath	Returns application path

GetSelectedCurves	Returns array of curve id's for curves selected in current graph

GetSelectedYAxis	Returns id of selected Y-axis

GetWindowNames	Returns names of current Easy-SPICE windows

GetXAxis	Returns id of x-axis for currently selected graph

GraphLimits	Returns x and y limits of selected graph

GroupDelay	Returns group delay of argument

Groups	Returns array of available groups.

GroupsInCollection	Returns array of groups belonging to specified collection

Histogram	Returns histogram of argument

Iff

IIR	Infinite Impulse Response digital filter

im	Return imaginary part of argument

imag	same as im()

InputGraph	User Interface function. Input text for graph operation

integ	Returns integral of argument

Interp	Interpolates argument to specified number of evenly spaced points

IsComplex	Returns TRUE if argument is complex

IsNum	Returns TRUE if argument is numeric

IsStr	Returns TRUE if argument is a string

length	Returns number of elements in vector.

ln	Natural logarithm

log	Natural logarithm

log10	Base 10 logarithm

mag	Magnitude (same as abs())

magnitude	As mag()

MakeCollection	Creates a collection and returns unique name

MakeDir	Make new file system directory and return value according to success

MakeString	Create a string array with specified number of elements

Maxidx	Returns index of vector where largest value is held

Maxima	Returns locations of maxima of specified vector

MCOptions	User Interface function. Returns user specified Monte Carlo options

mean	Returns statistical mean of all values in vector

Mean1	Returns mean of data in given range

Mid	Returns substring of string

minidx	Returns index of vector where smallest value is held

Minima	Returns locations of minima of specified vector

norm	Returns argument scaled so that its largest value is unity.

Parse	Splits string into substrings.

PassiveDialog	User interface function. Returns passive component value selected by user.

PhysType	Returns physical type of argument

ph	Returns phase of argument

phase	As ph()

phase_rad	As ph() but result always in radians

PhysType	Returns physical type of argument

RadioSelect	User interface function. Returns user selection of up to 5 radio buttons

Range	Returns range of vector

re	Return real part of argument

ReadFile	Reads text file and returns contents as an array of strings

real	As re()

Ref	Returns reference of argument

RefName	Returns the name of the arguments reference vector

RelativePath	Returns a relative path name given a full path and a reference path

Rms	Returns accumulative rms value of argument

RMS1	Returns rms of argument over specified range

rnd	Returns random number

RootSumOfSquares	Returns root sum of squares of argument over specified range

Scan	Splits a character delimited string into its components

ScriptName	Return name of currently executing script

SearchModels	Special purpose used by library installation. Returns pathnames of SPICE compatible model files

SelectColumns	Analyses an array of character delimited strings and returns selected values.

SelectDialog	User interface function. Allows selection of one or more items from list

SelectRows	Analyses an array of character delimited strings and returns selected values

SelGraph	Returns TRUE if at least one graph is open

sign	Return sign of argument

sin	Sine

Sort	Performs alphanumeric sort on argument

SplitPath	Splits file system path into its components

sqrt	Square root

StepDialog	User interface function. Returns user selected parameters for component stepping

Str	Converts argument to string

SumNoise	Same as RootSumOfSquares

tan	Tangent

Time

TransformerDialog	Special function to select transformer characteristics

Units	Returns physical units of argument

UnitVec	Returns vector of specified length whose elements are all 1

Val	Converts argument to value

ValueDialog	User interface function. Opens dialog with up to 10 boxes for entering numeric values. Return array of user selected values

Vector	Returns vector of specified length with each element equal to its index

VectorsInGroup	Returns array of variable names belonging to specified group

VersionInfo	Returns info about Easy-SPICE version

Xcursor	Returns x location of graph cursor

Xdatum	Returns x location of graph reference cursor

XFromY	Returns array of values specifying horizontal locations where specified vector crosses given y value

Ycursor	Returns y location of graph cursor

Ydatum	Returns x location of graph reference cursor

YFromX	Returns array of values specifying the vertical value of the specified vector at the given x value


Functions

Only a few of the approx. 200 functions are documented in the help system. The ones listed here are the functions that accept and return numeric values and that could conceivably used for graph plots

abs(real/complex)

cos(real/complex)

db(real/complex)

diff(real)

exp(real/complex)

fft(real [, string])

FIR(real, real [, real])

Floor(real)

GroupDelay(real/complex)

Histogram(real, real)

Iff(real, any, any)

IIR(real, real [, real])

im(real/complex), imag(real/complex)

integ(real)

Interp(real, real [, real, real])

IsComplex(any)

length(any)

ln(real/complex), log(real/complex)

log10(real/complex)

mag(real/complex), magnitude(real/complex)

maxidx(real/complex)

Maxima(real [, real, string])

mean(real/complex)

Mean1(real [, real, real])

minidx(real/complex)

Minima(real [, real, string])

norm(real/complex)

ph(real/complex), phase(real/complex)

phase_rad(real/complex)

Range(real/complex [, real, real])

re(real/complex), real(real/complex)

Ref(real/complex)

Rms(real)

RMS1(real [, real, real])

rnd(real)

RootSumOfSquares(real [, real, real])

sign(real)

sin(real/complex)

sqrt(real/complex)

SumNoise(real [, real, real])

tan(real/complex)

unitvec(real)

vector(real)

XY(real, real)


GaAsFET

Model Parameters

Netlist Entry

Zxxxx drain gate source modelname [area] [OFF] [IC=vds , vgs]

drain	Drain node

gate	Gate node

source	Source node

modelname	Name of model defined in a .model control. Must begin with a letter but can contain any character except whitespace and ' . ' .

area	Area multiplying factor. Area scales up the device. E.g an area of 3 would make the device behave like 3 transistors in parallel. Default is one.

OFF	Forces the device to be initially off. The affects the initial guess prior to commencing the DC operating point analysis and is useful to force a particular state for a bistable circuit. See .nodeset for more information.

vds,vgs	Initial conditions for drain-source and gate-source junctions respectively. These only have an effect if the UIC parameter is specified on the .tran control.


GMIN
A value which defaults to 1E-12 but can be changed with the .options control.


GaAs Model Parameters

Notes

Model Syntax:

.model modelname NMF ( parameters )

Parameters:

The symbols ' × ' and ' ÷ ' in the Area column means that that parameter should be multiplied or divided by the area factor respectively.

Name	Description	Units	Default	Area

VTO	Pinch-off Voltage	V	-2.0

BETA	Transconductance parameter	A/V^2	2.5e-3	×

B	Doping tail extending parameter	1/V	0.3

ALPHA	Saturation voltage parameter	1/V	2

LAMBDA	Channel length modulation parameter	1/V	0

RD	Drain ohmic resistance	Ω	0	÷

RS	Source ohmic resistance	Ω	0	÷

CGS	Zero bias gate source capacitance	F	0	×

CGD	Zero bias gate drain capacitance	F	0	×

PB	Gate junction potential	V	1

IS	Gate p-n saturation current	A	1e-14	×

FC	Forward bias depletion capacitance
coefficient	0.5

KF	Flicker noise coefficient	0

AF	Flicker noise exponent	1


GaAsFET parameter Notes
The GaAsFET model is derived from the model developed by Statz. The DC characteristics are defined by parameters VTO, B and BETA, which determine the variation of drain current with gate voltage, ALPHA, which determines saturation voltage, and LAMBDA, which determines the output conductance. IS determines the gate-source and gate-drain dc characteristics.

Two ohmic resistances are included. Charge storage is modeled by total gate charge as a function of gate-drain and gate-source voltages and is defined by the parameters CGS, CGD and PB.


Global Nodes

Overview of sub-circuits

Sometimes it is desirable to refer to a node at the circuit's top level from within a subcircuit without having to explicitly pass it. This is sometimes useful for supply rails.

Easy-SPICE provides two methods.

1.	'#' prefix. Any node within a subcircuit prefixed with '#' will connect to a top level node of the same name without the '#' prefix.

2.	'$g_' prefix. Any node in the circuit prefixed '$g_' will be treated as global

The second approach is compatible with PSPICE®.

Note the two approaches are subtly different. In the second approach the '$g_' prefix must be applied to all connected nodes, whereas in the first approach the '#' prefix must be applied only to subcircuit nodes.


Graph - copying to clipboard

Graphs and Probes

Copying to the Clipboard

There are three different ways a graph can be copied to the clipboard. These are detailed in the following table.

Graph popup menu	Description
Copy to Clipboard|Colour	Copies graph to clipboard in full colour. The curve legends identify the curves using coloured squares similar to how the graph is displayed on the screen.
Copy to Clipboard|Monochrome	Copies graph to clipboard in monochrome. Curves are distinguished using varying markers and line styles. Curve legends distinguished curves with a straight line example
Copy to Clipboard|Colour with markers	Copies graph to clipboard in full colour but also differentiates curves using markers and line styles.  Curve legends distinguished curves with a straight line example.


Graph Cursors

Graphs and Probes

Graph cursors can be used to make measurements from waveforms.

To enable select the graph popup Cursors On menu item.

Initially two cursors will appear both positioned at the first point of one of the curves on the graph.

These are pictured below:

   Measurement cursor

   Reference cursor

The reference cursor is moved using the right mouse key. The other cursor is moved with the left key but you must first place the mouse cursor near it otherwise the left key will zoom the graph as it does normally when cursors are off. Use the TAB key to move the measurement cursor to a new curve and control-TAB for the reference cursor. (You can also use the Select Curve menu). A readout of the absolute position of the measurement cursor as well as its relative position to the reference cursor is displayed in a status window at the bottom of the graph.

When in cursor mode the left key has three functions depending on its position i.e. if it is within the measurement cursors area it will move the cursor, if it is in a selection area for an axis (cursor changes to an arrow) it will select that axis and if it is anywhere else it will zoom the graph. This triple function can be confusing and sometimes a little exasperating at first, but experience with it is gained quickly after which it becomes simple and quick to use.

There are four functions which can be used in expressions which return the current positions of the cursors. These are

Xdatum()

Ydatum()

Xcursor()

Ycursor()

Moving cursors along a curve

You can move the cursors along a curve using a number of hot keys. These are summarised below.

F5	Move main cursor to next peak
shift-F5	Move main cursor to previous peak
F6	Move main cursor to next trough
shift-F6	Move main cursor to previous trough
F7	Move reference cursor to next peak
shift-F7	Move reference cursor to previous peak
F8	Move reference cursor to next trough
shift-F8	Move reference cursor to previous trough

These operations can also be accessed from the graph popup menu Move Cursors.


Graph Legend Panel Popup

The legend panel is the panel in the graph window between the toolbar and main graph area. Right click in this area to bring up popup menu.

The following all perform curve measurements.

1 RMS

2 RMS/cycle

3 Mean

4 Mean/cycle

5 Rise Time

6 Fall Time

7 Peak

8 Trough

9 Frequency

The above are just a small selection of the available curve measurement functions. For the remainder use the following menu.

A More Functions...	Opens tree list dialog listing all available curve measurement functions

B Plot|FFT of Selected Curve	Create new FFT of data for selected curve

C Plot|FFT of Selected Curve (Cursor span)
Create new FFT of data for selected curve

D Delete Measurements...	Delete selected curve measurements

E Delete All Measurements	Delete all curve measurements


Graph Toolbar


Graph Window

Graph Toolbar	Editing axes

Windows and Tabbed Sheets

Normally new graphs are created within the same window as a "Tabbed Sheet". A row of tabs will appear at the top of the graph window allowing you select which graph you wish to view. You can also create a new graph window using the menu Probe|New Graph Window. This will create an empty window to which you may add new graphs.


Graph Zooming
Graph Zooming and Scrolling

Graphs and Probes

Zooming with the Mouse

To zoom in on a portion of a graph, place the cursor at the top left of the area you wish to view, press and hold the left mouse key then move cursor to bottom right of area and release left key. The axes limits will be modified appropriately.

To view whole graph again select graph popup Zoom Full or the Zoom Full toolbar button.

Zooming with the Keyboard

F12 to zoom out

shift-F12 to zoom in

Home returns graph to full view. (Same as popup Zoom Full)

Recovering an earlier zoom

Press the toolbar "Undo Zoom" button to recover earlier zoom or scroll positions.

Scrolling with the Keyboard

up, down, left and right cursor keys will scroll the active graph.

Zooming selected axes.

When using the mouse to zoom graphs, all curves on the same grid are normally zoomed together. To zoom only the curve on the selected grid, press and hold the shift key while selecting the zoom area with the mouse.

Notes

If you add a new curve to a graph which has been zoomed, the axes limits will not change to accommodate that curve; if the new curve does not lie within the zoomed area you will not see it. Selecting Zoom Full restores the graph to auto-scaling and the limits will always adjust so that all curves are visible even ones subsequently added.


Graph popups

Edit Curve|Rename Curve...	Change title of selected curve as displayed in legend panel.

Edit Curve|Delete Selected Curves	Delete selected curves

Edit Curve|Hide Selected Curves	This removes selected curves as if they were deleted but can be later recovered with Show Selected Curves

Edit Curve|Show Selected Curves	Show selected curves that were previously hidden

Edit Curve|Move Selected Curves	Move selected curves to a new axis.

New Axis	Create new y-Axis. See Multiple Y-Axis Graphs

New Grid	Create new Grid. See Multiple Y-Axis Graphs

Delete Axis/Grid	Delete selected axis or grid. See Deleting Axes

Edit Axis

Copy to Clipboard|Colour	Copy currently selected graph to windows clipboard. This allows graph image to be pasted into other applications.

Copy to Clipboard|Monochrome

Copy to Clipboard|Colour with markers

Copy to Clipboard|Graph Data	Copies data for selected curves to clipboard in ASCII form.

Change Title...	Changes caption bar and printed title of selected graph window.

Zoom|Full	Restore x and y axes to view full graph. See Graph Zooming.

Zoom|Full Selected Axis	Restore x and y axes to view full graph for selected axis only.

Zoom|In	Increase magnification

Zoom|Out	Decrease magnification

Scroll Left

Scroll Right

Scroll Up

Scroll Down

The follwing scroll selected axes only

Scroll|Left Selected Axis

Scroll|Right Selected Axis

Scroll|Up Selected Axis

Scroll|Down Selected Axis

Cursors On	Switch on graph measurement cursors. See Graph Cursors.

Cursors Off	Switch off graph measurement cursors. See Graph Cursors.

Select Curve	Select curve that carries cursor. Use left button for main cursor and right button for reference cursor.

Show Curve Info	Display information about curve that carries main cursor. Useful for identifying curves in monte carlo run

Move Cursors|Step Main Cursor	Step main cursor to next curve. See Graph Cursors.

Move Cursors|Step Reference Cursor	Step reference cursor to next curve. See Graph Cursors.

The following 8 menus all have hot-key equivalents that are usually more convenient. More info: Graph cursors

Move Cursors|Main Cursor to Next Peak	Hot key F5

Move Cursors|Main Cursor to Prev Peak	Hot key shift-F5

Move Cursors|Main Cursor to Next Trough	Hot key F6

Move Cursors|Main Cursor to Prev Trough	Hot key shift-F6

Move Cursors|Ref. Cursor to Next Peak	Hot key F7

Move Cursors|Ref. Cursor to Prev Peak	Hot key shift-F7

Move Cursors|Ref. Cursor to Next Trough	Hot key F8

Move Cursors|Ref. Cursor to Prev Trough	Hot key shift-F8

Align Cursors	Aligns the two cursors so that they are located at the same vertical location.

Preferences|Curve Thickness...	Specify displayed thickness of curves. Medium is clearest but thin curves draw more rapidly.

Preferences|Print Curve Thickness...	Specify thickness of curves for printing

Preferences|Print Grid Thickness...	Specify Thickness of major grid lines for printing

Preferences|Print Curve Styles...	To distinguish curves on a monochromatic printer, various combinations of curve markers and line styles are used. For a small number of curves one or the other will be used - you can state your preference with this option. For a larger number of curves, both will be used anyway.

Close Sheet	Close current tabbed sheet. If it is the only one, the whole window will close as well.


Graphs and Data Menu

Add Curve...	Opens "Define curve dialog box" to plot results of simulation.

New Graph Sheet	Open new graph sheet in current window

New Graph Window	Open new graph window

Create Noise Output File	Create output file after noise analysis

View Noise Output File	Open noise output file in file viewer.

List Pole-zero/TransferFunction Results	Displays in command shell results of pole-zero or transfer function analysis

Change Data Group...	Change currently selected group. More info: Plotting Previous Results.

Delete Data Group...	Delete simulation results.

Keep Current Data Group	Prevent current group from being automatically purged. More info: Plotting Previous Results


Graphs and Probes
Graphs, Probes and Data Analysis

Creating graphs from the schematic

You can cross probe the schematic in a number of ways to create graphs. Refer to the schematic editor's documentation for full details

Other methods of creating graphs

As well as cross-probing the schematic you can also manually enter an expression relating node voltages and/or device currents. This is covered in the topic Plotting arbitrary expressions

You can also retrieve data created by an earlier run see Plotting results from a previous simulation.

General graph topics

The following topics provide details on operations with the graphs themselves, such as manipulating axes and curves.

Graph layout - multiple y-axis graphs

Curve operations

Graph cursors

Graph zooming and scrolling

Copy to clipboard

Data Analysis

Curve measurements


Group popup
Simulation data is organised into groups each with a name related to the run type. E.g. tran2, ac3, op1 etc.


GroupDelay() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns the group delay of the argument. Group delay is defined as:

where y is the supplied vector and x is its reference. The GroupDelay() function expects the result of AC analysis where y is a voltage or current and its reference is frequency.

This function will yield an error if its argument is complex and has no reference.


Help Menu
Command Shell Help Menu

Help|Contents	Start help system

Help|Tutorial	Start help system, opening the Tutorial topic.

Help|Keyboard	Shows keyboard topic

Help|Menu Reference	Shows Menu Reference topic

Help|Error Messages	Shows Error Messages topic

Help|About...	Display About box. This gives version, copyright and contact information.


Hiding and showing curves

A curve may be hidden without it actually being deleted. This is sometimes useful when there are many curves on a graph but the detail of one you wish to see is hidden by others. In this instance you can temporarily remove the curves from the graph. To hide a curve (or curves) select it (or them) then press "Hide selected curves" button. To show it (or them) again, press "Show selected curves" button.


Histogram() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Vector

Argument 2	Type:	Real only

Compulsory ?:	Yes

Purpose	Number of bins

Return value	Type:	Real

Vector allowed:	Yes

Creates a histogram of argument 1 with the number of bins specified by argument 2. The bins are divided evenly between the maximum and minimum values in the argument.

Histograms are useful for finding information about waveforms that are difficult to determine by other means. They are particularly useful for finding "flat" areas such as the flat tops of pulses as these appear as well defined peaks. The Histogram() function is used in the rise and fall time scripts for this purpose.

User's should note that using this function applied to raw transient analysis data will produce misleading results as the values are unevenly spaced. If you apply this function to simulation data, you must either specify that the simulator outputs at fixed intervals (see .TRAN) or you must interpolate the results using the Interp() function.


IIR() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Vector to be filtered

Argument 2	Type:	Real only

Compulsory ?:	Yes

Purpose	Coefficients

Argument 3	Type:	Real only

Compulsory ?:	No

Purpose	Initial conditions

Default	zero

Return value	Type:	Real

Vector allowed:	Yes

Performs "Infinite Impulse Response" digital filtering on supplied vector. This function performs the operation:

Where:

x is the input vector (argument 1)

c is the coefficient vector (argument 2)

y is the result (returned value)

The third argument provide the "history" of y i.e. y-1, y-2 etc as required.

The operation of this function (and also the FIR() function) is simple but its application can be the subject of several volumes! In principle an almost unlimited range of IIR filtering operations may be performed using this function. Any text on Digital Signal Processing will provide further details.

User's should note that using this function applied to raw transient analysis data will not produce meaningful results as the values are unevenly spaced. If you apply this function to simulation data, you must either specify that the simulator outputs at fixed intervals (see .TRAN) or you must interpolate the results using the Interp() function.

Example

The following graph shows the result of applying a simple first order IIR filter to a step:

The coefficients used give a time constant of 10 * the sample interval. In the above the sample interval was 1Sec so giving a 10Sec time constant. As can be seen a first order IIR filter has exactly the same response as an single pole RC network. A general first order function is:

where

The above example is simple but it is possible to construct much more complex filters using this function. While it is also possible to place analog representations on the circuit being simulated, use of the IIR function permits viewing of filtered waveforms after a simulation run has completed. This is especially useful if the run took a long time to complete.


Iff

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Test

Argument 2	Type:	Any - must be the same as arg 3

Compulsory ?:	Yes

Purpose	Result if test TRUE

Argument 3	Type:	Any - must be the same as arg 2

Compulsory ?:	Yes

Purpose	Result if test FALSE

Return value	Type:	Same as args 2 and 3

Vector allowed:	No

If the first argument evaluates to TRUE (i.e. non-zero) the function will return the value of argument 2. Otherwise it will return the value of argument 3. Note that the type of arguments 2 and 3 must both be the same. No implicit type conversion will be performed on these arguments.


Inductor

Examples

Netlist Entry

Lxxxx N1 N2 value [IC=init_cond]

N1	Node 1

N2	Node 2

value	Value in henries

init_cond	Initial current in inductor. Only effective if UIC option is specified on .tran control.

The above describes the primitive simulator device for an ideal inductor. Easy-SPICE is also shipped with models for saturable inductors. For more info see Non-linear Magnetics.


Inductor Examples
Example:


Inductor with voltage initial condition

Netlist entry:

Axxxx ind_p ind_n model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
ind	Inductor terminals	inout	gd	gd	n/a
Model format:

.MODEL model_name cm_ind parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
l	Inductance	real	none	1e-18 - INF	No	n/a
ic	Current initial condition	real	0	none	No	n/a
Description

This is like a standard inductor but the internal implementation is different and permits the specification of a current initial condition which works without having to specify the transient UIC switch.

In some circumstances, large value inductors are better implemented using this device than the standard inductor but note that during the DC operating point solution, the device looks like an open circuit, not a short circuit as is the case with the normal SPICE device.

Note that this type of inductor cannot be coupled using the 'K' device.


Installing model libraries the easy way

You can install a model library very easily by placing the file or files in the same directory as the standard Easy-SPICE libraries and then renaming them to have the .LB extension. Then in Easy-SPICE select the menu File|Model Library|Rebuild catalog.


Internal Tables

Note: You will need a minimum horizontal resolution of 800 pixels to view this topic.

Internal Resolve In-Out table

outputs	TTL	HC	HCT	FAST	LS	ALS	4000-5	4000-10	4000-15	ECL10K	ECL10E	AC	ACT	FOREC5	UNIV	UNKNOWN
inputs
TTL	OK	OK	OK	OK	OK	OK	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
HC	WARN	OK	OK	WARN	WARN	WARN	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
HCT	OK	OK	OK	OK	OK	OK	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
FAST	OK	OK	OK	OK	OK	OK	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
LS	OK	OK	OK	OK	OK	OK	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
ALS	OK	OK	OK	OK	OK	OK	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
4000-5	WARN	OK	OK	WARN	WARN	WARN	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
4000-10	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ERR	ERR	ERR	ERR	ERR	ERR	OK	ERR
4000-15	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ERR	ERR	ERR	ERR	ERR	OK	ERR
ECL10K	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	OK	ERR	ERR	ERR	OK	ERR
ECL10E	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	OK	ERR	ERR	ERR	OK	ERR
AC	WARN	OK	OK	WARN	WARN	WARN	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
ACT	OK	OK	OK	OK	OK	OK	OK	ERR	ERR	ERR	ERR	OK	OK	OK	OK	ERR
FOREC5	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ERR
UNIV	OK	OK	OK	OK	OK	OK	OK	OK	OK	OK	OK	OK	OK	OK	OK	ERR
UNKNOWN	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR

Internal Resolve in-in table

	TTL	HC	HCT	FAST	LS	ALS	4000-5	4000-10	4000-15	ECL10K	ECL10E	AC	ACT	FOREC5	UNIV	UNKNOWN
TTL	OK	COL	ROW	COL	ROW	ROW	COL	ERR	ERR	ERR	ERR	COL	ROW	ERR	ROW	ERR
HC	ROW	OK	ROW	ROW	ROW	ROW	ROW	ERR	ERR	ERR	ERR	COL	ROW	ERR	ROW	ERR
HCT	COL	COL	OK	COL	COL	COL	COL	ERR	ERR	ERR	ERR	COL	COL	ERR	ROW	ERR
FAST	ROW	COL	ROW	OK	ROW	ROW	COL	ERR	ERR	ERR	ERR	COL	ROW	ERR	ROW	ERR
LS	COL	COL	ROW	COL	OK	ROW	COL	ERR	ERR	ERR	ERR	COL	ROW	ERR	ROW	ERR
ALS	COL	COL	ROW	COL	COL	OK	COL	ERR	ERR	ERR	ERR	COL	ROW	ERR	ROW	ERR
4000-5	ROW	COL	ROW	ROW	ROW	ROW	OK	ERR	ERR	ERR	ERR	COL	ROW	ERR	ROW	ERR
4000-10	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ERR	ERR	ERR	ERR	ERR	ERR	ROW	ERR
4000-15	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ERR	ERR	ERR	ERR	ERR	ROW	ERR
ECL10K	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	COL	ERR	ERR	ERR	ROW	ERR
ECL10E	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ROW	OK	ERR	ERR	ERR	ROW	ERR
AC	ROW	ROW	ROW	ROW	ROW	ROW	ROW	ERR	ERR	ERR	ERR	OK	ROW	ERR	ROW	ERR
ACT	COL	COL	ROW	COL	COL	COL	COL	ERR	ERR	ERR	ERR	COL	OK	ERR	ROW	ERR
FORCE5	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ROW	ERR
UNIV	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	OK	ERR
UNKNOWN	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR
Internal Resolve out-out table

	TTL	HC	HCT	FAST	LS	ALS	4000-5	4000-10	4000-15	ECL10K	ECL10E	AC	ACT	FORCE5	UNIV	UNKNOWN
TTL	OK	ROW	COL	ROW	COL	COL	ROW	ERR	ERR	ERR	ERR	ROW	COL	ERR	ROW	ERR
HC	COL	OK	COL	COL	COL	COL	COL	ERR	ERR	ERR	ERR	ROW	COL	ERR	ROW	ERR
HCT	ROW	ROW	OK	ROW	ROW	ROW	ROW	ERR	ERR	ERR	ERR	ROW	ROW	ERR	ROW	ERR
FAST	COL	ROW	COL	OK	COL	COL	ROW	ERR	ERR	ERR	ERR	ROW	COL	ERR	ROW	ERR
LS	ROW	ROW	COL	ROW	OK	COL	ROW	ERR	ERR	ERR	ERR	ROW	COL	ERR	ROW	ERR
ALS	ROW	ROW	COL	ROW	ROW	OK	ROW	ERR	ERR	ERR	ERR	ROW	COL	ERR	ROW	ERR
4000-5	COL	ROW	COL	COL	COL	COL	OK	ERR	ERR	ERR	ERR	ROW	COL	ERR	ROW	ERR
4000-10	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ERR	ERR	ERR	ERR	ERR	ERR	ROW	ERR
4000-15	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ERR	ERR	ERR	ERR	ERR	ROW	ERR
ECL10K	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ROW	ERR	ERR	ERR	ROW	ERR
ECL10E	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	COL	OK	ERR	ERR	ERR	ROW	ERR
AC	COL	COL	COL	COL	COL	COL	COL	ERR	ERR	ERR	ERR	OK	COL	ERR	ROW	ERR
ACT	ROW	ROW	COL	ROW	ROW	ROW	ROW	ERR	ERR	ERR	ERR	ROW	OK	ERR	ROW	ERR
FORCE5	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	OK	ROW	ERR
UNIV	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	COL	OK	ERR
UNKNOWN	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR	ERR


Interp() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Vector to be interpolated

Argument 2	Type:	Real only

Compulsory ?:	Yes

Purpose	Number of points in result

Argument 3	Type:	Real only

Compulsory ?:	No

Purpose	Interpolation order

Default	2

Return value	Type:	Real only

Vector allowed:	Yes

Returns a vector with length specified by argument 2 obtained by interpolating the vector supplied as argument 1 at evenly spaced intervals. The optional third argument specifies the interpolation order. This can be any integer 1 or greater but in practice there are seldom reasons to use values greater than 4.

The Interp() function overcomes some of the problems caused by the fact that raw transient analysis results are unevenly spaced. It is used by the FFT plotting scripts to provide evenly spaced sample points for the FFT() function. The Interp() function also makes it possible to perform operations on two vectors that originated from different transient runs and therefore will have different sample points.


Inverter

Netlist entry:

Axxxx in out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	n/a
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_inverter parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	HC	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

If the OPEN_C parameter is not specified or is FALSE, this device simply inverts the state of its input. I.e. if the input is logic '0' the output will be logic '1' and vice-versa. If the input is UNKNOWN the output will also be UNKNOWN.

If OPEN_C is TRUE, the output state is always at logic '0' and the input determines its strength. If the input is at logic '1' the output strength is STRONG and if it is at logic '0' the output strength is HI-IMPEDANCE.  The output strength will be UNDETERMINED if the input is UNKNOWN.


IsComplex
IsComplex() function

Functions

Argument 1	Type:	Any

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	No

Returns 1 (=TRUE) if the supplied argument is complex and 0 (=FALSE) if the argument is any other type


JFET Examples
,

Q2 is a 2N3819 with a local temperature of 100°C.


JFET Model parameters

Model syntax:

N channel:

.model modelname NJF ( parameters )

P channel:

.model modelname PJF ( parameters )

Parameters:

The symbols ' × ' and ' ÷ ' in the Area column means that that parameter should be multiplied or divided by the area factor respectively.

Name	Description	Units	Default	Area

VTO	Threshold voltage	V	-2.0

BETA	Transconductance parameter	A/V^2	1e-4	×

BETATCE	BETA temperature coefficient	%	0

LAMBDA	Channel length modulation parameter	1/V	0

RD	Drain ohmic resistance	Ω	0	÷

RS	Source ohmic resistance	Ω	0	÷

CGS	Zero-bias G-S junction capacitance	F	0	÷

CGD	Zero-bias G-D junction capacitance	F	0	÷

Μ	Grading coefficient	1.0

PB	Gate junction potential	V	1

IS	Gate junction saturation current	A	1e-14	×

N	Gate junction emission coefficient	1

XTI	IS temperature coefficient	3

KF	Flicker noise coefficient	0

AF	Flicker noise exponent	1

FC	Coefficient for forward bias depletion
capacitance	0.5

TNOM	Parameter measurement temperature	°C	27


JK Flip Flop

Netlist entry:

Axxxx j k clk set reset out nout model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
j	J input	in	d	d	n/a
k	K input	in	d	d	n/a
clk	Clock	in	d	d	n/a
set	Asynch. set	in	d	d	n/a
reset	Asynch. reset	in	d	d	n/a
out	Data output	out	d	d	n/a
nout	Inverted data output	out	d	d	n/a
Model format:

.MODEL model_name d_jkff parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
clk_delay	Delay from clk	real	1.00E-09	1e-12 - INF	No	n/a
set_delay	Delay from set	real	1.00E-09	1e-12 - INF	No	n/a
reset_delay	Delay from reset	real	1.00E-09	1e-12 - INF	No	n/a
ic	Output initial state	integer	0	0 - 2	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
jk_load	J,k load values (F)	real	1.00E-12	none	No	n/a
clk_load	Clk load value (F)	real	1.00E-12	none	No	n/a
set_load	Set load value (F)	real	1.00E-12	none	No	n/a
reset_load	Reset load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

The following circuit and graph illustrate the operation of this device:

The following table describes the operation of the device when both inputs are at known states: The output can only change on a positive edge of the clock.

J input	K input	Output
0	0	No change
0	1	0
1	0	1
1	1	toggle

When either input is UNKNOWN, the situation is more complicated. There are some circumstances when a known state can be clocked to the output even if one of the inputs is unknown. The following table describes the operation for all possible input states. X means UNKNOWN.

J input	K input	old output	new output
0	0	0	0
0	0	1	1
0	0	X	X
0	1	0	0
0	1	1	0
0	1	X	0
0	X	0	0
0	X	1	X
0	X	X	X
1	0	0	1
1	0	1	1
1	0	X	1
1	1	0	1
1	1	1	0
1	1	X	X
1	X	0	1
1	X	1	X
1	X	X	X
X	0	0	X
X	0	1	1
X	0	X	X
X	1	0	X
X	1	1`	0
X	1	X	X
X	X	0	X
X	X	1	X
X	X	X	X


Junction FET

Model parameters	Examples

Netlist Entry

Jxxxx drain gate source modelname [area] [OFF] [IC=vds,vgs] [TEMP=local_temp]

drain	Drain node

gate	Gate node

source	Source node

modelname	Name of model defined in a .model control. Must begin with a letter but can contain any character except whitespace and ' . ' .

area	Area multiplying factor. Area scales up the device. E.g an area of 3 would make the device behave like 3 transistors in parallel. Default is 1.

OFF	Forces the device to be initially off. The affects the initial guess prior to commencing the DC operating point analysis and is useful to force a particular state for a bistable circuit. See .nodeset for more information.

vds,vgs	Initial conditions for drain-source and gate-source junctions respectively. These only have an effect if the UIC parameter is specified on the .tran control.

local_temp	Local temperature. Overrides specification in .options or .temp control.


Keyboard

The following keys definitions are built in.

Key	Unshifted	Shift	Control	Alt
F1
F2	Step script	Pause script	Resume script
F3	More analysis functions (graph)
F4				Quit/Close window
F5	Cursor to next peak (graph)	Cursor to previous peak (graph)
F6	Cursor to next trough (graph)	Cursor to previous trough (graph)
F7	Ref cursor to next peak (graph)	Ref cursor to previous peak (graph)
F8	Ref cursor to next trough (graph)	Ref cursor to previous trough (graph)
F9
F10	New graph sheet
F11
F12	Zoom out (graph)	Zoom in graph
Insert
Delete
Home	Zoom full (graph)	Zoom full selected axis (graph)
End
Page Up
Page Down
Up	Scroll up (graph)	Scroll up selected axis (graph)
Down	Scroll down (graph)	Scroll down selected axis (graph)
Left	Scroll left (graph)	Scroll left selected axis (graph)
Right	Scroll right (graph)	Scroll right selected axis (graph)
SPACE
TAB	Stem main cursor	Step reference cursor
ESC	Abort macro, cancel operation or pause simulation

In addition, cntrl-C applied in the graph window will copy the graphs graphics to the clipboard.


LTRA Examples

The above could represent a 10 metre length of RG58 cable. The parameters would be described in a .model control e.g.

.model RG58_10m LTRA( R=0.1 C=100p L=250n LEN=10)


LTRA parameter Notes
The uniform RLC/RC/LC/RG transmission line model (LTRA) models a uniform constant-parameter distributed transmission line. The LC case may also be modeled using the lossless transmission line model. The operation of the lossy transmission line model is based on the convolution of the transmission line's impulse responses with its inputs.

The following types of lines have been implemented:

RLC	Transmission line with series loss only

RC	Uniform RC line

LC	Lossless line

RG	Distributed series resistance and parallel conductance

All other combinations will lead to an error.

REL and ABS are model parameters that control the setting of breakpoints. A breakpoint is a point in time when an analysis is unconditionally performed. The more there are the more accurate the result but the longer it will take to arrive. Reducing REL and/or ABS will yield greater precision.


Laplace - Example 1
S-domain transfer block - Example 1

S-domain transfer block

A single pole filter

Model for above device:

.model Laplace s_xfer laplace="1/(s+1)" denormalized_freq=1

Frequency response

This is a simple first order roll off with a 1 second time constant.


Laplace - Example 2
S-domain transfer function - Example 2

S-domain transfer block

Single pole and zero

.model Laplace s_xfer
+ laplace="(1/s)/(1/s + 1/(0.1*s+1))"
+ denormalized_freq=1

The laplace expression has been entered how it might have been written down without any attempt to simplify it. The above actually simplifies to (0.1*s+1)/(1.1*s+1)


Laplace - limitations
S-domain transfer function - limitations

S-domain transfer block

Easy-SPICE expands the expression you enter to create a quotient of two polynomials. If the constant terms of both numerator and denominator are both zero, both are divided by S. That process is repeated until one or both of the polynomials has a non-zero constant term.

The result of this process must satisfy the following:

The order the denominator must be greater than or equal to that of the numerator.

The constant term of the denominator may not be zero.


Laplace - other model parameters
S-domain transfer function - Other model parameters

S-domain transfer block

DENORMALISED_FREQ is a frequency scaling factor.

INT_IC specifies the initial conditions for the device. This is an array of maximum size equal to the order of the denominator. The right-most value is the zeroth order initial condition.

NUM_COEFF and DEN_COEFF are largely redundant but included for compatibility with other XSPICE products. They allow the literal definition of the numerator and denominator coefficients as an array.

GAIN and IN_OFFSET are the DC gain and input offset respectively


Laplace block - Example 3
S-domain transfer block - Example 3

S-domain transfer block

Underdamped second order response

.model Laplace s_xfer

+ laplace="1/(s2+1.1*s+1)"

+ denormalized_freq=2k

The above expression is a second order response that is slightly underdamped. The following graph shows the transient response.


Laplace block - Example 4
S-domain transfer function - Example 4

S-domain transfer block

5th order Chebyshev low-pass filter

The S-domain transfer block has a number of built in functions to implement standard filter response. Here is an example. This is a 5th order chebyshev with -3dB at 100Hz and 0.5dB passband ripple.

.model Laplace s_xfer

+ laplace="chebyshevLP(5,100,0.5)"

+ denormalized_freq=1

and the response:


Laplace expression

S-domain transfer block

The transfer function of the device is defined by the model parameter LAPLACE. This is a text string and must be enclosed in double quotation marks. This may be any arithmetic expression containing the following elements:

Operators:

+ - * / ^

^ means raise to power. Only integral powers may be specified.

Constants

Any decimal number following normal rules. SPICE style engineering suffixes are accepted.

S Variable

This can be raised to a power with '^' or by simply placing a constant directly after it (with no spaces). E.g. s^2 is the same as s2.

Filter response functions

These are:

BesselLP( order, cut-off)	Bessel low-pass

BesselHP( order, cut-off)	Bessel high-pass

ButterworthLP( order, cut-off)	Butterworth low-pass

ButterworthHP( order, cut-off)	Butterworth high-pass

ChebyshevLP( order, cut-off, passband_ripple)	Chebyshev low-pass

ChebyshevHP( order, cut-off, passband_ripple)	Chebyshev high-pass

Where:

order	Integer specifying order of filter. There is no maximum limit but in practice orders larger than about 50 tend to give accuracy problems.

cut-off	-3dB Frequency in Hertz

passband_ripple	Chebyshev only. Passband ripple spec in dB


Level 1,2,3 MOSFET params Notes
Notes:

The three levels 1 to 3 are as follows:

LEVEL 1.	Shichman-Hodges model. The simplest and is similar to the JFET model.

LEVEL 2	A complex model which models the device according to an understanding of the device physics.

LEVEL 3	Simpler than level 2. Uses a semi-empirical approach i.e. the device equations are partly based on observed effects rather than the theory governing its operation.

The L and W parameters perform the same function as the L and W parameters on the device line. If omitted altogether they are set to the option values (set with .options control) DEFL and DEFW respectively. These values in turn default to 100 microns.

The above models differ from all other Easy-SPICE (and SPICE) models in that they contain many geometry relative parameters. The geometry of the device (length, width etc.) is entered on a per component basis and various electrical characteristics are calculated from parameters which are scaled according to those dimensions. This is approach is very much geared towards integrated circuit simulation and is inconvenient for discrete devices. If you are modeling a particular device by hand we recommend you use the level 7 model which is designed for discrete vertical devices.


Level 7 MOSFET parameters

Notes:

The level 7 MOSFET was developed to model discrete vertical MOS transistors rather than the integrated lateral devices that levels 1 to 3 are aimed at. Level 7 is based on level 1 but has the following important additions and changes:

5 new parameters to model gate-drain capacitance

2 new parameters to model rdson variation with temperature.

All parameters are absolute rather than geometry relative. (e.g capacitance is specified in farads not farads/meter)

All MOSFET models supplied with Easy-SPICE are level 7 types. Many models supplied by manufacturers are subcircuits made up from a level 1, 2 or 3 device with additional circuitry to correctly model the gate-drain capacitance. While the latter approach can be reasonably accurate it tends to be slow because of its complexity.

The parasitic reverse diode is not modeled and will need to be added as a separate device if required.

Model syntax:

NMOS:

.model modelname NMOS ( level=7 parameters )

PMOS:

.model modelname PMOS ( level=7 parameters )

Parameters:

Name	Description	Units	Default

VTO or VT0	Threshold voltage	V	0.0

KP	Transconductance parameter	A/V^2	2.0e-5

GAMMA	Bulk threshold parameter	√V	0.0

PHI	Surface potential	V	0.6

LAMBDA	Channel length modulation	1/V	0.0

RD	Drain ohmic resistance	Ω	0.0

RS	Source ohmic resistance	Ω	0.0

CBD	B-D junction capacitance	F	0.0

CBS	B-S junction capacitance	F	0.0

IS	Bulk junction sat. current	A	1.0e-14

PB	Bulk junction potential	V	0.8

CGSO	Gate-source overlap capacitance	F	0.0

CGBO	Gate-bulk overlap capacitance	F	0.0

CJ	Zero bias bulk junction bottom
capacitance	F	0.0

MJ	Bulk junction bottom grading coefficient	0.5

CJSW	Zero bias bulk junction sidewall
capacitance	F	0.0

MJSW	Bulk junction sidewall grading coefficient	0.5

FC	Forward bias depletion capacitance
coefficient	0.5

TNOM	Parameter measurement temperature	°C	27

KF	Flicker noise coefficient	0.0

AF	Flicker noise exponent	1.0

CGDMAX	Max value of gate-drain capacitance	F	0.0

CGDMIN	Min value of gate-drain capacitance	F	0.0

XG1CGD	cgd max-min crossover gradient	1.0

XG2CGD	cgd max-min crossover gradient	1.0

VTCGD	cgd max-min crossover threshold voltage	V	0.0

TC1RD	First order temperature coefficient of rd	1/°C	0.0

TC2RD	Second order temperature coefficient of rd	1/°C^2	0.0


Levels 1, 2 and 3 MOSFET parameters

Notes

Model syntax:

NMOS:

.model modelname NMOS ( level= 1|2|3 parameters )

PMOS:

.model modelname PMOS ( level= 1|2|3 parameters )

Parameters:

Name	Description	Units	Default	Levels

VTO or VT0	Threshold voltage	V	0.0	all

KP	Transconductance parameter	A/V^2	2.0e-5	all

GAMMA	Bulk threshold parameter	√V	0.0	all

PHI	Surface potential	V	0.6	all

LAMBDA	Channel length modulation	1/V	0.0	all

RG	Gate ohmic resistance	Ω	0.0	1 & 3

RD	Drain ohmic resistance	Ω	0.0	all

RS	Source ohmic resistance	Ω	0.0	all

CBD	B-D junction capacitance	F	0.0	all

CBS	B-S junction capacitance	F	0.0	all

IS	Bulk junction sat. current	A	1.0e-14	all

PB	Bulk junction potential	V	0.8	all

CGSO	Gate-source overlap capacitance	F/m	0.0	all

CGDO	Gate-drain overlap capacitance	F/m	0.0	all

CGBO	Gate-bulk overlap capacitance	F/m	0.0	all

RSH	Drain and source diffusion resistance	Ω/square	0.0	all

CJ	Zero bias bulk junction bottom
capacitance/sq-metre of junc. area	F/m^2	0.0	all

MJ	Bulk junction bottom grading coefficient	0.5	all

CJSW	Zero bias bulk junction sidewall
capacitance	F/m	0.0	all

MJSW	Bulk junction sidewall grading coefficient	0.5 (level1)
0.33(level 2 ,3 )	all

JS	Bulk junction saturation current/sq-metre
of junction area	A/m^2	0.0	all

TOX	Oxide thickness	metre	1e-7	all

NSUB	Substrate doping	1/cm^3	0.0	all

NSS	Surface state density	1/cm^2	0.0	all

NFS	Fast surface state density	1/cm^2	0.0	2,3

TPG	Type of gate material:
+1 opposite. to substrate
-1 same as substrate
0 Al gate	all

XJ	Metallurgical junction depth	metre	0.0	2,3

LD	Lateral diffusion	metre	0.0	all

UO	Surface mobility	cm^2/Vs	600	all

UCRIT	Critical field for mobility	V/cm	0.0	2

UEXP	Critical field exponent in mobility
degradation	0.0	2

UTRA	Transverse field coeff (mobility)	0.0	1,3

VMAX	Maximum drift velocity of carriers	m/s	0.0	2,3

NEFF	Total channel charge (fixed and mobile)
coefficient	1.0	2

FC	Forward bias depletion capacitance
coefficient	0.5	all

TNOM	Parameter measurement temperature	°C	27	all

KF	Flicker noise coefficient	0.0	all

AF	Flicker noise exponent	1.0	all

DELTA	Width effect on threshold voltage	0.0	2,3

THETA	Mobility modulation	1/V	0.0	3

ETA	Static feedback	0.0	3

KAPPA	Saturation field factor	0.2	3

W	Width	metre	DEFW	1,2,3
(see notes)

L	Length	metre	DEFL	1,2,3
(see notes)


Library Diagnostics

Device Library and Parts Management - Overview

When enabled, library diagnostics display messages showing the progress of the location of device models.

Library diagnostics are on be default. To switch off, select command shell menu File|Options|General... then Model Library tab.


Library indexing mechanism

Device Library and Parts Management - Overview

This is a technique used to speed the search for models and subcircuits. It is completely transparent and requires no action from the user. Easy-SPICE creates an index file for each library specification (i.e. cache, LibFile option or .lib entries) it encounters. This index files contain details of the file locations of models and subcircuit definitions referenced by the library specification. These index files can then be used for later simulation runs to speed the search for models and subcircuits. Index files are automatically rebuilt if any of the library files referenced are modified. (Modifications are detected by comparing file dates). All index files are named SIMXIDX.n where n is a number from 0 to 999.

In releases earlier than 2.5 these index files were read and checked every time a simulation was run. For very large libraries, this could take several seconds as it checked the file dates of all model files to see if they had been modified. From release 2.5, these indexes are loaded into memory just once when Easy-SPICE starts. Further, the loading of the indexes is performed in the background so that in most cases, by the time a simulation is run, they are already loaded and devices can be located almost instantaneously.

There is however a drawback to this approach. Now that the indexes are loaded only once, no checks are made to detect if any models have changed. This is not a problem if a modification is made to a model already in the index as, if it is actually used in a design, Easy-SPICE will check its date (and if necessary re-index it) when it reads in the model definition. The problem arises when new models are added to a library. Easy-SPICE won't know that they exist and won't find them until the indexes are reloaded. When this happens it will be necessary to manually instruct Easy-SPICE to reload its indexes. This can be done with the menu File|Model Library|Re-build Catalog


Logic families

Digital simulation overview

The digital simulator only knows about the 12 logic states. It doesn't know anything about threshold voltages or output impedances and consequently cannot directly handle the effects of interconnecting devices from different logic families. It does however feature a mechanism of determining the level of compatibility between families and will raise an error if incompatible devices are interconnected. For example, ECL and high speed CMOS operate at completely different thresholds and cannot be connected except via a special interface gate. Easy-SPICE knows this so that if you attempt to connect such devices, an error message will be displayed and the simulation will not run. Conversely, it is perfectly OK to drive an LSTTL input from an HC output and Easy-SPICE will operate normally if you do so. If you drive an HC input from an LSTTL output Easy-SPICE will issue a warning as, although this may work in practice, it cannot be guaranteed to do so under all circumstances.

Another problem arises when connecting inputs from different logic families together. Easy-SPICE deals with this by treating groups of inputs as if they were all from the same logic family provided they are compatible. This selected logic family is then used to resolve any output-input conflict as described above. It is also used to select an analog-digital interface bridge

Groups of outputs from different families are dealt with in the same way as inputs described above.

Easy-SPICE knows how to resolve these situations by referring to a set of three tables called the Logic Compatibility Tables (see below).

Logic Family Model Parameters.

There are three model parameters used to specify the logic family to which a device belongs. These are :

IN_FAMILY	Family for inputs
OUT_FAMILY	Family for outputs
FAMILY	Family for both inputs and outputs if IN_FAMILY/OUT_FAMILY not specified

The parameters are text strings. Any name may be used that is defined in the logic compatibility tables but you must not use the underscore character in a family name. See Supported Logic Families for the families supported by the internal tables.

The underscore character is used to define a sub-family that has the same characteristics as the main family as far as logic compatibility is concerned but which will call a different interface bridge when connected to an analog node. This is used to define schmitt trigger devices such as the 74HC14. In an all-digital circuit this behaves exactly like a normal inverter with a slightly longer delay. When the input is connected to an analog system an interface bridge with the appropriate hysteresis is called up instead of the normal interface.

Logic Compatibility Tables

As explained in the above section, there are three of these. Each table has a row and column entry for each of the logic families supported. These are:

Resolve In-Out table. Decides what to do when an output is connected to an input from a different family. Possible responses are OK, ERR (error - not permissible) and WARN (OK but give warning to user)

Resolve In-In table. Decides how to treat the situation when two inputs from dissimilar families are connected. As described above Easy-SPICE must treat a group of inputs connected together as all belonging to the same logic family for the purpose of deciding an analog interface bridge and to resolve in-out family conflicts. Possible responses are ROW, COLUMN and ERR. ROW means that the family defining the ROW entry has priority and COLUMN means that the family defining the COLUMN entry has priority. ERR means that it is an error to interconnect these two inputs. You can also enter OK which signifies that the two families are equivalent and it doesn't matter which is chosen. Currently this response is exactly equivalent to ROW.

Resolve Out-Out table. Works the same way as the Resolve In-In table but used to define output priorities.

For the tables built-in to the simulator see Internal Tables.

Universal Logic Family

The internal tables support the concept of a "Universal logic family". This is called "UNIV" and can connect to any logic family without error. This is the default if no model FAMILY parameter is supplied.


Logic states

Digital simulation overview

The Easy-SPICE digital simulator is described as "12-state". This means that any digital signal can be in 1 of 12 states. These 12 states are combined from 3 levels and 4 strengths as follows:

Logic levels	Strengths
HIGH	STRONG
LOW	RESISTIVE
UNKNOWN	HI-IMPEDANCE
	UNDETERMINED

Logic levels HIGH and LOW are self-explanatory. UNKNOWN means the signal could be either HIGH or LOW but which is not known at this stage. The start up state of a flip-flop is an example of an UNKNOWN state. Strength refers to the driving force behind the signal. STRONG is the highest with HI-IMPEDANCE the lowest. It is used to resolve conflicts when two outputs are connected together. For example consider a LOW-RESISTIVE signal (as possessed by a pull-down resistor) connected to a HIGH-STRONG signal There is a conflict between the two logic levels but as they are different strengths, the stronger wins and therefore the resulting level is HIGH.

State resolution table

The following table defines how a state is decided when two outputs are connected:

	0S	1S	XS	0R	1R	XR	0Z	1Z	XZ	0U	IU	XU
0S	0S	XS	XS	0S	0S	0S	0S	0S	0S	0S	XS	XS
1S	XS	1S	XS	1S	1S	1S	1S	1S	1S	XS	1S	XS
XS	XS	XS	XS	XS	XS	XS	XS	XS	XS	XS	XS	XS
0R	0S	1S	XS	0R	XR	XR	0R	0R	0R	0U	XU	XU
1R	0S	1S	XS	XR	1R	XR	1R	1R	1R	XU	1U	XU
XR	0S	1S	XS	XR	XR	XR	XR	XR	XR	1U	XU	XU
0Z	0S	1S	XS	0R	1R	XR	0Z	XZ	XZ	0U	XU	XU
1Z	0S	1S	XS	0R	1R	XR	XZ	1Z	XZ	XU	1U	XU
XZ	0S	1S	XS	0R	1R	XR	XZ	XZ	XZ	XU	XU	XU
0U	0S	XS	XS	0U	XU	XU	0U	XU	XU	0U	XU	XU
1U	XS	1S	XS	XU	1U	XU	XU	1U	XU	XU	1U	XU
XU	XS	XS	XS	XU	XU	XU	XU	XU	XU	XU	XU	XU
0S = LOW-STRONG

1S = HIGH-STRONG

XS = UNKNOWN-STRONG

0R = LOW-RESISTIVE

1R = HIGH-RESISTIVE

XR = UNKNOWN-RESISTIVE

0Z = LOW-HI-Z

1Z = HIGH-HI-Z

XZ = UNKNOWN-HI-Z

0U = LOW-UNDETERMINED

1U = HIGH-UNDETERMINED

XU=UNKNOWN-UNDETERMINED


Lossy TRA Model Parameters
Lossy Transmission Line Model Parameters

Notes

Model Syntax:

.model modelname LTRA ( parameters )

Parameters:

Name	Description	Units	Default

R	Resistance/unit length	Ω/unit length	0.0

L	Inductance/unit length	Henrys/unit length	0.0

G	Conductance/unit length	Siemens/unit length	0.0

C	Capacitance/unit length	Farads/unit length	0.0

LEN	Length	Required

These remaining parameters control the way the line is simulated rather than its electrical characteristics. More accurate results ( at the expense of simulation time) can be obtained by using lower values.

REL	Relative rate of change of derivative
for breakpoint	1.0

ABS	Absolute rate of change of derivative
for breakpoint	1.0


Lossy Transmission line

Model Parameters	Examples

Netlist Entry

Oxxxx P1 N1 P2 N2 modelname [IC=v1,i1,v2,i2]

P1	Positive input port 1

N1	Negative input port 2

P2	Positive input port 1

N2	Negative input port 2

modelname	Name of model defined in a .model control. Must begin with a letter but can contain any character except whitespace and ' . ' .

v1,i1,v2,i2	Initial conditions for voltage at port 1, current at port 1, voltage at port 2 and current at port 2 respectively. These only have an effect if the UIC parameter is specified on the .tran control.


MOSFET

Model Parameters

Mxxxx drain gate source bulk modelname [L=length] [W=width] [AD=drain_area] [AS=source_area] [PD=drain_perimeter] [PS=source_perimeter] [NRD=drain_squares] [NRS=source_squares] [OFF] [IC=vds,vgs,vbs] [TEMP=local_temp]

drain	Drain node

gate	Gate node

source	Source node

bulk	Bulk (substrate) node

modelname	Name of model, see Device Library and Parts Management. Must begin with a letter but can contain any character except whitespace and ' . '

(The following 8 parameters are not supported by the level 7 MOSFET model)

length	Channel length (metres).

width	Channel width (metres).

drain_area	Drain area (m^2).

source_area	Source area (m^2).

drain_perimeter	Drain perimeter (metres).

source_perimeter	Source perimeter (metres).

drain_squares	Equivalent number of squares for drain diffusion.

source_squares	Equivalent number of squares for source diffusion.

OFF	Forces the device to be initially off. The affects the initial guess prior to commencing the DC operating point analysis and is useful to force a particular state for a bistable circuit. See .nodeset for more information.

vds, vgs, vbs	Initial condition voltages for drain-source gate-source and bulk(=substrate)-source respectively. These only have an effect if the UIC parameter is specified on the .tran control.

local_temp	Local temperature. Overrides specification in .options or .temp control.

area	Area parameter.

Notes:

All versions of Easy-SPICE support four types of MOSFET model specified in the model definition. These are referred to as levels 1, 2, 3 and 7. Levels 1,2, and 3 are the same as the SPICE2 and SPICE3 equivalents. Level 7 is proprietary to Easy-SPICE. For further information see Level 7 MOSFET parameters.


MOSFET Model Parameters
Levels 1, 2 and 3

Level 7 (Vertical MOS)


Manually creating axes and grids

Multiple Y-axis overview

Two toolbar buttons "Create new grid" and "Create new axis" allow manual creation of new axes and grids. These will be initially empty. Subsequent add curve operations will use the new axis or grid unconditionally as long as it remains selected.


Maxidx() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	No

Returns index of the array element in argument 1 with the largest magnitude.


Maxima() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Vector

Argument 2	Type:	Real only

Compulsory ?:	No

Purpose	minimum value

Default	-

Return value	Type:	Real

Vector allowed:	Yes

Returns array of values holding every maximum point in the supplied vector whose value is above argument 2. The value returned is obtained by fitting a parabola to the maximum and each point either side then calculating the x,y location of the point with zero slope. The vector returned by this function has an attached reference which contains the x values of the maximum points. Note however that the vector is arranged in order of descending y values i.e. largest y value first, smallest last.


Mean1
Mean1() function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Input vector

Argument 2	Type:	Real only

Compulsory ?:	No

Purpose	Start x value

Default	Start of input vector

Argument 3	Type:	Real only

Compulsory ?:	No

Purpose	End x value

Default	End of input vector

Return value	Type:	Real

Vector allowed:	No

Returns the integral of the supplied vector between the ranges specified by arguments 2 and 3 divided by the span (= arg 3 -arg 2). If the values supplied for argument 2 and/or 3 do not lie on sample points, second order interpolation will be used to estimate y values at those points.


Menu Reference

Command Shell Menus

File Menu

Simulator Menu

Graphs and Data Menu

Help Menu

Popup Menus

Graph Popup

Graph Legend Panel Popup


Minima() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Vector

Argument 2	Type:	Real only

Compulsory ?:	No

Purpose	maximum value

Default	+

Return value	Type:	Real

Vector allowed:	Yes

Returns array of values holding every minimum point in the supplied vector whose value is below argument 2. The value returned is obtained by fitting a parabola to the minimum and each point either side then calculating the x,y location of the point with zero slope. The vector returned by this function has an attached reference which contains the x values of the minimum points. Note however that the vector is arranged in order of ascending y values i.e. smallest y value first, largest last.


Mixed-mode Simulator - How it Works

Digital simulation overview

Event Driven Digital Simulator

The digital simulator is said to be "Event Driven". An event is essentially a change of state e.g. a gate output changing from logic '0' to logic '1'. When an event occurs on an output, all devices with inputs connected to that output are notified of the event and can respond appropriately by generating new events.

For example, consider the following circuit fragment.

U1 receives an event, a rising edge at its input at time = T. U1 has a propagation delay of 5.5nS, so on receipt of the event at its input, U1 posts an event at its output with a time T+5.5nS. At that time this event is received by U2 and U3. U3 does not respond to this event because one of its inputs is permanently at logic '1' so its output will always be low. U2, however, does respond and creates a low-high event at a time delayed by its propagation delay of 6.5nS i.e. T+5.5nS+6.5nS. Any device with an input connected to the output of U2 will process this new event and so the process continues.

In addition to the propagation delays described above, there are also additional delays caused by loading effects. Each input has an effective input capacitance and each output a resistance. For each event, an additional delay is added equal to the sum of all capacitances on the node multiplied by the driving output's resistance.

Interfacing to the Analog Simulator

Connections between the analog and digital system are made via special interfaces bridges. (These bridges are implicitly included by the simulator and it isn't necessary for the user to wire them in.) The digital to analog interface has an output that looks like - to a first approximation - an analog representation of a digital gate. This output changes voltage at a specified rise and fall time when the digital input changes state.  More importantly, the analog system is notified when an event occurs at the input to a D-A interface bridge and a timestep is forced at that time. This is known as a breakpoint and is the analog equivalent of an event. The analog system is only notified of events that occur at the input of D-A bridges. It knows nothing of events that are internal to the digital system.

Analog to digital interface bridges are much like a comparator. When the analog input passes a threshold, the output state changes appropriately and a digital event is generated.

Time Step Control

With two simulators running largely independently, something is needed to synchronise the timesteps. Basically the analog system is in control. It tells the digital system to process events up to a certain time, that time being the analog system's next anticipated time point. A problem arises, however in that the next analog timestep is not guaranteed to be accepted. The analog system frequently rejects timesteps either because of slow convergence or because a shorter timestep is needed to maintain the required accuracy. If the analog system has to cut back the timestep to a point prior to the most recent digital event, then the digital system has to back-track. This process is known as roll-back and the need for the digital simulator to be able to perform it substantially increases its complexity. In order to roll-back the digital simulator has to store its past history back to the most recent accepted analog timepoint


Moving curves

Multiple Y-axis overview

You can freely move curves around from one axis or grid to another. Proceed as follows:

Select the curve or curves you wish to move by checking its checkbox next to the coloured legend which designates the curve.

Select the axis you wish to move it to. (See above)

Press the "Move selected curves to new axis" button. The curves will be re-drawn on the new axis. Any axes that become empty as  a result of this operation will be deleted unless it is the "Main" axis. See Deleting axes


Multiple Y-Axis Graphs
Multiple Y-Axes and Grids - Overview

Graphs and Probes

See following topics for further details

"AutoAxis"

Manually creating axes and grids

Moving curves to a different axis or grid

Selecting Axes

Deleting Axes

Graphs may have additional Y axes to accommodate plotting results with incompatible scales. This occurs particularly for plotting dB and phase against each other and also for voltage and current. The additional Y axes may either be superimposed or stacked. In the user interface and in the documentation these are referred to respectively as "Axes" and "Grid". These are illustrated below.

Current and Voltage plotted on separate "Axes"

Current and Voltage plotted on separate "Grids"


Mutual inductor

Specifies coupling between two inductors.

Netlist Entry:

Kxxxx L1 L2 coupling_factor

L1	Component reference of first inductor

L2	Component reference of second inductor

coupling_factor	Coupling factor, K

If mutual inductance is M then:

K cannot be greater than 1.


Nand Gate

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	2 - no upper bound
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_nand parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device operation

If the model parameter OPEN_C is false, The output will be at logic '1' if either input is at logic '0'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '0'.

If the model parameter OPEN_C is true the device will be open collector.  In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '0' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.


Nesting sub-circuits

Overview

Subcircuit definitions may contain both calls to other sub-circuits and local sub-circuit definitions.

If a sub-circuit definition is placed within another sub-circuit definition, it becomes local. That is, it is only available to its "host" sub-circuit.

Calls to sub-circuits may not be recursive. A sub-circuit may not directly or indirectly call its own definition.


Noise Source

noise interval rms_value [start_time [stop_time]]

Source generates a random value at interval with distribution such that spectrum of signal generated is approximately flat up to frequency equal to 1/(2*interval). Amplitude of noise is rms_value volts. start_time and stop_time provide a means of specifying a time window over which the source is enabled. Outside this time window, the source will be zero. If stop_time is omitted or zero a value of infinity will be assumed.

The noise source is a feature of Easy-SPICE and does not form part of standard SPICE.


Nor Gate

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	2 - no upper bound
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_nor parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (pF)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device operation

If the model parameter OPEN_C is false, The output will be at logic '0' if either input is at logic '1'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '1'.

If the model parameter OPEN_C is true the device will be open collector.  In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '1' the output strength will be STRONG. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state.


Open-Collector Buffer

Netlist entry:

Axxxx in out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	n/a
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_open_c parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
open_delay	Open delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
Device Operation

This device is included for compatibility with other XSPICE products. It is recommend that you use the digital buffer for new designs as this supports the additional common parameters such as static input loads and families.

The logic description for the open-collector buffer is described by the following table

Input	Output state	Output strength
0	0	STRONG
1	1	HI-IMPEDANCE
UNKNOWN	UNKNOWN	UNDETERMINED


Open-Emitter Buffer

Netlist entry:

Axxxx in out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	n/a
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_open_e parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
open_delay	Open delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
Device Operation

This device is included for compatibility with other XSPICE products. It is recommend that you use the digital buffer device for new designs as this supports the additional common parameters such as static input loads and families.

The logic description for the open-collector buffer is described by the following table

Input	Output state	Output strength
0	0	HI-IMPEDANCE
1	1	STRONG
UNKNOWN	UNKNOWN	UNDETERMINED


Options Box - File Extensions

Options dialog box

Defines extensions used for the various files used by Easy-SPICE.

Note that the default settings for three file types have five letters rather than the usual three. This is to avoid conflict with other applications where file associations are involved. Some file servers on network systems do not support five letter extensions. If you are using such a system you will need to change these settings.

For each setting, the supported extensions are separated by a semi-colon. The first in the list is the default. So, for example, the default data file extension is sxdat so when you save data without giving an extension, it will automatically be given the extension sxdat

Data Files	Extensions used for simulation data files
Text files	Supported extensions for text files. (File|Scripts|Edit File will list all files with these extensions)
Logic Def. Files	Files used for logic definitions for the arbitrary logic block. If the extension is omitted in the model (FILE parameter) this will be used.
Scripts	Default extension for scripts if called without an extension
Device models	SPICE model files. For future expansion, currently unused.
Device catalogs	Extension for device catalogs used by parts browser system.


Options Box - File Locations

Options dialog box

Locations in your files system of various files and folders needed for correct operation of Easy-SPICE.

Script	Location of script directory. This directory is searched for any scripts you run and is also the location for a number of other files needed for various purposes. Only change this setting if you are actually moving the script directory. Changing this setting has no effect until you restart Easy-SPICE.
Start up	Current working directory on start up.
Temp Data	Location of temporary simulation data files. Changing this setting has no effect until you restart Easy-SPICE.
Built-in Scripts	This is the first location that Easy-SPICE searches for scripts. Much of the user interface is implemented with scripts and these are all internal to the program. These can be overridden by placing scripts of the same name at this location. This allows modification of the UI. Changing this setting has no effect until you restart Easy-SPICE.
Start up Script	Name of script that is automatically run on startup. You can place custom menu or key definitions in this file.
Editor	Text editor called by EditFile command as used by a number of menus. Default is notepad.


Options Box - Graph Printing

Options dialog box

Axis line width	Width in mm of printed axis
Grid line width	Width in mm of printed grid lines
Curve line width	Width in mm of printed curves
Curve identification	When printing on monochrome printers or if "Use markers for colour" is selected, curves are differentiated using different line styles (solid, dashed etc.) and marker shapes (circles, squares etc). For a large number of curves both methods are used but for just a few you can use this option to state your preference
Prefer line styles	Printed curves will first be differentiated using line styles
Prefer curve markers	Printed curves will first be differentiated using curve markers
Use markers for colour	Even if printing to a colour printer, curves will still be printed using markers and variable line styles to differentiate them. They will also be printed in colour. This is useful when creating on-line documents (e.g. using Adobe PDFWriter) which might subsequently be viewed on-line or printed out.


Options Box - Graph/Probe/Data analysis

Options dialog box

Probe update times	Plots created from fixed probes are updated on a regular basis. This controls how frequently and when it starts.
Period	Update period in seconds
Start	Start delay in seconds
Temporary data file delete	Simulation data is stored in data files that are placed in the "Tempdata directory" (see file locations below). These options control when these data files are deleted.
Never	Temporary files are never deleted but will be overwritten in subsequent sessions. Not recommended unless you only ever do short simulations.
When Easy-SPICE starts	All temporary files are deleted when Easy-SPICE starts.
When Easy-SPICE closes	All temporary files are deleted when Easy-SPICE is shut down. While using Easy-SPICE, you can recover earlier simulation runs. Normally, only the 3 most recent are kept but earlier ones can be recovered from the TEMPDATA directory using File|Load Data... .
When data is no longer needed	This is the most aggressive delete method and is recommended if you do many long runs or/and have limited disc space. By default, the 3 most recent runs are kept but with the other options above, the data files are not deleted when the data is not needed but links to the data in them are released. (See explanation below). If this option is set, the data files are deleted as soon as they become out of date, optimising use of disc space at the expense of not being able to recover old data.
FFT Interpolation	See FFT notes
Points	Number of interpolation points to calculate FFT. Default is 1024. Increase to extend frequency range of result (at the expense of calculation time). Increasing this value can also reduce aliasing effects.
Order	Order of interpolation. If signal is smooth and continuous, higher values of interpolation order can improve the result. E.g. if you are looking at low level harmonics in a sinusoid a value of 4 will give good results. If the signal has sharp edges - a pulse for example - you should set this to 1.
Curve weight	Thickness of displayed curves. Curves display much quicker if this value is set to 1 but are clearer (but can lose detail) if set to 2.

How data is stored. For info only

Simulation data is stored in temporary data files as explained above. The data is not read into system memory until it is needed - say - to plot a graph. However, the location in the file of the various vectors is always in memory so that the data can be extracted from the file as rapidly as possible. It is this latter location data that is destroyed when a simulation run gets out of date. The file containing the data gets deleted at a time set by the above options, not necessarily when the data is "no longer needed". As long as the file exists, the data can be recovered by calling File|Load Data which re builds the location data.


Options Box - Model Library

Options dialog box

Library Diagnostics	Determines whether messages are displayed when models are found in the library.
Model read in	"Don't abort on unknown parameters". If cleared, the simulation will abort if models are found that have parameters unsupported by Easy-SPICE


Options Shell/Script
Options Box - Shell/Scripts

Options dialog box

Script Options
Echo all messages	If set, all script lines will be displayed in the message window. This will result in a great deal of output and will slow down the whole program operation. Only set this if you are debugging your own scripts.
Don't abort scripts on error	Normally scripts abort if an error is detected. Check this box to disable this behaviour.
Most recent files	Set the number of recent schematics to be displayed in the File|Reopen menu.
Menu/Keys disable	The built-in menu and key definitions can be disabled, allowing you to define your own. See Defining Keys and Menus for more info on how to do this.
Disable standard menus	Disables menu definitions and any key defined as shortcuts to a menu. Does not take effect until you restart Easy-SPICE.
Disable standard key definitions	Disable key definitions. Note that many of the key assignments are defined as menu shortcuts (their name appears in the menu text). These are not disabled by this option. Does not take effect until you restart Easy-SPICE.


Options and Preferences Overview

Easy-SPICE has a large number of user settable options and preferences. Many can be adjusted from the user interface via menus but a few require setting via the command line. See the following topics for details.

Options dialog box

Colours and fonts


Or Gate

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	2 - no upper bound
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_or parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device operation

If the model parameter OPEN_C is false, The output will be at logic '1' if either input is at logic '1'. Otherwise, if any input is UNKNOWN, the output will be UNKNOWN. Otherwise the output will be at logic '0'.

If the model parameter OPEN_C is true the device will be open collector.  In this case the output logic state is always '0'. The state of the inputs instead determines the strength of the output. If either input is at logic '1' the output strength will be HI-IMPEDANCE allowing a pull-up resistor to force it to the logic '1' state. Otherwise if any input is UNKNOWN the output strength will be UNDETERMINED. Otherwise the output strength will be STRONG.


PSPICE
PSPICE is a registered trademark of Cadence Design Systems Inc.


Passing parameters to subcircuits

Overview of subcircuits

You can pass parameters to a subcircuit This subject is covered in detail in the section on parameters.


Piece wise linear file
Piece Wise Linear File Source

pwlfile filename

This performs the same function as the normal piece wise linear source except that the values are read from a file named filename.

The file contains a list of time voltage pairs in text form separated by any whitespace character (space, tab, newline). It is not necessary to add the '+' continuation character for new lines but they will be ignored if they are included. Any non-numeric data contained in the file will also be ignored.

Notes:

The pwlfile source is considerably more efficient at reading large pwl definitions than the standard pwl source. Consequently it is recommended that all pwl definitions with more than 200 points are defined in this way.

The use of engineering suffixes (e.g. k, m, p etc) is not supported by pwlfile.

The noise source is a feature of Easy-SPICE and does not form part of standard SPICE.


Piece-Wise Linear Source

This applies to both voltage and current sources

pwl ( T1 V1 [T2 V2 [T3 V3 [... ]]] )

Each pair of values (Ti Vi) specifies that the value of the source is Vi at time = Ti. The value of the source at intermediate values of time is determined by using linear interpolation on the input values.

Example:

produces signal:


Plots from Curves

Two plots can be made directly from selected curves. These are described below

FFT of selected curve

With a single curve selected, from legend popup menu select Plot|FFT of Selected Curve. A new graph sheet will be opened with the FFT of the curve displayed

Smoothed curves

With a single curve selected, from legend popup menu select Plot|LP Filter of Selected Curve. A dialog box offering alternative time constants will appear. After selecting one as appropriate, a new curve will be displayed showing original curve low-pass filtered.


Plotting Previous Results
Plotting Results from a Previous Simulation

Graphs and Probes

To Plot the results from a previous simulation:

Select the menu item Graphs and Data|Change Data Group... .

Select the name of the previous run (or group) that you require. The most recent will be at the bottom of the list. (Note that the AC analysis mode generates two groups. One for the ac results and the other for the dc operating point results.)

Plot the result you require in the normal way.

Note

By default, only the three most recent groups are kept. A particular group can be kept permanently using the Graphs and Data|Keep Current Data Group menu item.

Although only three groups are held at a time, the data is actually stored on a disc file which will not necessarily have been deleted. If you wish to access an old run, use File|Load Data... and retrieve the data from the TEMPDATA directory created under the Easy-SPICE install directory. The file will have the same name as the group appended with ".SXDAT". In the case of monte carlo analyses, it will be named MCn.SXDAT. Whether or not the data file is still available depends on a preference setting in the options dialog.


Probes - Plotting arbitrary expressions
Plotting arbitrary expressions

If what you wish to plot is not in one of the probe menus, Easy-SPICE has a facility to plot an arbitrary expression of node voltages or device currents. This can be from the menu

Graphs and Data|Add Curve...

Selecting this menu brings up the "Define Curve" dialog box.

Refer to following topics for full details on using this dialog box

Define Curve Sheet

Axis/Graph Options Sheet

Axis Scales Sheet

Axis Labels Sheet


Probes - changing update period
Changing update period and start delay

The update period of all fixed probes can be changed from the Options dialog box. Select command shell menu File|Options|General... and click on "Graph/Probe/Data analysis". In the "Probe update times/seconds" box there are two values that can be edited. "Period" is the update period and "Start" is the delay after the simulation begins before the curves are first created.


Pulldown Resistor

Netlist entry:

Axxxx out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_pulldown parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
load	Load value (F)	real	0	none	No	n/a
strong	Strong output	boolean	FALSE	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
Device Operation

This is a single terminal device that can provide either a RESISTIVE or STRONG logic '0'. When resistive it can be used for wire-OR connected open emitter outputs. If STRONG is specified (by the STRONG parameter) its main application is as a digital ground connection.


Pullup Resistor

Netlist entry:

Axxxx out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_pullup parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
load	Load value (F)	real	0	none	No	n/a
strong	Strong output	boolean	FALSE	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
Device Operation

This is a single terminal device that can provide either a RESISTIVE or STRONG logic '1'. When resistive it can be used for wire-AND connected open collector outputs. If STRONG is specified (by the STRONG parameter) its main application is as a digital "VCC" connection


Pulse Source

See Also

This applies to both voltage and current sources

pulse( V1  V2  [TD  [TR  [TF  [PW  [PER ]]]]] )

V1	Initial value	Compulsory

V2	Pulsed value	Compulsory

TD	Delay time	Default if omitted = 0

TR	Rise time	Default if omitted, negative or zero = Time step

TF	Fall time	Default if omitted, negative or zero = Time step

PW	Pulse width	Default if omitted or negative = stop time

PER	Period	Default if omitted, negative or zero = stop time

Easy-SPICE deviates from standard SPICE in the action taken for a pulse width of zero. Standard SPICE treats a zero pulse width as if it had been omitted and changes it to the stop time. In Easy-SPICE a zero pulse width means just that.


RMS1() Function

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Input vector

Argument 2	Type:	Real only

Compulsory ?:	No

Purpose	Start x value

Default	Start of input vector

Argument 3	Type:	Real only

Compulsory ?:	No

Purpose	End x value

Default	End of input vector

Return value	Type:	Real

Vector allowed:	No

Returns the root mean square value of the supplied vector between the ranges specified by arguments 2 and 3. If the values supplied for argument 2 and/or 3 do not lie on sample points, second order interpolation will be used to estimate y values at those points.


Random Access Memory

Netlist entry:

Axxxx [ data_in_0 data_in_1 .. data_in_n ] [ data_out_0 data_out_1 .. data_out_n ] [ address_0 address_1 .. address_n ] write_en [ select_0 select_1 .. select_n ] model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
data_in	Data input line(s)	in	d	d	1 - INF
data_out	Data output line(s)	out	d	d	1 - INF
address	Address input line(s)	in	d	d	1 - INF
write_en	Write enable	in	d	d	n/a
select	Chip select line(s)	in	d	d	1 - 16
Model format:

.MODEL model_name d_ram parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
select_value	Decimal active value for select line comparison	integer	1	0 - 32767	No	n/a
ic	Initial bit state @ DC	integer	2	0 - 2	No	n/a
read_delay	Read delay from address/select/write_en active	real	1.00E-07	1e-12 - INF	No	n/a
data_load	Data_in load value (F)	real	1.00E-12	none	No	n/a
address_load	Address line load value (F)	real	1.00E-12	none	No	n/a
select_load	Select load value (F)	real	1.00E-12	none	No	n/a
enable_load	Enable line load value (F)	real	1.00E-12	none	No	n/a
Device Operation

This device is provided for compatibility with other XSPICE products and is not recommended for new designs. In some circumstances, this device can consume large quantities of system (i.e. your PC's) RAM as it uses an inefficient method of storing state history. RAM's can also be implemented using the arbitrary logic block which is much more efficient. An example of a simple 256X8 RAM can be found amongst the supplied example circuits (Examples\ALB_Examples\RAM.sxsch and RAM.ldf).


Range() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Purpose	Vector

Argument 2	Type:	Real only

Compulsory ?:	No

Purpose	Start index

Default	0

Argument 3	Type:	Real only

Compulsory ?:	No

Purpose	End index

Default	vector length - 1

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns a vector which is a range of the input vector in argument 1. The range extends from the indexes specified by arguments 2 and 3. If argument 3 is not supplied the range extends to the end of the input vector. If neither arguments 2 or 3 are supplied, the input vector is returned unmodified.


Re-titling curves

You can change the title of a curve by selecting it then pressing "Name curve" button. This will change the name of the curve as displayed in the legend panel. (Above main graph area and below toolbar)


Ref() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns the reference of the argument.


Removing Model Libraries

Device Library and Parts Management - Overview

Select Model Library|Remove Libraries... .Select the devices you wish to remove from the dialog box.


Resistor

Model Parameters

Netlist Entry

Rxxxx N1 N2 [model_name] value [ TEMP=local_temp] [TC1=tc1] [TC2=tc2]

N1	Node 1

N2	Node 2

model_name	(Optional) Name of model, see Device Library and Parts Management. Must begin with a letter but can contain any character except whitespace and ' . '

value	Resistance (Ω)

local_temp	Resistor temperature (°C)

tc1	First order temperature coefficient

tc2	Second order temperature coefficient


Resistor Model Parameters

Model syntax:

.model modelname RES ( parameters )

Parameters:

Name	Description	Units	Default

R	Resistance multiplier	1

TC1	First order temperature coefficient	1/°C	0

TC2	Second order temperature coefficient	1/°C^2	0


Rms() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns a vector of the accumulative rms value of the input. Unlike RMS1() this function returns a vector which can be plotted.


RootSumOfSquares() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Input vector

Argument 2	Type:	Real only

Compulsory ?:	No

Purpose	Start x value

Default	Start of input vector

Argument 3	Type:	Real only

Compulsory ?:	No

Purpose	End x value

Default	End of input vector

Return value	Type:	Real

Vector allowed:	Yes

Similar to RMS1 function but returns the root of the sum without performing an average.


S-domain Transfer Function Block

Functional modelling overview

Netlist entry:

Axxxx t clk set reset out nout model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	v	v, vd, i, id	n/a
out	Output	out	v	v, vd, i, id	n/a
Model format:

.MODEL model_name s_xfer parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
in_offset	Input offset	real	0	none	No	n/a
gain	Gain	real	1	none	No	n/a
laplace	Laplace expression (overrides num_coeff and den_coeff)	string	none	none	No	n/a
num_coeff	Numerator poly coeff.	real	none	none	Yes	1 - INF
den_coeff	Denominator poly coeff.	real	none	none	Yes	1 - INF
int_ic	Int stage init. cond	real	0	none	Yes	none
denormalized_freq	Frequency (radians/second) at which to denormalize coefficients	real	1	none	No	n/a
Description

Refer to the following topics examples and a full description of this model

Example 1 - A single pole filter

Example 2 - Single pole and zero

Example 3 - Underdamped second order response

Example 4 - 5th order Chebyshev low-pass filter

The Laplace Expression

Other Model Parameters

Limitations

The XSPICE S_XFER model

The Easy-SPICE Laplace transfer model is compatible with the original XSPICE version but the transient analysis portion of it has been completely rewritten. The original XSPICE version was seriously flawed and would only give accurate results if the timestep was forced to be very small. Further, convergence would fail if the device was used inside a feedback loop.

The ability to enter the laplace transform as an arbitrary expression is a Easy-SPICE enhancement. The original version required the user to enter the coefficients of the numerator and denominator explicitly. The filter response functions are also a Easy-SPICE enhancement.


SR Latch

Netlist entry:

Axxxx s r enable set reset out nout model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
s	S input	in	d	d	n/a
r	R input	in	d	d	n/a
enable	Enable	in	d	d	n/a
set	Asynch. set	in	d	d	n/a
reset	Asynch. reset	in	d	d	n/a
out	Data output	out	d	d	n/a
nout	Inverted data output	out	d	d	n/a
Model format:

.MODEL model_name d_srlatch parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
sr_delay	Delay from s or r input change	real	1.00E-09	1e-12 - INF	No	n/a
enable_delay	Delay from clk	real	1.00E-09	1e-12 - INF	No	n/a
set_delay	Delay from set	real	1.00E-09	1e-12 - INF	No	n/a
reset_delay	Delay from reset	real	1.00E-09	1e-12 - INF	No	n/a
ic	Output initial state	integer	0	0 - 2	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
sr_load	S & r load values (F)	real	1.00E-12	none	No	n/a
enable_load	Clk load value (F)	real	1.00E-12	none	No	n/a
set_load	Set load value (F)	real	1.00E-12	none	No	n/a
reset_load	Reset load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

This device is identical to the SR flip flop except that it is level not edge triggered. That is the output may change whenever the enable input is high.


Saving Results of Simulation

You can save the results of a simulation to be restored in a later session

To save the most recent simulation:

Select File|Save Data...

Type in or select a filename. An extension of .sxdat is recommended.

Select OK.

The results saved can later be restored using File|Load Data...

To save a previous simulation:

Select Graphs and Data|Change Data Group...

Select the group (i.e. results of earlier simulation run)

Select OK.

Select File|Save Data...

Type in or select a filename. An extension of .sxdat is recommended.

Select OK.

If you wish to continue plotting results from latest simulation run you should restore the current group using Graphs and Data|Change Data Group....


Scripting: Built-in Scripts

Scripts used by the standard user interface are all embedded in the executable file. These are known as built_in or internal scripts. For a listing of all internal scripts see \SCRIPT\BUILTIN on the installation CD-ROM (Full product only)


Scripting: Vector References
Vector References

Simulation vectors are usually attached to a reference. The reference is a vector's x-values. E.g. any vector created from a transient analysis simulation will have a reference of time. AC analysis results have a reference of Frequency.

Vectors created by other means may be assigned a reference using the SetRef command.


See Also
Using Expressions for Circuit Parameters

.dc


See Also .lib
Device Library and Parts Management - Overview


See Also pulse source
Voltage Source

Current Source


Select Curve Menu

Cursors may be positioned on any curve using the popup menu "Select Curve". Proceed as follows

Switch cursors on

Select Graph popup "Select Curve"

Click left button on desired curve to place main measurement cursor or click right button for reference cursor.

This method is particularly useful in monte carlo analysis where a large number of curves may be present on a graph.


Selecting Axes

Multiple Y-axis overview

Some operations are performed on the selected axis or grid. The selected axis or grid will be displayed with its vertical axis line a deep black while the remaining axes and grids will be light grey. Newly created axes and grids are always selected. To select an axis, click the left mouse button immediately to the left of the vertical axis line.


Selecting Curves


Set-Reset Flip-Flop

Netlist entry:

Axxxx s r clk set reset out nout model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
s	S input	in	d	d	n/a
r	R input	in	d	d	n/a
clk	Clock	in	d	d	n/a
set	Asynch. set	in	d	d	n/a
reset	Asynch. reset	in	d	d	n/a
out	Data output	out	d	d	n/a
nout	Inverted data output	out	d	d	n/a
Model format:

.MODEL model_name d_srff parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
clk_delay	Delay from clk	real	1.00E-09	1e-12 - INF	No	n/a
set_delay	Delay from set	real	1.00E-09	1e-12 - INF	No	n/a
reset_delay	Delay from reset	real	1.00E-09	1e-12 - INF	No	n/a
ic	Output initial state	integer	0	0 - 2	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
sr_load	S,r load values (F)	real	1.00E-12	none	No	n/a
clk_load	Clk load value (F)	real	1.00E-12	none	No	n/a
set_load	Set load value (F)	real	1.00E-12	none	No	n/a
reset_load	Reset load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
open_c	Open collector output	boolean	FALSE	none	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

The SR flip flop is similar to a JK flip flop except that the output is UNKNOWN when both S and R inputs are high. In a JK the output toggles in the same circumstances.

The following table describes the operation of the device when both inputs are at known states: The output can only change on a positive edge on the clock.

S input	R input	Output
0	0	No change
0	1	0
1	0	1
1	1	UNKNOWN

When either input is UNKNOWN, the situation is more complicated. There are some circumstances when a known state can be clocked to the output even if one of the inputs is unknown. The following table describes the operation for possible input states. X means UNKNOWN.

S input	R input	old output	new output
0	0	0	0
0	0	1	1
0	0	X	X
0	1	0	0
0	1	1	0
0	1	X	0
0	X	0	0
0	X	1	X
0	X	X	X
1	0	0	1
1	0	1	1
1	0	X	1
1	1	0	X
1	1	1	X
1	1	X	X
1	X	0	X
1	X	1	X
1	X	X	X
X	0	0	X
X	0	1	1
X	0	X	X
X	1	0	X
X	1	1`	X
X	1	X	X
X	X	0	X
X	X	1	X
X	X	X	X


Show Curve Info Menu

This displays in the message window of the command shell information about the curve that currently possesses the main measurement cursor. In particular it provides information on which run the curve originated from for a monte carlo analysis.


Simulation Times

The following table shows simulation times for various circuits. The number of equations shown gives an idea of the complexity of the circuit.

The circuits are

amp.sch	Example circuit. Open loop amplifier. (43 equations)

driver.sch	Example circuit. Pulse driver circuit designed for infra-red LED's. (13 equations)

switcher.sch	Example circuit. Simple switched mode step-up converter. (24 equations)

psu.sch	Precision high current linear power supply. (Circuit not supplied) (238 equations)

ua727.sch	Circuit used for original SPICE2 development by UC Berkeley.(Circuit not supplied) (62 equations)

mem_plus	Standard benchmark. (from ftp.mcnc.org) 17789 equations, 7474 MOSFETs, 14379 Capacitors

Processor	486DX-33	Pentium 90	AMD K6-233	PIII-500	P4-1.5G
OS	Windows 95	Windows  NT 3.51	Windows NT 4.0	Windows NT 4.0	Windows NT 4.0
amp	5.4	0.65	0.31	0.11
driver	16.9	1.7	0.19	0.081
switcher	6.2	0.53	0.63	0.38
psu	251	44.8	21.0	6.189	3.075
ua727	11.7	1.7	0.781	0.24
mem_plus		17811	8136	2584	1626

The above execution times are in seconds and is the time to run the simulation but does not include the time taken to netlist, annotate and read in the circuit.

Historical Note.

The simulation times for the ua727 circuit listed above are published in the original thesis by L.Nagel on the development of SPICE2. The times quoted are in the region of 22 seconds for a CDC 6400 machine which is a 1970's main frame computer at the time only affordable by prestigious universities and large corporations. Readers might like to compare this figure with those quoted in the table above.


Simulation for the Novice

When measuring a real circuit, you would probably connect up a power source - bench power supply perhaps - maybe also some signal source, then switch it on and take measurements using - probably - an oscilloscope. You can also make adjustments to the circuit and see the effects straight away.

For simulation, you have a choice of analysis modes and not all of them have an exact "real life" equivalent. The analysis mode that most closely resembles the method of bench testing a circuit described above is "Transient Analysis". This performs an analysis over a specified (by you) time period and saves all the results - i.e. all the voltages and currents in the circuit - to your hard disk. The difference between real life testing and simulation is that the simulation is not running all the time. If you want to see the effects of changing a component value, you have to change it then re-run the simulation.

In order to solve the circuit, the simulator has to calculate the voltage at every node at every time point. Disk space is cheap and plentiful so Easy-SPICE saves all these values as well as the device currents. Not all simulators do this, some require you to state in advance what you want saved.

After the run is complete, you can then randomly probe the circuit to look at any voltage, current or device power over the analysis time period. You can also place fixed probes on the circuit before running the analysis which will cause the waveform at that point of the circuit to be automatically be displayed while the simulation is running or optionally after its completion.

Some of the other analysis modes are: AC analysis which performs a frequency sweep, DC sweep which ramps a voltage or current source and noise analysis which calculates total noise at a specified point and which components are responsible for that noise.


Simulator Command Reference
Simulator Control Reference

Alphabetic listing

.ac AC analysis

.alias

.dc DC analysis

.ends End sub-circuit definition

.file and .endf Embed file in netlist.

.ic Set initial condition

.inc Include contents of file

.graph

.keep

.lib Specify library path

.model Device model definition

.name

.nodeset

.noise Noise analysis

.op DC operating point analysis

.options Set simulator option

.param Define parameters

.sens Sensitivity analysis

.subckt Start sub-circuit definition

.temp Set simulation temperature

.tf Transfer function analysis

.trace

.tran Transient analysis


Simulator Menu
Command Shell Simulator Menu

Run Netlist...	Runs a simulation on a previously generated netlist.

Resume	Resume paused simulation.

Pause	Pause currently running simulation.

View Netlist	View most recently created netlist.

Edit Netlist	Edit most recently created netlist.

Show Statistics	Display statistics for most recent simulation.


Single Frequency FM
Single Frequency FM Source

This applies to both voltage and current sources

sffm ( VO VA [FC [MDI [FS ]]] )

VO	Offset (Volts or amps)	Compulsory

VA	Amplitude (Volts or amps)	Compulsory

FC	Carrier frequency (Hz)	Default if omitted or zero = 1/Stop time

MDI	Modulation index	Default if omitted = 0

FS	Signal frequency (Hz)	Default if omitted or zero = 1/Stop time

Defined by:

V(t) = VO +  VA.sin[2.π.FC.t+MDI.sin(2.π.FS.t)]


Sinusoidal Source

This applies to both voltage and current sources

SIN[E] ( vo va  [freq [delay [theta ]]] )

vo	Voltage or current offset	Compulsory

va	Peak voltage or current	Compulsory

freq	Frequency (Hz)	Default if omitted or zero= 1/Stop time

delay	Delay (seconds)	Default if omitted = 0

theta	Damping factor (1/seconds)	Default if omitted = 0

The shape of the waveform is described by:

0 to delay:	vo

delay to Stop time	vo + va.exp(-(t-delay)theta)).sin(2.π.freq(t+delay))

Examples:

The circuit:

gives output of:

The circuit:

gives output of:


State Machine

Netlist entry:

Axxxx [ in_0 in_1 .. in_n ] clk reset [ out_0 out_1 .. out_n ] model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	none
clk	Clock	in	d	d	n/a
reset	Reset	in	d	d	n/a
out	Output	out	d	d	1 - no upper bound
Model format:

.MODEL model_name d_state parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
clk_delay	Delay from CLK	real	1.00E-09	none	No	n/a
reset_delay	Delay from reset	real	1.00E-09	none	No	n/a
state_file	State transition specification file name	string	none	none	No	n/a
reset_state	Default state on RESET & at DC	integer	0	none	No	n/a
input_load	Input loading capacitance (F)	real	1.00E-12	none	No	n/a
clk_load	Clock loading capacitance (F)	real	1.00E-12	none	No	n/a
reset_load	Reset loading capacitance (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a

Notes

Currently this model is unsupported as it has not undergone testing or analysis. It is part of the original XSPICE system and should be compatible with other implementations but this cannot be guaranteed.

The following is an example of a state transition specification file

* This is a simple example of a state machine state file

* It is a 2 bit up down counter with synchronous reset

*Present    Outputs     Inputs              State destination

*State      for state   (reset, up/down)

0           0S  0S      0       0           ->  3

                        0       1           ->  1

                        1       0           ->  0

                        1       1           ->  0

1           0S  1S      0       0           ->  0

                        0       1           ->  2

                        1       0           ->  0

                        1       1           ->  0

2           1S  0S      0       0           ->  1

                        0       1           ->  3

                        1       0           ->  0

                        1       1           ->  0

3           1S  1S      0       0           ->  2

                        0       1           ->  0

                        1       0           ->  0

                        1       1           ->  0

See Examples\Digital_Devices\state_updown.sxsch


Subcircuit Instance

Netlist Entry

Xxxxx n1 n2 n3 ... subcircuit_name [pinnames: pin1 pin2 pin3 ...] [[params]: expression1 expression2 ....]

n1, n2 etc.	Subcircuit nodes

pin1, pin2 etc	Pin names corresponding to pin names on schematic symbol. They need to be specified for cross-probing of subcircuit pin currents to work. The netlister will generate these automatically for all the standard subcircuit symbols.

subcircuit_name	Subcircuit name referred to in subcircuit definition (i.e with .subckt control)

expression1 etc.	Parameter expressions. See Using Expressions For Circuit Parameters.

See sub-circuits for full documentation.


SumNoise() Function

Functions

Identical to RootSumOfSquares() function.


Supported Logic Families

The following logic families are supported by the internal Logic Compatibility Tables.

Family name	Description
TTL	TTL - 74 series
HC	High speed CMOS - 74HC series
HCT	TTL compatible High speed CMOS - 74HCT series
FAST	FAST TTL - 74F series
LS	Low power schottky TTL - 74LS series
ALS	Advanced low power schottky TTL - 74ALS series
4000-5	4000 series CMOS - 5V operation
4000-10	4000 series CMOS - 10V operation
4000-15	4000 series CMOS - 15V operation
ECL10K	ECL 10K series
ECL10KE	ECL Eclipse series
AC	Advanced CMOS - 74AC series
ACT	TTL compatible Advanced CMOS - 74ACT series
FORCE5	Used for 5V VCC rails.
UNIV	Universal family - see below


Switch Model Parameters

Notes:

The voltage controlled switch is a type of voltage controlled resistor. Between VON and VOFF the resistance varies gradually following a cubic law.

Model syntax:

.model modelname VSWITCH ( parameters )

OR

.model modelname SW ( parameters )

Parameters:

Name	Description	Units	Default

RON	On resistance	Ω	1

ROFF	Off resistance	Ω	1/GMIN

VON	Voltage at which switch begins to turn on	V	1

VOFF	Voltage at which switch begins to turn off	V	0


System Requirements

Simulation times

Easy-SPICE requires the following minimum system to run:

486DX 66MHz

16MByte RAM

VGA adapter and monitor

Two button mouse (Three button mouse is advantageous)

20MByte available hard disc space

Windows 95/98, Windows NT 4.0, Windows 2000 .


TRA Examples

The above line has an impedance of 50Ω and a delay of 1μS.


Toggle Flip Flop

Netlist entry:

Axxxx t clk set reset out nout model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
t	Toggle input	in	d	d	n/a
clk	Clock	in	d	d	n/a
set	Asynch. set	in	d	d	n/a
reset	Asynch. reset	in	d	d	n/a
out	Data output	out	d	d	n/a
nout	Inverted data output	out	d	d	n/a
Model format:

.MODEL model_name d_tff parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
clk_delay	Delay from clk	real	1.00E-09	1e-12 - INF	No	n/a
set_delay	Delay from set	real	1.00E-09	1e-12 - INF	No	n/a
reset_delay	Delay from reset	real	1.00E-09	1e-12 - INF	No	n/a
ic	Output initial state	integer	0	0 - 2	No	n/a
rise_delay	Rise delay	real	1.00E-09	1e-12 - INF	No	n/a
fall_delay	Fall delay	real	1.00E-09	1e-12 - INF	No	n/a
t_load	Toggle load value (F)	real	1.00E-12	none	No	n/a
clk_load	Clk load value (F)	real	1.00E-12	none	No	n/a
set_load	Set load value (F)	real	1.00E-12	none	No	n/a
reset_load	Reset load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

The operation of the toggle flip flop is illustrated by the following diagrams. When the T input is high, the output toggles on each rising edge of the clock. If the T input is UNKNOWN the output will be UNKNOWN.


Transmission line
Transmission line (lossless)

Example

Netlist Entry

Txxxx P1 N1 P2 N2 Z0=characteristic_imp [TD=delay] [F=frequency [NL=norm_length]] [rel=rel] [abs=abs]

P1	Positive input port 1

N1	Negative input port 2

P2	Positive input port 1

N2	Negative input port 2

impedance	characteristic impedance

delay	Line delay (Seconds)

frequency	Alternative means of specifying delay=norm_length/frequency

norm_length	See frequency. Default 0.25 if omitted.

TD takes precedence over NL/F. Either TD or F must be specified.

These remaining parameters control the way the line is simulated rather than its electrical characteristics. More accurate results ( at the expense of simulation time) can be obtained by using lower values.

rel	Relative rate of change of derivative for breakpoint

abs	Absolute rate of change of derivative for breakpoint


Tri-State Buffer

Netlist entry:

Axxxx in enable out model_name

Connection details:

Name	Description	Direction	Default type	Allowed types	Vector bounds
in	Input	in	d	d	n/a
enable	Enable	in	d	d	n/a
out	Output	out	d	d	n/a
Model format:

.MODEL model_name d_tristate parameters

Model parameters:

Name	Description	Type	Default	Limits	Vector?	Vector bounds
delay	Delay	real	1.00E-09	1e-12 - INF	No	n/a
input_load	Input load value (F)	real	1.00E-12	none	No	n/a
enable_load	Enable load value (F)	real	1.00E-12	none	No	n/a
family	Logic family	string	UNIV	none	No	n/a
in_family	Input logic family	string	UNIV	none	No	n/a
out_family	Output logic family	string	UNIV	none	No	n/a
out_res	Digital output resistance	real	100	0 - INF	No	n/a
min_sink	Minimum sink current	real	-0.001	none	No	n/a
max_source	Maximum source current	real	0.001	none	No	n/a
sink_current	Input sink current	real	0	none	No	n/a
source_current	Input source current	real	0	none	No	n/a
Device Operation

This is a three terminal buffer device. The output state is equal to the input state and the output strength is determined by the enable input as follows:

Enable	Output Strength
0	HI-IMPEDANCE
1	STRONG
UNKNOWN	UNDETERMINED


UnitVec() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Length of result

Return value	Type:	Real

Vector allowed:	Yes

Returns a vector consisting of all 1's. Argument specifies length of vector.

See Also

Vector()


Using Expressions for Circuit Parameters

It is possible to assign expressions to component values which are evaluated when the circuit is simulated. This has a number of uses. For example you might have a filter design for which several component values affect the roll off frequency. Rather than recalculate and change each component every time you wish to change the roll of frequency it is possible to enter the formula for the component's value in terms of this frequency.

Example:

The above circuit is that of a two pole low-pass filter. C1 is fixed and R1=R2. The design equations are:

R1=R2=2/(2*pi*freq*C1*alpha)

C2=C1*alpha*alpha/4

where freq is the cut off frequency and alpha is the damping factor.

Expressions for device values must be entered enclosed in curly braces ( '{' and '}' ).

Before running the above circuit you must assign values to the variables. This can be done by one of two methods:

1	With Let command from the command line or from a script. (If using a script you must prefix the parameter names with "global:")

2	With the .PARAM control placed in the netlist. If you are using a schematic editor to enter your design, refer to the schematic editor's documentation to find out how to add user entries to the netlist.

Suppose we wish a 1kHz roll off for the above filter. Using the Let command, you would type (or run from a script):

let freq=1k

let alpha=1

let C1=10n

If you then wanted to alter the damping factor to 0.8 you only need to type in its new value:

let alpha=0.8

then re-run the simulator.

Using the .PARAM control, you would enter in the text window:

.PARAM freq 1k

.PARAM alpha 1

.PARAM C1 10n

In many cases the .PARAM approach is more convenient as the value are stored with the schematic.

Example passing parameters to subcircuits.

If the filter example above was implemented as a subcircuit, different values of the parameters freq, alpha and C1 could be passed to each instance of the subcircuit. This allows several filters with differing roll-off frequencies and damping factors to be quickly drawn.

You can set the values of the parameters for each instance of the above subcircuit by appending the expressions to the value property of the symbol in the main circuit separated by a ':'. E.g.:-


VSRC Examples

In the above:

V1 is a fixed 5V source.

V2 has a dc value of 5V and a magnitude of 1 for AC analysis

V3 will produce a pulse -0.1V to 0.1V with 100nS rise and fall times, a 1μS pulse width and a 10μS period.

V4 produces a sine wave of 100kHz frequency with a 5V peak amplitude (i.e 10V p-p) and a 1V offset.

V5 produces a piece wise linear waveform.


Vector() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns a vector with length specified by the argument. The value in each element of the vector equals its index.

See Also

UnitVec()


Voltage controlled current source

Netlist Entry

Gxxxx NOUT+ NOUT- VC+ VC- transconductance

NOUT+	Positive output node

NOUT-	Negative output node

VC+	Positive control node

VC-	Negative control node

transconductance	Output current/Input voltage (Siemens)

SPICE2 polynomial sources are also supported in order to maintain compatibility with commercially available libraries for IC's. (Most Op-amp models for example use several polynomial sources). In general, however the arbitrary source is more flexible and easier to use.

The netlist format for a polynomial source is:

Gxxxx NOUT+ NOUT- poly( num_inputs ) VC1+ VC1- VC2+ VC2- ... polynomial_specification

VC1+ etc.	Controlling nodes

num_inputs	Number of controlling node pairs for source.


Voltage controlled switch

Model Parameters

Netlist Entry

Sxxxx NOUT1 NOUT2 VC+ VC- modelname

NOUT1	Switch node 1

NOUT2	Switch node 2

VC+	Positive control node

VC-	Negative control node

modelname	Name of model, see Device Library and Parts Management. Must begin with a letter but can contain any character except whitespace and ' . ' .


Voltage controlled voltage source

Netlist Entry

Exxxx NOUT+ NOUT- VC+ VC- gain

NOUT+	Positive output node

NOUT-	Negative output node

VC+	Positive control node

VC-	Negative control node

gain	Output voltage/Input voltage

SPICE2 polynomial sources are also supported in order to maintain compatibility with commercially available libraries for IC's. (Most Op-amp models for example use several polynomial sources). In general, however the arbitrary source is more flexible and easier to use.

The netlist format for a polynomial source is:

Exxxx NOUT+ NOUT- poly( num_inputs ) VC1+ VC1- VC2+ VC2- ... polynomial_specification

VC1+ etc.	Controlling nodes

num_inputs	Number of controlling node pairs for source.


Voltage source

Examples

Netlist Entry

Vxxxx N+ N- [DC dcvalue] [AC magnitude [phase]] [transient_spec]

N+	Positive output node

N-	Negative output node

dcvalue	Value of source for dc operating point analysis

magnitude	AC magnitude for AC sweep analysis.

phase	phase for AC sweep analysis

transient_spec	Specification for time varying source. Can be one of following:

Pulse
Piece wise linear
Piece wise linear file
Sine
Exponential
Single frequency FM
Noise


Why Simulate?

Integrated circuit designers have been using analog simulation software for many years. The difficulty of bread-boarding and high production engineering costs have made the use of such software essential.

For discrete designers the case has not been so clear cut. For them prototyping is straightforward, inexpensive and generally provides an accurate assessment of how the final production version of a circuit will behave. By contrast computer simulation has been seen as slow and prone to inaccuracies stemming from imperfect models.

In recent years, however, the simulation of discrete analog circuits has become more viable. This has come about because of the almost relentless advances in CPU power and - to a lesser extent - the increased availability of device models from their manufacturers.

The pressure to reduce product development timescales has meant that for many projects the traditional bread-boarding phase is skipped altogether - with or without simulation - and circuit development is carried out on the first revisions of PCB. The use of simulation on a circuit or parts of a circuit can help to eliminate errors in a circuit design prior to this stage and reduce the number of PCB revisions required before the final production version is reached. Of course, to be useful, the simulation process must therefore not be too time consuming.

Computer simulation, does however, have many more uses. There are some things you can do with a simulator which cannot be achieved with practical approaches. You can remove parasitic elements, you can make non-invasive measurements that are impossible in real-life or you can run components outside of their safe operating area. These abilities make simulation a valuable tool for finding out why a particular design does not behave as expected. If the problem can be reproduced on a simulator then its cause can be much more easily identified. Even if a problem cannot be reproduced then this gives some clues. It means that it is caused by something that is not modeled, a wiring parasitic perhaps.

Simulation is extremely useful for testing ideas at the system level. Sometimes it is not easy to test a concept because the hardware to implement it is very costly or time consuming to build. It may even be that you don't know how to implement the idea in hardware at all. The alternative is to design a model and simulate it with a computer. Once it has been established that the concept is viable then attention can be given to its implementation. If it proves not to be viable, then a great deal of time will have been saved.


XSPICE - Digital delays

Most digital devices have at least one model parameter that specifies a time delay. Unless otherwise noted, all delays are inertial. This means that glitches shorter than the delay time will be swallowed and not passed on. For example, the following waveforms show the input and output of a gate that has a propagation delay of 10nS. The first pulse is only 5nS so does not appear at the output. The second pulse is 20nS so therefore is present at the output delayed by 10nS.

The Buffer device has an optional stored delay parameter that makes possible the specification of pure delays.


XSPICE Digital device common parameters

A number of model parameters are common to most of the digital models. These are described below.

Family Parameters

These identify the logic family to which the input and outputs belong. Most models have three family parameters:

in_family	Specifies family for inputs. If omitted, the input family is specified by the FAMILY parameter
out_family	Specifies family for outputs. If omitted, the output family is specified by the FAMILY parameter
family	Default value for IN_FAMILY and OUT_FAMILY
Output Parameters

out_res	This is used to calculate loading delay. It has dimensions of Ohms so is referred to as a resistance. The additional loading delay is calculated by multiplying OUT_RES by the total capacitative load detected on the node to which the output connects.
min_sink	Used to calculate static loading effects. This is the current that the device is able to sink. Current flowing out of the pin is positive so this parameter is usually negative. If the total sink load current is arithmetically smaller (i.e. more negative) than this parameter then the output will be forced to an UNKNOWN state. This is used to implement fan out limitations in bipolar logic.
max_source	Used to calculate static loading effects. This is the current that the device is able to source. Current flowing out of the pin is positive. If the total source load current is larger than this parameter then the output will be forced to an UNKNOWN state. This is used to implement fan out limitations in bipolar logic.
Input Parameters

sink_current	Current that the input sinks. Positive current flows into the device so this parameter is usually negative. The total of all the input sink currents are added together when a node is in the logic '0' state. If the total sink load current is arithmetically smaller (i.e. more negative) than the MIN_SINK parameter of the device driving the node, then it will be forced to an UNKNOWN state. This is used to implement fan out limitations in bipolar logic.
source_current	Current that the input sources. Positive current flows into the device. The total of all the input source currents are added together when a node is in the logic '1' state. If the total source load current is larger than the MAX_SOURCE parameter of the device driving the node, then it will be forced to an UNKNOWN state. This is used to implement fan out limitations in bipolar logic.


XSPICE variable type connections

In the device references that follow, each has a table titled "Connection Details". Each table has the column entries "Default type" and "Allowed types". The type referred to here is the type of electrical connection e.g. voltage, current, differential or single-ended. Some devices allow some or all of their connections to be specified with a range of types. For example, the analog-digital converter has a single ended voltage input by default. However, using a simple modification to the netlist entry, an ADC can be specified with a differential voltage input or even a differential current. Changing the type of connection involves no changes to the .MODEL control, only to the netlist entry.

The following table lists all the available types. The modifier is the text used to alter a connection type at the netlist level. This is explained below

Description	Modifier
Single ended voltage	%v
Single ended current	%i
Differential voltage	%vd
Differential current	%id
Digital	%d
Grounded conductance (voltage input current output)	%g
Grounded resistance (current input, voltage output)	%h
Differential conductance (voltage input current output)	%gd
Differential resistance (voltage input current output)	%hd

With the models supplied with Easy-SPICE, only the first four in the above table are ever offered as options. The others are used but are always compulsory, and an understanding of their meaning is not necessary to make full use the system.

As well as type, all connections also have a direction. This can be in, out or inout. Voltage, current and digital connections may be in or out while the conductance and resistance connections may only be inout. Voltage inputs are always open circuit, current inputs are always short circuit, voltage outputs always have zero output impedance and current outputs always have infinite output impedance.

The conductance connections are a combined voltage input and current output connected in parallel. If the output is made to be proportional to the input, the connection would be a conductor with a constant of proportionality equal to its conductance, hence the name.

Similarly, the resistance connections are a combined current input and voltage output connected in series. If the output is made to be proportional to the input, the connection would be a resistor with a constant of proportionality equal to its resistance.

Changing Connection Type

If a model allows one or more of its connections to be given a different type, this can be done by preceding the connection entry with the appropriate modifier listed in the table above. For example if you wish to specify a 4 bit ADC with a differential voltage input, the netlist entry would be something like:

A1 %vd ANALOG_INP ANALOG_INN CLOCK_IN [ DATA_OUT_0 DATA_OUT_1 DATA_OUT_2 DATA_OUT_3 ] DATA_VALID ADC_4


XSPICE vector connections

Some models feature an arbitrary number of inputs or/and outputs. For example, an AND gate can have any number of inputs. It would be inflexible to have a separate model for every configuration of AND gate so a method of grouping connections together has been devised. These are known as vector connections. Vector connections are enclosed in square brackets. E.g. the netlist entry for an AND gate is:

Axxxx [ in_0 in_1 .. in_n ] out model_name

The pins in_0 in_1 to in_n form a single vector connection. Any number of pins may be placed inside the square brackets, in fact the same model may be used for devices with different numbers of inputs.

Some devices have a minimum and/or maximum number of pins that may be used in a vector connection. This is known as vector bounds and if they apply will be listed in the vector bounds column of the Connection Details table provided with every device definition.


XY Plots

Normally, when you plot the result of a simulation such as a voltage or current the x-axis values are the sample points of the simulation i.e time for transient analysis and frequency for AC analysis. However, it is also possible to plot two values from a simulation against each other. The most common use of this is to plot Nyquist diagrams where the real and imaginary parts of an ac analysis result are plotted.

To create XY plots, use the Probe|Arbitrary Expression (New graph sheet)... or Probe|Arbitrary Expression (Add to open graph)... menus. This opens the "Define Curve" dialog box that has an option to specify both X and Y expressions. For more details see Plotting arbitrary expressions

To plot a nyquist diagram use the menu Probe AC/Noise|Nyquist - Voltage.... These menus use the functions real() and imag() to access the real and imaginary parts of a complex vector. Note that the results of an AC analysis are always complex.


XY()

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Y vector

Argument 2	Type:	Real only

Compulsory ?:	Yes

Purpose	X vector

Default	Start of input vector

Return value	Type:	Real

Vector allowed:	Yes

Returns a vector with y-values of argument 1and x-values of argument 2. This function provides a means of creating X-Y plots using the .GRAPH control.


abs() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real only

Vector allowed:	Yes

Returns absolute value or magnitude of argument. This function is identical to the mag() function.


atan() Function

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns the arc tangent of its argument in degrees.


cos() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Return cosine of argument in degrees.


db() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real only

Vector allowed:	Yes

Returns 20*log10(mag(argument))


diff() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Return value	Type:	Real only

Vector allowed:	Yes

Returns the derivative of the argument with respect to its reference. If the argument has no reference the function returns the derivative with respect to the argument's index - in effect a vector containing the difference between successive values in the argument.


exp() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns e raised to the power of argument. If the argument is greater than 709.016, an overflow  error occurs.


fft() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Purpose	Vector to be processed

Argument 2	Type:	String only

Compulsory ?:	No

Purpose	Window function

Default	'Hanning'

Return value	Type:	Complex

Vector allowed:	Yes

Performs a Fast Fourier Transform on supplied vector. The number of points used is the next binary power higher than the length of argument1. Excess points are zero-filled. Window used may be 'Hanning' (default) or 'None'.

User's should note that using this function applied to raw transient analysis data will not produce meaningful results as the values are unevenly spaced. If you apply this function to simulation data, you must either specify that the simulator outputs at fixed intervals (see .TRAN) or you must interpolate the results using the Interp() function. (The FFT plotting menu items run a script which interpolate the data if it detects that the results are unevenly spaced. Use of these menus does not require special consideration by the user.)

Note that much better results are obtained if the original data is genuinely evenly spaced and not interpolated. If the fixed interval option is specified for transient analysis, the simulator will actually perform an analysis at the evenly spaced points and good FFT results can be obtained. This is not the case with most other SPICE products which interpolate. Interpolation, introduces errors into FFT results especially at frequencies far removed from fundamental components.


history_window
Message Window

The message window is the window in the command shell below the command line. The majority of messages, including errors and warnings, are displayed here.

You can copy a line of text from the message window to the command line by placing the cursor on the line and either double clicking the left mouse key or pressing the Insert key.

Up to 2000 lines of messages will be retained for viewing at any time.


im() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns imaginary part of argument.


imag() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns imaginary part of argument.


integ() Function

Functions

Argument 1	Type:	Real only

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Integrates the argument with respect to its reference.

The function uses simple trapezoidal integration.

An error will occur if the argument supplied has no reference.


legend panel
The panel in the graph window between the toolbar and main graph area. Note that this panel may be resized by dragging its bottom edge.


length() Function

Functions

Argument 1	Type:	Any

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns the number of elements in the argument. The result will be 1 for a scalar and 0 for an empty value.

The length() function is the only function which will not return an error if supplied with an "empty" value. Empty variables are returned by some functions when they cannot produce a return value. All other functions and operators will yield an error if presented with an empty value and abort any script that called it.


ln() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns the natural logarithm of the argument. If the argument is real and 0 or negative an error will result. If the argument is complex it will return a complex result even if the imaginary part is 0 and the real part negative. An error will always occur if both real and imaginary parts are zero.


log() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Same as ln() function.


log10() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns log to base 10 of argument. If the argument is real and 0 or negative an error will result. If the argument is complex it will return a complex result even if the imaginary part is 0 and the real part negative. An error will always occur if both real and imaginary parts are zero.


mag() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns the magnitude of the argument. This function is identical to the abs() function.


magnitude() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

As mag() function.


mean() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns the average of all values in supplied argument. If the argument is complex the result will also be complex.


minidx() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	No

Returns index of the array element in argument 1 with the smallest magnitude.


Non-linear Magnetics

Easy-SPICE is supplied with a number of models for inductors and transformers that correctly model saturation characteristics. Please refer to the manual for further details.


norm() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns the input vector scaled such that the magnitude of its largest value is unity. If the argument is complex then so will be the return value.


Options dialog box

Options and preferences overview

Using the "Options dialog"

This is invoked with the menu File|Options|General...

Select the following topics for information on each tabbed sheet

Graph Printing

Graph/Probe/Data analysis

Model Library

File Locations

Shell/Scripts

File Extensions


ph() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns the phase of the argument. ph() is identical to phase() and return the phase in degrees

The ph() and phase() functions produces a continuous output i.e. it does wrap from 180 degrees to -180 degrees.


phase() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Identical to ph() function.


phase_rad() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Identical to ph() and phase() functions except that the result is always in radians and does not depend on the setting of the option "degrees".


polynomial_specification
Polynomial Specification

Polynomial controlled sources are supported in Easy-SPICE in order to maintain compatibility with SPICE2 syntax which is used for the majority of commercially available models. For new circuits it is recommended that non-linear controlled sources are implemented using the arbitrary source. The latter is more flexible and easier to understand.

The following is an extract from the SPICE2G.6 user manual explaining polynomial sources.

SPICE 2 Polynomial sources.

SPICE allows circuits to contain dependent sources characterized by any of the four equations

i=f(v) v=f(v) i=f(i) v=f(i)

where the functions must be polynomials, and the arguments may be multidimensional. The polynomial functions are specified by a set of coefficients p0, p1, ..., pn. Both the number of dimensions and the number of coefficients are arbitrary. The meaning of the coefficients depends upon the dimension of the polynomial, as shown in the following examples:

Suppose that the function is one-dimensional (that is, a function of one argument). Then the function value fv is determined by the following expression in fa (the function argument):

fv = p0 + (p1*fa) + (p2*fa^2) + (p3*fa^3) + (p4*fa^4) + (p5*fa^5) + ...

Suppose now that the function is two-dimensional, with arguments fa and fb. Then the function value fv is determined by the following expression:

fv = p0 + (p1*fa) + (p2*fb) + (p3*fa^2) + (p4*fa*fb) + (p5*fb^2) + (p6*fa^3) + (p7*fa^2*fb) + (p8*fa*fb^2) + (p9*fb^3) + ...

Consider now the case of a three-dimensional polynomial function with arguments fa, fb, and fc. Then the function value fv is determined by the following expression:

fv = p0 + (p1*fa) + (p2*fb) + (p3*fc) + (p4*fa^2) + (p5*fa*fb) + (p6*fa*fc) + (p7*fb^2) + (p8*fb*fc) + (p9*fc^2) + (p10*fa^3) + (p11*fa^2*fb) + (p12*fa^2*fc) + (p13*fa*fb^2) + (p14*fa*fb*fc) + (p15*fa*fc^2) + (p16*fb^3) + (p17*fb^2*fc) + (p18*fb*fc^2) + (p19*fc^3) + (p20*fa^4) + ...

Note: if the polynomial is one-dimensional and exactly one coefficient is specified, then SPICE assumes it to be p1 (and p0 = 0.0), in order to facilitate the input of linear controlled sources.


print_time
Time step is the first argument of the .tran simulator control.


re() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns the real part of the complex argument.


real() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns the real part of the complex argument.


rnd() Function

Functions

Argument 1	Type:	Real

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns a vector with each element a random value between 0 and the absolute value of the argument's corresponding element.


see_also_analmodes
Viewing DC operating point results


selected axis
The selected y-axis is a different colour to the remainder. (Default colours:Selected: Black; Unselected: Grey) To select an axis, click left button immediately to the left of the axis.


selected curves


sign() Function

Functions

Argument 1	Type:	Real

Compulsory ?:	Yes

Return value	Type:	Real

Vector allowed:	Yes

Returns 1 if argument is greater than 0 otherwise returns 0.


sin() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Return sine of argument in degrees.


sqrt() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Returns the square root of the argument. If the argument is real and negative, an error will result. If however the argument is complex a complex result will be returned.


stop_time
Stop time is the time at which a transient analysis finishes. It is specified in the second argument of the .tran simulator control. (The first argument if there is only one - see .tran)


Subcircuits

Subcircuits are a method of defining a circuit block which can be referenced any number of times by a single netlist line or schematic device. Subcircuits are the method used to define many device models such as op-amps.

You don't need to know anything about subcircuits unless you wish to define you own device models, perhaps to build up a library of tested blocks for general distribution. If you just wish to enter your circuit in a modular manner it will probably be more appropriate to use the hierarchical features of the schematic editor.

This section explains how to create a subcircuit and how to reference one in a netlist. For the netlist  control syntax see .SUBCKT

Topics:

Creating a sub-circuit manually

Passing parameters

Calling a sub-circuit from a netlist

Nesting sub-circuits

Global Nodes


tan() Function

Functions

Argument 1	Type:	Real or Complex

Compulsory ?:	Yes

Return value	Type:	Real or Complex

Vector allowed:	Yes

Return tan of argument in degrees.