High speed, fuzzy co-processor to implement high-level control in cost-sensitive applications

SGS-THOMSON Microelectronics has developed an 8-bit fuzzy logic co-processor, called W.A.R.P.2.0 (Weight Associative Rule Processor) that allows designers to exploit the benefits of the fuzzy logic approach to implement high level control without requiring a higher performance MCU or DSP.

The TD310 integrates all of the key interface functions such as an adjustable undervoltage lockout circuit, a current sense comparator with an alarm output, an enable input, enhanced latch-up immunity and an op amp that can be used to interface the current sense resistor to an ADC such as is typically built into MCUs. It therefore requires only a minimal number of external passive components, leading to simpler design, reduced PCB area and better reliability than more expensive discrete solutions in a wide variety of motor driving, power switching and high voltage level shifting applications.

The world’s first 8-bit dedicated fuzzy controller, W.A.R.P. 2.0 (STFLWARP20/PL) includes input fuzzification and output defuzzification stages, a high speed inferencing unit, memory banks for storing rules, antecedents and consequents, and control logic to handle the downloading of rules and variables. The result is a flexible chip that delivers high inferencing performance while working either as a co-processor that interfaces directly to all popular microprocessors or as a stand-alone unit.

With a 40MHz clock and the ability to handle up to 8 inputs, 4 outputs and 256 rules, W.A.R.P. 2.0 is ideal for use in applications such as motor control, thermal control, signal and image processing, industrial automation and consumer products.

An important benefit of the W.A.R.P. architecture is the patented SGS-THOMSON technique of storing the Membership Functions in dedicated on-chip memories. In this way, W.A.R.P.2.0 can compute a complete fuzzy process comprising eight inputs, four outputs and 256 rules in just 200 microseconds.

Another key feature of the W.A.R.P.2.0 architecture is that different data structures are used at different stages, so that the data representation is always optimized for the current computation. This overcomes the fact that the data structures most suitable for fuzzification are not well-suited to defuzzification (and vice versa), which is one of the greatest limiting factors in traditional fuzzy architectures.

The new device is fully supported by a powerful and user friendly development system known as the FUZZYSTUDIO 2.0. Using graphical design techniques and sophisticated editing, debugging and compiling tools, FUZZYSTUDIO 2.0 minimises the time taken to design fuzzy logic systems, whether the user is an expert or a first-time user.
December 1996

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