One-chip Primary Rate Controller IC Interfaces PCM bus to 2Mbit/s Link.

SGS-THOMSON Microelectronics has introduced a Primary Rate Controller integrated circuit to replace two-chip solutions, reducing the cost of Integrated Services Digital Network (ISDN) switching systems and central office trunk cards.

Interfacing directly the pulse-code modulation (PCM) multiplex bus to the 2Mbit/s link, the CMOS STLC5432 is suitable for all areas where 2.048Mbit/s PCM transmission is used and provides a one-chip solution from the PCM bus to the transformer in accordance with the Conference on European Post and Telecommunications (CEPT) standards. Additionally, thanks to the flexibility of the circuit it can be used as an ISDN primary access controller compatible with the European Telecom Standards Institute (ETSI) standards, options l & 2.

The STLC5432 interfaces easily to popular link controllers such as the SGS-THOMSON ST5451 High-level Data Link Control (HDLC), MK50H25 X.25 and MK5027 Signaling System Number 7 (SS#7) controllers. Moreover, it includes clock recovery circuitry and on the system side can operate on data rates of 2.048, 4.096 or 8.192Mbit/s in multiplexed applications. Four loopback modes are provided for diagnostics and a variable-length buffer memory allows both jitter compensation and automatic frame & superframe alignment.

Assembled in a PQFP44 package, the STLC5432 is available in sample quantities, with volume production expected to start in the second quarter of 1995.

A demonstration board is available for evaluation of the STLC5432. Containing two STLC5432s and four HDLC controllers, the board connects to two twisted pairs on one side and to digital test equipment on the other, allowing evaluation of all functions. The board is controlled through an IBM PC or compatible using menu-based interactive software.

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