SGS-THOMSON offers 0.35 micron ASIC technology

SGS-THOMSON Microelectronics has announced that it is now releasing onto the general market its CB45000 series of standard cells. Already adopted by several major customers, the CB45000 uses the 0.35 micron HCMOS6 process and up to five levels of metalization to deliver an ultra high performance semi-custom technology with a typical usable gate density of 15000 gates/mm2 including routing and the ability to implement systems with a complexity of over three million equivalent gates. The extensive library of embedded functions includes powerful microcontroller and DSP functions and is perfectly tuned to the needs of today's designs with their emphasis on synthesis, testability and first time silicon success.

A key feature of the HCMOS6 process is the use of salicided active areas, a technique that reduces the source-drain resistance from the hundreds or thousands of Ohms typical of previous technologies to just one or two Ohms. This has important benefits for cell design because it allows the transistor widths to be greatly reduced without loss of drive capability, leading, in turn, to smaller gate areas, lower capacitive loading and reduced power consumption. The CB45000 exploits this reduction in power consumption by selectively using salicided active stripes to distribute power within the basic cells, freeing up some of the first level metal and leading to greater circuit density and enhanced routability.

Another important benefit of the HCMOS6 process is the use of CMP (Chemical Mechanical Polishing) planarization technology. This technique allows a much higher level of planarity between metal layers than previous technologies, substantially eliminating the yield and cost penalties traditionally associated with the use of fourth and fifth layer metalizations. In the CB45000, intra-cell wiring is largely confined to the first metal layer, with the second, third and fourth metal layers dedicated to interconnect wiring and power distribution and the fifth metal layer used for power and clock bussing.

The CB45000 library is optimized for use with state-of-the-art design methodologies, with a huge library of over 500 SSI cells and a rich offering of macrocells and macrofunctions. With its very wide variety of buffers, combinatorial cells and multipower drive cells, the CB45000 library allows the synthesis tool to create an optimized netlist that supports maximum efficiency at the Place and Route stage. The basic library is augmented by macrofunctions such as counters, shift registers and adders and a wide variety of compiled and embedded macrocells.

The compiled cell generators, which include single- and dual-port RAM, ROM and Multipliers, employ a special leaf cell technique that ensures predictable layout and accurate model characteristics and allow the designer to select the optimum trade-off between speed, power and cell area. The application specific megacells allow the customer to access designs that have hitherto been used in proprietary products; examples include mixed mode cells for graphics, data conversion and PLL applications, DSP functions, 1Gbit/s serial transputer links, Viterbi and Reed-Solomon decoders and so on.

Because the CB45000 technology can be used to build extremely complex ASICs, considerable attention has been paid to testability issues. The CB45000 supports the JTAG Boundary Scan and provides the necessary macrocells for both edge- and level-sensitive scan design techniques. Testability is assured at device level with the close coupling of LSSD latch elements, Automatic Test pattern Generation (ATPG) and the high pattern depth tester architecture. Built-in Self Test (BIST) options are also available for the memory generators. At the system level, IEEE 1149.1 is fully supported.

The CB45000 does not use traditional I/O cell design; SGS-THOMSON was one of the pioneers of the emerging "Flexible I/O" approach and the CB45000 features variable bonding and a flexible output transistor scheme based on a pre-defined set of I/O transistor subcells. These subcells can be quickly configured using metalization layers to conform to a variety of I/O specifications whilst maintaining optimal ESD protection and latch-up prevention characteristics.

The bond pad itself is variable in terms of pitch and size and even supports staggered bonding methodologies. The I/O circuitry also includes subcells of specialized transistors that are used to form the slew rate control sections of each I/O line and current spike suppression logic that ensures that conducting transistors are turned off before the opposing set are turned on.

Although the transistors used in the CB45000 core logic have been specifically designed and optimized for operation at 3.3V, the I/O circuitry supports all common interface standards, including LVCMOS, LVTTL, LVDS, PCI, 5V tolerant interfaces and others and the library includes a full set of I/O cells.

For the design of CB45000 products, Cadence, Synopsys and Mentor Graphics products can be used for design capture and simulation, while full support is provided for other third party tools including IKOS, Motive, Crosscheck and Sunrise.

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