PALASM 4.1 MACH FITR - INTERNAL RELEASE (12-21-90)
 (C) - COPYRIGHT ADVANCED MICRO DEVICES INC., 1990

Reading User Design (TRE File)...

Flags Used:             Unplace=False        Max Packing=False
Flags Used:        Expand Small=False         Expand All=False


Reading Device Database ...
*********************************************************
     Mach PLD Fitter - v 1.45          BARREL SHIFTER
*********************************************************

PAIR Analysis...

Pre-Placement & Equation Usage Checks... 
 



*** Timing Analysis for Signals

 Parameter   Min   Max           Signal List (Those having Max delay.)
      Tsu     1     1                 Q0              Q1              Q2 
                                      Q3              Q4              Q5 
                                      Q6              Q7 
      Tco     0     0                 Q0              Q1              Q2 
                                      Q3              Q4              Q5 
                                      Q6              Q7 
      Tcr     1     1                 Q1              Q2              Q3 
                                      Q4              Q5              Q6 
                                      Q7              Q0 
.

 Key:
 Tpd - Combinatorial propagation delay, input to output
 Tsu - Combinatorial setup delay before clock
 Tco - Register clock to combinatorial output
 Tcr - Register thru combinatorial logic to setup
 All delay values are expressed in terms of array passes




*** Device Resource Checks

                Available        Used        Remaining
        Clocks:     2              1              1
          Pins:    38             22             16     ->    57%
     I/O Macro:    32              8             24
   Total Macro:    32              8             24
 Product Terms:   128             80             32     ->    74%
 
MACH-PLD Resource Checks OK!  



Partitioning Design into Blocks...

*** Last Equations Placed in Blocks

Weakly - 


*** Block Partitioning Results

               Array    Macros     # I/O    Buried   Product    Signal
              Inputs    Remain     Macro     Logic    Terms     Fanout
   Block-> A    17        12         4         0        48         8
   Block-> B    17        12         4         0        48         8



*** Block Signal List

Block-> A             Q3              Q2              Q1              Q0 

Block-> B             Q7              Q6              Q5              Q4 


|> INFORMATION F050 - Device Utilization....... *: 68 %
Assigning Resources...



*** Macro Block A


   I/O Macros>              Q0              Q1              Q2              Q3
      Targets>   1( 3)   4( 6)   9(15)  12(18)

             Q0 (A  1) -> (A  1) (B  1)
             Q1 (A  4) -> (A  4) (B  4)
             Q2 (A  9) -> (A  9) (B  9)
             Q3 (A 12) -> (A 12) (B 12)



*** Macro Block B


   I/O Macros>              Q4              Q5              Q6              Q7
      Targets>   1(25)   4(28)   9(37)  12(40)

             Q4 (B  1)?              Q5 (B  4)?              Q6 (B  9)? 
             Q7 (B 12)? 
             Q4 (B  1) ->   Blocked -> Reshuffling SwMtrx
             Q0 -> (A 18)    Moved.
             Q4 -> (A  1) (B 18)
             Q5 (B  4) ->   Blocked -> No Reshuffle Possible

|> ERROR F590 - Connection problem (Wiring Congested) - Q5
             Q6 (B  9) ->   Blocked -> Reshuffling SwMtrx
             Q2 -> (A 20)    Moved.
             Q6 -> (A  9) (B 20)
             Q7 (B 12) ->   Blocked -> No Reshuffle Possible

|> ERROR F590 - Connection problem (Wiring Congested) - Q7



*** Macro Block Inputs


       Inputs>              S0              S1              S2              LD              SE
      Targets>   0(10)   1(11)   2(13)   3(32)   4(33)

             LD (I  3)? 
             S0 (I  0) -> (A 16) (B 16)
             S1 (I  1) -> (A 17) (B 17)
             S2 (I  2) -> (A 19) (B 19)
             SE (I  4) -> (A 21) (B 21)
             LD (I  3) ->   Blocked -> No Reshuffle Possible


       Inputs>              LD              D0              D1              D2
                            D3              D4              D5              D6
                            D7
      Targets>   0(24)   2(26)   3(27)   4(28)   5(29)   6(30)   7(31)   8(36)
                10(38)  11(39)  12(40)  13(41)  14(42)  15(43)

     * Retry Mapping
     * Retry Mapping
     * Retry Mapping
             LD (B  0) -> (A  7) (B  7)
             D0 (B  2) -> (A  5)
             D1 (B  4) -> (A  3)
             D2 (B  5) -> (A  2)
             D3 (B  7) -> (A  0)
             D4 (B  8) -> (B 15)
             D5 (B 10) -> (B 13)
             D6 (B 13) -> (B 10)
             D7 (B 15) -> (B  8)




*** Signals - Tabular Information

          Signal   #   P/N #   (Loc)      Type     Logic  # PT    Blocks
          CLOCK    1    35      I  5   clock pin       .             
             D0    2    26      B  2       input       .           A 
             D1    3    28      B  4       input       .           A 
             D2    4    29      B  5       input       .           A 
             D3    5    31      B  7       input       .           A 
             D4    6    36      B  8       input       .            B
             D5    7    38      B 10       input       .            B
             D6    8    41      B 13       input       .            B
             D7    9    43      B 15       input       .            B
             Q0   10     3      A  1     i/o pin    d-ff    10     AB
             Q1   11     6      A  4     i/o pin    d-ff    10     AB
             Q2   12    15      A  9     i/o pin    d-ff    10     AB
             Q3   13    18      A 12     i/o pin    d-ff    10     AB
             Q4   14    25      B  1     i/o pin    d-ff    10     AB
             Q5   15     0       .?.     i/o pin    d-ff    10     AB
             Q6   16    37      B  9     i/o pin    d-ff    10     AB
             Q7   17     0       .?.     i/o pin    d-ff    10     AB
             S0   18    10      I  0       input       .           AB
             S1   19    11      I  1       input       .           AB
             S2   20    13      I  2       input       .           AB
             SE   21    33      I  4       input       .           AB
             LD   22    24      B  0       input       .           AB
.

 Key:
 P/N # - Pin/Node Number
 .?. - Signal Unplaced
 (Loc) - Macrocell Location (Block & Cell)
 # PT - Number of used product terms in logic
 Blocks- Device blocks driven by signal
 comb - Combinatorial logic function
 d-ff - D-Type Flip-flop
 t-ff - T-Type Flip-flop


*** Signals - Equations Where Used

   Signal Source                   Fanout List
          CLOCK
             D0:             Q0 
               {A}
             D1:             Q1 
               {A}
             D2:             Q2 
               {A}
             D3:             Q3 
               {A}
             D4:             Q4 
               {B}
             D5:             Q5 
               {Þ}
             D6:             Q6 
               {B}
             D7:             Q7 
               {Þ}
             Q0:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             Q1:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             Q2:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             Q3:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             Q4:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             Q5:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             Q6:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             Q7:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             S0:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             S1:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             S2:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             SE:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}

             LD:             Q0              Q1              Q2              Q3 
               :             Q4              Q5              Q6              Q7 
               {AAAA BÞBÞ}




*** Outputs with no feedback

  


*** Feedback Map - BARREL SHIFTER

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O
         | 0|       D3 : 0|     |21| SE                  | 0|     |21| SE  
         | 1|       Q4 : 1|     |20| Q2               Q0 : 1|     |20| Q6  
         | 2|       D2 : 2|     |19| S2                  | 2|     |19| S2  
         | 3|       D1 : 3|     |18| Q0                  | 3|     |18| Q4  
         | 4|       Q1 : 4|     |17| S1               Q1 : 4|     |17| S1  
         | 5|       D0 : 5|     |16| S0                  | 5|     |16| S0  
         '--'          | 6|     |15|                     | 6|     |15: D4  
                    LD : 7|     |14|                  LD : 7|     |14|     
                       | 8|     |13|                  D7 : 8|     |13: D5  
                    Q6 : 9|     |12: Q3               Q2 : 9|     |12: Q3  
                       |10|     |11|                  D6 :10|     |11|     
                       '--+-u--u+--'                     '--+-u--u+--'     




*** Logic Map - BARREL SHIFTER

 Gbl Inp .--.     I/O  .--+--A--+--.  I/O           I/O  .--+--B--+--.  I/O
       S0| 0|          | 0| *   |21|                     | 0| *   |21|     
       S1| 1|       Q0 | 1|10   |20|                  Q4 | 1|10   |20|     
       S2| 2|          | 2| *   |19|                     | 2| *   |19|     
         | 3|          | 3| *   |18|                     | 3| *   |18|     
       SE| 4|       Q1 | 4|10   |17|                     | 4| *   |17|     
    CLOCK| 5|          | 5| *   |16|                     | 5| *   |16|     
         '--'          | 6| .  .|15|                     | 6| .  .|15|     
                       | 7| .  .|14|                     | 7| .  .|14|     
                       | 8| *  *|13|                     | 8| *  *|13|     
                    Q2 | 9|10 10|12| Q3               Q6 | 9|10  *|12|     
                       |10| *  *|11|                     |10| *  *|11|     
                       '--+-u--u+--'                     '--+-u--u+--'     


The Design Doc is  stored in ===> Brl.Rpt
|> WARNING F120 - Marginal Block Partitioning Measure:  (Utilizations) 
%% FITR %% Error Count: 2, Warning Count: 1
%% FITR %% File Processing Terminated. - File: Brl (10 nc)
