ADDRESS
| Rade Koncara 18, 11000 Belgrade, Yugoslavia, (+381-11) 446-1252
|
DATE OF BIRTH
| December 5, 1965, Livno, Bosnia and Herzegovina
|
MARITAL STATUS
| Married, wife Danijela, an economist. Two children, son
Marko (March 9, 1994)
and daughter Marija (December 19, 1995).
|
EDUCATION
| Master degree thesis
"Processor modelling for synthesis in silicon compilation"
expected in the first half of 1996.
B.Sc.EE, School of Electrical Engineering,
University of Belgrade (1992)
|
CURRENT INTERESTS
| VLSI design; microprocessors; computer architecture; SMP and DSM systems;
systems software; programming languages; transaction processing
|
EMPLOYMENT HISTORY
|
(1993-present), Department of Computer Engineering,
School of Electrical Engineering, University of Belgrade,
POB 816, 11000 Belgrade, Yugoslavia
- Research Assistant at the Laboratory for VLSI
- Teaching Associate on courses of Computer Design in VLSI,
Microprocessor Systems, and Computer Architecture
(1991-1993), PC Art, Bulevar Lenjina 6, 11000 Belgrade, Yugoslavia
- Systems analyst, information systems designer and programmer
|
PROFESSIONAL EXPERIENCE / PROJECTS
|
- 64-bit RISC processor model design and development using HDL and
silicon compilation for
NIHON UNISYS,
(Tokyo branch of UNISYS) and
Marubeni Hytech Corp.,
Tokyo, Japan - chief designer
- DSM systems research for ENCORE, Fort Lauderdale, Florida, USA
- Simulator of i860 processor for TD Technologies, Cleveland,
Ohio, USA
- Banking information system design and development for
Vojvodjanska Bank, Belgrade, Yugoslavia and
Dafiment Bank, Belgrade, Yugoslavia
- Manufacturing and process control system design and development for
Belgrade Oil Refinery, Belgrade, Yugoslavia
- Rapid Application Development system design for internal use in
PC Art
- Invited lectures and conference presentations at home and
abroad
|
SKILLS
|
- In depth knowledge of computer architecture and modern microprocessors,
especially Intel range of RISC and CISC microprocessors
- SMP and DSM systems knowledge
- Research and Development expertise
- VLSI processor design and modelling
- Hardware modelling in VHDL and ISP' languages
- Simulation system design
- VLSI CAD and EDA tools
(N.2, Alliance, Tanner, Altera, OrCAD, Spice, etc.)
- Assembly language programming; excellent in i860
assembly language
- Experience in many programming languages (C, C++, Ada, and more)
- CASE tools, Visual Programming tools, and SQL language
- In depth knowledge of DOS, Novell, MSwindows, VMS
and UNIX
- System Administration and interoperability expertise based on multivendor
network systems (DEC ULTRIX, SCO UNIX, SGI IRIX, SunOS, LINUX,...)
|
LANGUAGES
| Fluently speaks, reads, and writes English, French and Russian
|
PERSONAL QUALITIES
|
- hard worker
- pronounced communication/writing skills and eloquence
- high efficiency and (self)organization
- fast reactions and control of non-standard situations
- ability to solve complex problems in short time
- self-confidence
|
SCIENTIFIC PUBLICATIONS RECORD
|
Application notes:
- Z. Petkovic and V. Milutinovic,
"An N.2 Simulator of the Intel i860," Application Note D#004/VM,
TD Technologies, Cleveland, Ohio, USA, January 1994.
- D. Milicev, Z. Petkovic, and V. Milutinovic,
"Using N.2 for Simulation of Cache Memory: Concave Versus Convex
Programming in ISP'," Application Note D#003/VM, TD Technologies,
Cleveland, Ohio, USA, January 1994.
International journal papers:
- V. Milutinovic, Z. Petkovic,
"Ten Lessons Learned from a RISC Design," IEEE Computer,
vol. 28, no. 3, March 1995, pp. 120.
- D. Milicev, Z. Petkovic, D. Raskovic, N. Stefanovic, M. Jelisavcic,
D. Jelic, M. Robal, M. Zivkovic, V. Milutinovic,
"A Synergistic Educational Effort in the Domain of RISC Microprocessor
Architecture and HDL ISP' + N.2 Professional Programming,"
IEEE Transactions on Education, (to be published in 1996/7).
International conference papers:
- Z. Petkovic, V. Milutinovic,
"An Approach to Processor Logic Design Using HDL for Silicon Compilation
," Proceedings of the 20th IEEE International Conference on
Microelectronics MIEL-95, Nis, Yugoslavia, September 12-14, 1995,
pp. 859-862.
- Z. Petkovic, V. Milutinovic,
"Processor Modelling for Silicon Compilation: A Methodology Derived
from Lessons Learned," Proceedings of the IFIP International
Workshop on Logic and Architecture Synthesis,
Grenoble, France,
December 18-19, 1995.
Local conference papers in Serbian:
- Z. Petkovic, "Inverzno projektovanje i860 mikroprocesora za
silicijumsku kompilaciju,"
Zbornik radova XXXVIII konferencije ETRAN, sveska III, Nis,
7-9. juna 1994., strane 31-32.
- V. Milutinovic, D. Milicev, Z. Petkovic, D. Raskovic, N. Stefanovic,
D. Jelic, M. Zivkovic, M. Robal, M. Jelisavcic,
"Sinergizam u nastavi iz oblasti RISC arhitektura i
HDL programiranja," Zbornik radova XXXVIII konferencije ETRAN,
sveska III, Nis, 7-9 juna 1994., strane 23-24.
- Z. Petkovic, "Jedan pristup projektovanju logike RISC
mikroprocesora koriscenjem HDL jezika,"
Zbornik odabranih radova SinfoN, Zlatibor,
28. oktobar-2. novembar 1994., strane 70-75.
- V. Milutinovic, Z. Petkovic,
"Pouke iz silicijumske kompilacije u domenu RISC procesora,"
Zbornik radova YU Info, Brezovica, april 1995.
|
LEISURE
| Literature, theatre, film, music, and sport
|