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CPU Access to Device Registers

The CPU accesses a device register using the mechanism illustrated in Figure 1-2. Access to device registers is always uncached. It is not affected by considerations of cache coherency in any system (see "Cache Use and Cache Coherency").

Figure 1-2 : CPU Access to Device Registers

  1. The address of the device is formed in the Execution unit. It may or may not be an address that is mapped by the TLB.

  2. A device address, after mapping if necessary, always falls in one of the ranges that is not cached, so it passes directly to the system bus.

  3. The device or bus attachment recognizes its physical address and responds with data.
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