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Appendix A: System-specific Issues
This appendix lists the Silicon Graphics functions available for writing device drivers and how those function differ from the functions listed in the IRIX Device Driver Reference Pages .
It contains the following sections:
Although all Silicon Graphics systems share similar architectural elements, there are several significant differences you must recognize when writing device drivers. Despite these differences, it is possible to write a device driver that runs on all Silicon Graphics systems. This appendix outlines the various CPU types used by Silicon Graphics systems and describes the CPU features that can vary. Also listed are the VME-bus addresses and interrupt vectors available for customer use.
Whenever possible, this appendix promotes the use of those IRIX kernel functions that are supported on all Silicon Graphics architectures. The hardware features that can differ across architectures are:
- Data cache write back and invalidation
- Write buffer flushing
- Hardware spinlocks (test and set variables)
- CPU Types
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- Data Cache Write Back and Invalidation
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- Flushing the Write Buffer
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- Registers and Register Optimization
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- Reliable Multiprocessor Spinlocks
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- VME Slave Addressing
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- VME Master Addressing
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- VME-bus Space Reserved for Customer Drivers
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- POWER Indigo2 and POWER CHALLENGE M Drivers
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