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Bus Interfaces
There are several types of bus interfaces available for Silicon Graphics workstations and servers:
- VME-bus interface
- SCSI-bus interface
- EISA-bus interface
- GIO-bus interface
Not all bus interfaces are available on all systems. Table 1-2 lists the bus interfaces available for each Silicon Graphics platform. The individual bus interfaces are discussed briefly below.
Bus Interfaces for Silicon Graphics Platforms
| Product Family | VME | SCSI | EISA | GIO |
|---|
| POWER CHALLENGE/POWER Onyx Series Systems | X | X | | X[2] |
| CHALLENGE/Onyx L and XL Series Systems | X | X | | Xa |
| Crimson Series Systems | X | X | | X[3] |
| Indigo Series Systems | | X | | X |
| CHALLENGE M and Indigo2 Series Systems | | X | X | X |
| CHALLENGE S and Indy Series Systems | | X | | X |
| IRIS-4D/20/30/100/200/300/400 Series Systems | X | X | | |
VME-bus Interface
The VME (VERSA Module Eurocard) bus is an industry-standard bus for interfacing devices. It supports the following features:
- Seven levels of prioritized processor interrupts
- 16-, 24-, 32-, and 64-bit address spaces
- 8-, 16,- 32-, and 64-bit data accesses
- DMA to and from main memory
The VME-bus does not distinguish between I/O and memory space, and it supports multiple address spaces. This feature allows you to put 16-bit devices in the 16-bit space, 24-bit devices in the 24-bit space, and 32-bit devices in the 32-bit space. So you must know which of the three address spaces that the board uses when designing a VME device driver. Most VME systems also support VME-SCSI adapters with two interfaces per board.
IRIX assumes that VME devices are I/O channel resources and that they will relinquish bus access promptly to the MIPS processor. IRIX has no model for multiprocessing on the VME bus. PIO access is much slower than DMA, so you may want to "Just say 'No' to PIO" for better performance.
Note: On some devices, you can use jumpers or switch settings to configure the device to use a particular address space. Some Silicon Graphics systems have DMA-mapping registers to make memory appear contiguous to the VME card.
For additional information on VME-bus operation, see the ANSI/IEEE
1014-1987 Standard.
EISA-bus Interface
The EISA (Extended Industry Standard Architecture) bus standard is an enhancement of the ISA (Industry Standard Architecture) bus standard developed by IBM for the PC/AT. EISA is backward compatible with ISA and expands the ISA data bus from 16 bits to 32 bits and provides 23 more address lines and 16 more indicator and control lines.
The EISA bus supports the following features:
- all ISA transfers
- bus master devices
- burst-mode DMA transfers
- 32-bit memory data and address path
- peer-to-peer card communication
- dynamic bus sizing (i.e., 32-bit bus master to 16-bit memory)
For additional information on EISA-bus operation, see the ANSI/IEEE 1014-1987 Standard.
SCSI-bus Interface
The SCSI-bus is an industry standard I/O bus designed to provide host computers with device independence within a class of devices, such as disk drives, tape drives, and image scanners. SCSI is an acronym for Small Computer System Interface.
All Silicon Graphics systems that run IRIX 5.x or 6.0 provide an interface to at least a single SCSI-bus for peripherals that support the SCSI standard. Your device driver can place commands on the bus by using the SCSI host adapter driver. Systems with POWERchannel(TM) I/O processor boards (IO3) support two SCSI interfaces per POWERchannel board; CHALLENGE systems support up to 32 SCSI interfaces. POWERchannel-2(TM) (IO4) boards support many more SCSI interfaces per board.
Caution: All SCSI devices on a bus should support the connect/disconnect strategy while performing operations that take relatively long periods to perform. However, while the device driver can be configured not to time out, serious system throughput and reliability issues could occur.
Most VME systems also support VME-SCSI adapters with two interfaces per board.
For additional information on SCSI-bus operation, see the ANSI standards X3.131-1986 and X3T9.2/85-52 Rev 4B.
GIO-bus Interface
The GIO-bus is a family of synchronous, multiplexed address-data buses for connecting high-speed devices to main memory and CPU for Silicon Graphics systems. The GIO-bus has three varieties: GIO32, GIO32-bis, and GIO64.
- The GIO32 is a 32-bit, synchronous, multiplexed address-data bus that runs at speeds from 25 to 33 MHz. This bus is found on R3000-based Indigos.
- The GIO32-bis is a 32-bit version of the non-pipelined GIO64 bus or a GIO32 bus with pipelined control signals. This bus is found on R4000-based Indigo and Indy workstations.
- The GIO64 bus is a 64-bit, synchronous, multiplexed address-data bus that can run at speeds up to 33 MHz. It supports both 32- and 64-bit GIO64 devices. GIO64 has two slightly different varieties: non-pipelined for internal system memory, and pipelined for graphics and pipelined GIO64 slot devices. This bus is implemented in the Indigo2 platform.
For additional information on the operation of the GIO bus, see the
GIO Bus Specification.
[2] Requires an IBus to GIO adapter. Not available for custom devices.
[3] Crimson systems with 4GI adapters support GIO-bus graphics.
Not available for custom devices.
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