Processor differences

This assembler programming site deals with the older ARM processors - the ARM 2 and the ARM 3. Well written code should work on later ARM processors, including the StrongARM.

• ARM 2
  The processor within the first RISC OS machines. For a brief time the ARM 2 also powered Arthur; but in the words of STEPS, that one is Better Best Forgotten. :-)

• Next came the ARM 3
  This processor greatly boosted the behaviour of RISC OS due to a 4K cache.
  An extra opcode was added, SWP which swaps between registers and memory.
  Additionally, co-processor register 15 is used to communicate with the processor for things such as reading its version number.

• ARM 250
  This was created for the A30x0 series. The actual chip contains the entire ARM chipset in one package (MEMC, VIDC, IOC, and ARM).
  The ARM within this package is an ARM 250. It is a version of the ARM 3 without the co-processor register or the cache. It was designed to be cheap, the A30x0 series being to the Archimedes like the Electron was to the BBC micro.

To determine which processor you have, you need to conduct a few tests:

  Does it understand SWP?
    If not, it is an ARM 2

  Does it understand CP15 instructions?
    If not, it is an ARM 250.

  It is an ARM 3.

• If the ARM3Support module is present, an ARM 3 processor is in use...
  Set Arm3$Present Yes
RMEnsure ARM3Support 0.00 Set ARM3$Present No

Here is some code to determine the processor type:

REM Processor type
REM
REM by Richard Murray 26th April 1999
REM
REM Downloaded from: http://www.heyrick.co.uk/assembler/

DIM code% 256

FOR loop% = 0 TO 2 STEP 2
  P% = code%
  [ OPT loop%

    STMFD   R13!, {R1-R12, R14}              ; Preserve registers

    MOV     R0, #1                           ; Set up a handler for
    ADR     R1, unknown_instruction          ; unknown instructions
    MOV     R2, #0
    MOV     R3, #0
    SWI     "OS_ChangeEnvironment"

    SWI     "OS_EnterOS"                     ; Enter SVC mode

    MOV     R0, #2

    \ Test for ARM 250 or better.
    ADR     R2, safe_word                    ; Make R2 point somewhere safe
    EQUD    &E1021091                        ; "SWP R1, R1, [R2]"
    MOV     R0, #250

    \ Test for ARM 3.
    CMP     R0, #250                         ; Compare R0 with 250.
    EQUD    &EE101F10                        ; "MRCEQ CP15, 0, R1, C0, C0"
    MOV     R0, #3

    TSTP    PC, #&F0000000                   ; Return to USR mode.
    MOV     R0, R0

    LDMFD   R13!, {R1-R12, PC}^              ; Restore registers and exit.

  .unknown_instruction
    ADDS    PC, R14, #4                      ; Upon unknown instruction, skip
                                             ; PC on beyond the MOV instruction.
  .safe_word
    EQUD    0

  ]
NEXT

a% = USR(code%)

CASE a% OF
  WHEN   2 : PRINT "Running on an ARM 2"
  WHEN 250 : PRINT "Running on an ARM 250"
  WHEN   3 : PRINT "Running on an ARM 3"
OTHERWISE  : PRINT "Running on unknown processor (reply = "+STR$(a%)+")"
ENDCASE

END

This software has only been tested on an ARM 3 processor.