Int 02  - External Hardware - Non-maskable Interrupt                       [H]

Desc:  generated by the CPU when the input to the NMI pin is asserted

Notes: return address points to start of interrupted instruction on 80286+
   on the 80286+, further NMIs are disabled until the next IRET
     instruction, but one additional NMI is remembered by the hardware
     and will be serviced after the IRET instruction reenables NMIs
   maskable interrupts may interrupt the NMI handler if interrupts are
     enabled
   although the Intel documentation states that this interrupt is
     typically used for power-failure procedures, it has many other uses
     on IBM-compatible machines:
       Memory parity error: all except Jr, CONV, and some machines
               without memory parity
       Breakout switch on hardware debuggers
       Coprocessor interrupt: all except Jr and CONV
       Keyboard interrupt: Jr, CONV
       I/O channel check: CONV, PS50+
       Disk-controller power-on request: CONV
       System suspend: CONV
       Real-time clock: CONV
       System watch-dog timer, time-out interrupt: PS50+
       DMA timer time-out interrupt: PS50+
       Low battery: HP 95LX
       Module pulled: HP 95LX