03F8-03FF ---- serial port (8250, 8251, 16450, 16550), same as 02F8 and 0378


03F8   w   serial port, transmitter holding register, which contains the
       character to be sent. Bit 0 is sent first.
        bit 7-0   data bits when DLAB=0 (Divisor Latch Access Bit)
   r   receiver buffer register, which contains the received character
       Bit 0 is received first
        bit 7-0   data bits when DLAB=0 (Divisor Latch Access Bit)
   r/w divisor latch low byte when DLAB=1

03F9   r/w divisor latch high byte when DLAB=1
   r/w interrupt enable register when DLAB=0
        bits 7-4   reserved
        bit 3 = 1  modem-status interrupt enable
        bit 2 = 1  receiver-line-status interrupt enable
        bit 1 = 1  transmitter-holding-register empty interrupt enable
        bit 0 = 1  received-data-avail.int. enable (and 16550 timeout)

         - 16550 will interrupt if data exists in the FIFO and isn't read
       within the time it takes to receive four bytes or if no data is
       received within the time it takes to receive four bytes

03FA   r   interrupt identification register. Information about a pending
       interrupt is stored here. When the ID register is addressed,
       the highest priority interrupt is held, and no other interrupts
       are acknowledged until the CPU services that interrupt.
        bit 7-6 = 00  reserved on 8250, 8251, 16450
            = 11  if FIFO queues are enabled (16550 only)
        bit 5-4 = 0 reserved
        bit 3   = 0 reserved  8250, 16450
            = 1 16550  timeout int. pending
        bit 2-1 identify pending interrupt with the highest priority
         = 11  receiver line status interrupt. priority=highest
         = 10  received data available register interrupt. pr.=second
         = 01  transmitter holding register empty interrupt. pr.=third
         = 00  modem status interrupt. priority=fourth
        bit 0 = 0  interrupt pending. contents of register can be used
               as a pointer to the appropriate int.service routine
            1  no interrupt pending

         - interrupt pending flag uses reverse logic, 0=pending, 1=none
         - interrupt will occur if any of the line status bits are set
         - THRE bit is set when THRE register is emptied into the TSR


03FA   w   16650 FCR  (FIFO Control Register)
        bit 7-6 = 00  1 byte
            = 01  4 bytes
            = 10  8 bytes
            = 11 14 bytes
        bit 5-4 = 00 reserved
        bit 3   = 1  change RXRDY  TXRDY pins from mode 0 to mode 1
        bit 2   = 1  clear XMIT FIFO
        bit 1   = 1  clear RCVR FIFO
        bit 0   = 1  enable clear XMIT and RCVR FIFO queues

         - bit 0 must be set in order to write to other FCR bits
         - bit 1 when set  the RCVR FIFO is cleared and this bit is reset
        the receiver shift register is not cleared
         - bit 2 when set  the XMIT FIFO is cleared and this bit is reset
        the transmit shift register is not cleared

03FB   r/w line control register
        bit 7 = 1  divisor latch access bit (DLAB)
            0  receiver buffer, transmitter holding, or interrupt
               enable register access
        bit 6 = 1  set break enable. serial ouput is forced to spacing
               state and remains there.
        bit 5 =    stick parity
        bit 4 = 1  even parity select
        bit 3 =    parity enable
            1  even number of ones are sent and checked in the
               data word bits and parity bit
            0  odd number of ones are sent and checked
        bit 2 = 0  one stop bit
            1  zero stop bit
        bit 1-0 00 word length is 5 bits
            01 word length is 6 bits
            10 word length is 7 bits
            11 word length is 8 bits

03FC   r/w modem control register
        bit 7-5 = 0  reserved
        bit 4 = 1  loopback mode for diagnostic testing of serial port
               output of transmitter shift register is looped back
               to receiver shift register input. In this mode
               transmitted data is received immediately so that
               the CPU can verify the transmit data/receive data
               serial port paths.
        bit 3 = 1  auxiliary user-designated output 2
        bit 2 = 1  auxiliary user-designated output 1
        bit 1 = 1  force request-to-send active
        bit 0 = 1  force data-terminal-ready active

03FD   r   line status register
        bit 7 = 0  reserved
        bit 6 = 1  transmitter shift and holding registers empty
        bit 5 = 1  transmitter holding register empty. Controller is
               ready toaccept a new character to send.
        bit 4 = 1  break interrupt. the received data input is held in
               in the zero bit state longer than the time of start
               bit + data bits + parity bit + stop bits.
        bit 3 = 1  framing error. the stop bit that follows the last
               parity or data bit is a zero bit.
        bit 2 = 1  parity error. Character has wrong parity
        bit 1 = 1  overrun error. a character was sent to the receiver
               buffer before the previous character in the buffer
               could be read. This destroys the previous
               character.
        bit 0 = 1  data ready. a complete incoming character has been
               received and sent to the receiver buffer register.

03FE   r   modem status register
        bit 7 = 1  data carrier detect
        bit 6 = 1  ring indicator
        bit 5 = 1  data set ready
        bit 4 = 1  clear to send
        bit 3 = 1  delta data carrier detect
        bit 2 = 1  trailing edge ring indicator
        bit 1 = 1  delta data set ready
        bit 0 = 1  delta clear to send

         - bits 0-3 are reset when the CPU reads the MSR
         - bit 4 is the Modem Control Register RTS during loopback test
         - bit 5 is the Modem Control Register DTR during loopback test
         - bit 6 is the Modem Control Register OUT1 during loopback test
         - bit 7 is the Modem Control Register OUT2 during loopback test

03FF   r/w scratch register