0060-006F ---- Keyboard controller (8041, 8042)  (or PPI (8255) on XT)

                 XT uses 60-63,  AT uses 60-64

        AT keyboard controller input port bit definitions
         bit 7   = 0  keyboard inhibited
         bit 6   = 0  CGA, else MDA
         bit 5   = 0  manufacturing jumper installed
         bit 4   = 0  system RAM 512K, else 640K
         bit 3-0      reserved

        AT keyboard controller output port bit definitions
         bit 7 =    keyboard data output
         bit 6 =    keyboard clock output
         bit 5 = 0  input buffer full
         bit 4 = 0  output buffer empty
         bit 3 =    reserved (see note)
         bit 2 =    reserved (see note)
         bit 1 =    gate A20
         bit 0 =    system reset

       Note:   bits 2 and 3 are the turbo speed switch or password
             lock on Award/AMI/Phoenix BIOSes.  These bits make
             use of nonstandard keyboard controller BIOS
             functionality to manipulate
               pin 23 (8041 port 22) as turbo switch for AWARD
               pin 35 (8041 port 15) as turbo switch/pw lock for
               Phoenix

0060   r/w KB controller data port or keyboard input buffer (ISA, EISA)
       should only be read from after status port bit0 = 1
       should only be written to if status port bit1 = 0
       keyboard commands (data goes also to port 0060):
        ED dbl   set/reset mode indicators Caps Num Scrl
        EE sngl  diagnostic echo. returns EE.
        EF-F2  sngl  NOP (No OPeration). reserved for future use
        F3 dbl   set typematic rate/delay
        F4 sngl  enable keyboard
        F5 sngl  disable keyboard. set default parameters
        F6 sngl  set default parameters
        F7-FD  sngl  NOP
        FE sngl  resend last scancode
        FF sngl  perform internal power-on reset function


0060   r   KeyBoard or KB controller data output buffer (via PPI on XT)

0061   w   KB controller port B (ISA, EISA)   (PS/2 port A is at 0092)
       system control port for compatibility with 8255
        bit 7  (1= IRQ 0 reset )
        bit 6-4    reserved
        bit 3 = 1  channel check enable
        bit 2 = 1  parity check enable
        bit 1 = 1  speaker data enable
        bit 0 = 1  timer 2 gate to speaker enable

0061   r   KB controller port B control register (ISA, EISA)
       system control port for compatibility with 8255
        bit 7   parity check occurred
        bit 6   channel check occurred
        bit 5   mirrors timer 2 output condition
        bit 4   toggles with each refresh request
        bit 3   channel check status
        bit 2   parity check status
        bit 1   speaker data status
        bit 0   timer 2 gate to speaker status

0061   w   PPI  Programmable Peripheral Interface 8255 (XT only)
       system control port
        bit 7 = 1  clear keyboard
        bit 6 = 0  hold keyboard clock low
        bit 5 = 0  I/O check enable
        bit 4 = 0  RAM parity check enable
        bit 3 = 0  read low switches
        bit 2      reserved, often used as turbo switch
        bit 1 = 1  speaker data enable
        bit 0 = 1  timer 2 gate to speaker enable

0062   r/w PPI (XT only)
        bit 7 = 1  RAM parity check
        bit 6 = 1  I/O channel check
        bit 5 = 1  timer 2 channel out
        bit 4      reserved
        bit 3 = 1  system board RAM size type 1
        bit 2 = 1  system board RAM size type 2
        bit 1 = 1  coprocessor installed
        bit 0 = 1  loop in POST

0063   r/w PPI (XT only) command mode register  (read dipswitches)
        bit 7-6 = 00  1 diskette drive
            = 01  2 diskette drives
            = 10  3 diskette drives
            = 11  4 diskette drives
        bit 5-4 = 00  reserved
            = 01  40*25 color (mono mode)
            = 10  80*25 color (mono mode)
            = 11  MDA 80*25
        bit 3-2 = 00  256K (using 256K chips)
            = 01  512K (using 256K chips)
            = 10  576K (using 256K chips)
            = 11  640K (using 256K chips)
        bit 3-2 = 00  64K  (using 64K chips)
            = 01  128K (using 64K chips)
            = 10  192K (using 64K chips)
            = 11  256K (using 64K chips)
        bit 1-0       reserved

0064   r   KB controller read status (ISA, EISA)
        bit 7 = 1 parity error on transmission from keyboard
        bit 6 = 1 receive timeout
        bit 5 = 1 transmit timeout
        bit 4 = 0 keyboard inhibit
        bit 3 = 1 data in input register is command
            0 data in input register is data
        bit 2 = 0 system flag status 0=power up or reset 1=selftest OK
        bit 1 = 1 input buffer full (input 60/64 has data for 8042)
        bit 0 = 1 output buffer full (output 60 has data for system)

0064   w   KB controller input buffer (ISA, EISA)
       KB controller commands (data goes to port 0060):
        20 read  read byte zero of internal RAM, this is the
                 last KB command send to 8041
        21-3F  read  reads the byte specified in the lower 5 bits of
                 the command in the 8041's internal RAM
        60-7F  dbl   writes the data byte to the address specified in
                 the 5 lower bits of the command.

                 Alternate description KB IO command 60 summary:
                  bit7 = 0 reserved
                  bit6 =   IBM PC compatibility mode
                  bit5 =   IBM PC mode
                  bit4 =   disable kb
                  bit3 =   inhibit override
                  bit2 =   system flag
                  bit1 = 0 reserved
                  bit0 =   enableoutput buffer full interrupt

        AA sngl  initiate self-test. will return 55 to data port
        AB sngl  initiate interface test. result values:
                  0 = no error
                  1 = keyboard clock line stuck low
                  2 = keyboard clock line stuck high
                  3 = keyboard data line is stuck low
                  4 = keyboard data line stuck high
        AC read  diagnostic dump. the contents of the 8041 RAM,
                 output port, input port, status word are send.
        AD sngl  disable keyboard
        AE sngl  enable keyboard
        AF AWARD Enhanced Command: read keyboard version
        C0 read  read input port
        C1 AWARD Enhanced Command: poll input port Low nibble
        C2 AWARD Enhanced Command: poll input port High nibble
        D0 read  read output port
        D1 dbl   write output port. next byte written  to 0060
                 will be written to the 8041 output port
        D2 AWARD Enhanced Command: write keyboard output buffer
        D3 AWARD Enhanced Command: write pointing device out.buf.
        D4 AWARD Enhanced Command: write to auxiliary device
        DD sngl  disable address line A20. default in Real Mode
        DF sngl  enable address line A20
        E0 read  read test inputs. bit0 = T0 and bit1 = T1
        Exxx   AWARD Enhanced Command: active output port
        F0-FF  sngl  pulse output port low for 6 microseconds.
                 bits 0-3 contain the mask for the bits to be
                 pulsed. a bit is pulsed if it's mask bit is
                 zero.

0065   r   communications port (Olivetti M24)

0068   w   HP-Vectra  control buffer (HP commands)
0069   r   HP-Vectra  SVC (keyboard request SerViCe port)
006A   w   HP-Vectra  clear processing, done

006C-006F  HP-HIL  (Human Interface Link = async. serial inputs 0-7)