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The architecture of the main logic board is designed around five large custom integrated circuits:
The computer also uses several standard ICs that are used in other Macintosh computers. This section describes only the custom ICs.
The Grackle IC functions as the bridge between the PowerPC microprocessor bus and the I/O and graphics devices on the PCI bus. It provides buffering and address translation from one bus to the other.
The Grackle IC also provides the control and timing signals for ROM and RAM. The memory control logic supports byte, word, longword, and burst accesses to the system memory. If an access is not aligned to the appropriate address boundary, Grackle generates multiple data transfers on the bus.
The Grackle IC controls the system RAM and ROM and provides address multiplexing and refresh signals for the DRAM devices. For information about the address multiplexing, see RAM Address Multiplexing .
The Grackle IC acts as a bridge between the processor bus and the PCI expansion bus, converting signals on one bus to the equivalent signals on the other bus. The PCI bridge functions are performed by two converters. One accepts requests from the processor bus and presents them to the PCI bus. The other converter accepts requests from the PCI bus and provides access to the RAM and ROM on the processor bus.
The PCI bus bridge in the Grackle IC runs synchronously. The processor bus operates at a clock rate of 67 MHz, and the PCI bus operates at 30 or 33 MHz.
The PCI bus bridge generates PCI parity as required by the PCI bus specification, but it does not check parity or respond to the parity error signal.
The Heathrow IC is an I/O controller and DMA engine for Power Macintosh computers using the PCI bus architecture.
Heathrow also provides power-management control functions for energy saving features included on Power Macintosh computers. The Heathrow IC is connected to the PCI bus and uses the 30-33 MHz PCI bus clock.
The Heathrow IC includes circuitry equivalent to the Ethernet, IDE, SCC, SCSI, SWIM3, and VIA controller ICs. The functional blocks in the Heathrow IC include the following:
The Heathrow IC provides bus interfaces for the following I/O devices:
The SCSI controller cell in the Heathrow IC is an 8-bit MESH controller. The MESH cell supports data transfer rates of 5 MB per second.
The Heathrow IC also contains a serial interface and sound control logic for the Screamer sound IC on the Audio/Video and Audio input/output cards.
The 85C30 SCC cell in the Heathrow IC is an 8-bit device. The SCC circuitry supports serial and LocalTalk protocols.
The Screamer custom IC combines a waveform amplifier with a 16-bit digital sound encoder and decoder (codec). The Screamer IC supports all of the audio input and output features on the Audio/Video and Audio input/output cards. The Screamer IC provides improved audio performance over the AWACS IC used in previous Macintosh computers. For additional information about the audio features of the Audio/Video and Audio input/output cards, see Sound .
The Burgundy custom IC combines a waveform amplifier with an internal 18-bit digital sound codec (only 16 bits supported for analog to digital/digital to analog sound capture and playback). The Burgundy IC supports all of the audio input and output features on the DVD-Video and Audio/Video Card. The Burgundy IC provides improved audio performance over the Screamer IC used on the Audio/Video and Audio input/output cards.
The ATI 3D RAGE graphics controller contains the logic for the video display. It includes the following functions:
A separate data bus handles data transfers between the ATI 3D RAGE graphics controller and the display memory. The display memory data bus is 64 bits wide, and all data transfers consist of 32 bits at a time. The ATI 3D RAGE IC breaks each 64-bit data transfer into several pixels of the appropriate size for the current display mode--4, 8, 16, 24, or 32 bits per pixel.
The ATI 3D RAGE graphics controller uses several clocks. Its transactions are synchronized with the PCI bus. Data transfers from the frame-buffer RAM are clocked by the MEM_CLK signal. Data transfers to the CLUT and the video output are clocked by the dot clock, which has a different rate for different display monitors.
The 2D graphics accelerator is a fixed-function accelerator for rectangle fill, line draw, polygon fill, panning/scrolling, bit masking, monochrome expansion, and scissoring.