Developer Documentation
PATHHardware Documentation > Original Power Mac G3 Computers Developer Note


Memory Subsystem

The memory subsystem of the main logic board consists of RAM, ROM, and back-side second-level (L2) cache, in addition to the PowerPC  microprocessor cache. The Grackle custom IC provides burst mode control to the ROM.

ROM

The ROM consists of 4 MB of ROM installed in a DIMM socket.

Second-Level Cache

The back-side second-level (L2) cache consists of 512 KB or 1 MB of SRAM. The cache is on the microprocessor card module. This cache runs at one half the speed of the microprocessor, a ratio of 2:1.

System RAM

The Power Macintosh G3 computers have 0 MB of DRAM memory soldered on the main logic board. All RAM expansion is provided by SDRAM devices on 64-bit 168-pin JEDEC-standard 3.3-volt unbuffered SDRAM DIMMs. Three DIMM sockets are used for memory expansion. Supported DIMM sizes are 8, 16, 32, 64, 128, and 256 MB. The DIMM sockets support both one-, two-, and 4-bank SDRAM DIMMs with no more than 16 memory devices on a DIMM. To accommodate the 16 device load limit, 256 MB SDRAM DIMM require 16M x 8 or higher density devices. The Grackle custom IC provides memory control for the system RAM.

For additional information about SDRAM DIMMs for Power Macintosh G3 computers, see RAM DIMMs .


© 1998 Apple Computer, Inc. - Revised 8/13/98