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The memory controller in the Grackle IC supports 1 M, 4 M, 8 M, 16 M, and 64 M SDRAM devices. The speed of the SDRAM devices is 100 MHz/10ns or faster. The devices are programmed to run with a CAS latency of 3. The access time from clock at CAS latency of 3 should be 7 ns or faster. Burst length should be at least 4 and the minimum clock delay, back to back random column accesses should be a latency of 1 clock.
The Grackle IC provides a CAS-before-RAS refresh cycle every 15.6 s. DRAM devices must be compatible with this refresh cycle; for example, this cycle will refresh 2K-refresh parts within 32 milliseconds.
Table 4-3 lists some vendors and part numbers for SDRAM DIMMs that have been qualified as compatible with the Power Macintosh G3 architecture.