Memory Test for PC compatible computers

AleGr MEMTEST

Russian version

For program updates go to MEMTEST WWW page.


AleGr MEMTEST is a program for testing DRAM (main memory) of PC-compatible computers built on Intel 386 or higher processor. The program is written with knowledge of system bus, cache and main memory of 80486, Pentium and Pentium Pro (Pentium II) processors.

Maximum size of memory the program is able to test is 3 gigabytes.

The program can be run only under "bare" DOS session, that is without any memory managers, such as HIMEM.SYS and EMM386.EXE. To start bare DOS session, restart the computer and press Shift+F5 when "Starting Windows 95..." message appears. For Windows 98 bare DOS session, press and hold Ctrl when OS boot begins (just after BIOS detected all disk drives). Windows 98 boot menu will appear. Press Shift+F5 to start DOS.

Unlike older known memory testing programs which were written for cacheless processors, the test does not require to disable L1/L2 caches in BIOS setup. Test patterns used by the program are designed to test burst transfers between CPU and L2 cache and/or memory. Such transfers occur most of the time in real applications. If cache is disabled, burst transfers wouldn't be tested.

Command line to start the program is as follows:

MEMTEST <memory size> <base address of area to test> /program options

Optional memory size and base address of an area to test are specified in megabytes. If they are not specified, all available memory (but only up to 512 megabytes) will be tested. If your computer has more than 512 MB of memory, you have to specify its size. Since the program detects actual memory size, it is safe to specify more memory than actually installed.

The program cannot test less than 8 megabytes.

The following command line options are recognized:

/row <size> - specifies size (in kilobytes) of DRAM memory array row. Allowed values are 4 up to 64 (only powers of 2). By default all possible row sizes from 4 to 64 are tested. Specify this option only if you exactly know row size (it depends on memory chip manufacturer and model and is not usually published in memory data sheets). If specified size does not match real value, the program won't be able to test the memory chips for maximum noise on word lines.

/delay <time1> <time2> - specifies the delay (in seconds) between memory write and read passes. The delay specified by time1 is inserted on every other test pass, default value is 1 second. The delay specified by time2 is inserted on 62th and 63th passes of 64, default is 60 seconds. This allows to test for proper DRAM refresh.

/speed - tells the program to measure CPU clock rate and also L2 cache and main memory read/write speed (including write in write-allocate mode);

/readtwice - tells the program to compare test data twice;

/writethru - disables writeback cache policy;

/nocache - disables cache at all (not recommended).

/nocheck - disables machine check on Pentium (and newer) systems. Machine check interrupt is triggered when bus or cache parity error occurs.

/preheat - the program will try to preheat the memory chips by the special access sequence, before writing each test pattern.

It is not possible to return back to DOS after MEMTEST is started, since the program switches the CPU to 32-bit protected mode. Testing can be stopped only by system restart - either by pressing Ctrl+Alt+Del or by pressing Reset (it can be found on system case, not on keyboard), or by turning power off then off (recommended only for systems without Reset button).

When memory errors messages fill all the screen, the program pauses screen output to prevent error message loss. To resume the output, press Enter.

While working, the program prints test pass number. Full test consists of 64 passes. Required time depends on CPU and memory size. Keep in mind that every other test pass includes 36 seconds of delay and two passes of 64 both include 36 minutes of delay. After the program completed all 64 passes, it will continue to run the test from the beginning.


Test set

First test performs pseudorandom data read/write. The data consists of "all ones"/"all zeros" patterns produced by pseudorandom sequence generator. The test checks for address errors.

The second test uses "running one"/running zero" patters. This test sequence allows also to check system bus in maximum noise conditions. The following test sequence is written:

0111111111111111 0111111111111111 0111111111111111 0111111111111111
1000000000000000 1000000000000000 1000000000000000 1000000000000000
0111111111111111 0111111111111111 0111111111111111 0111111111111111
1000000000000000 1000000000000000 1000000000000000 1000000000000000

After all the memory being tested is filled with the pattern, it is read in ascenting direction and compared with reference data. As the memory is read, the data is replaced with inverse test pattern. After all the memory is read and replaced with inverted pattern, it is read in descenting direction and compared with new reference data. As the memory is read, the data is replaced with next test pattern, which is like first one shifted to right:

1011111111111111 1011111111111111 1011111111111111 1011111111111111
0100000000000000 0100000000000000 0100000000000000 0100000000000000
1011111111111111 1011111111111111 1011111111111111 1011111111111111
0100000000000000 0100000000000000 0100000000000000 0100000000000000

Such tests are performed for all bit positions (total 16). For testing 32-bit memory systems, used in 386 and 486 class systems, 32-bit test patterns are used.

Next tests work with "all ones"/"all zeros" patterns, with pattern inverted on every other memory array row. The test is based on dynamic RAM structure.

Dynamic RAM array is crossed by word (or row) lines (that go from row address decoder) and column lines. Each pair of column lines is connected to differential inputs of read detector. Even rows are connected to even column lines, and odd rows are connected to odd lines. Column lines are connected also to reference cells that are charged to half voltage of a regular cell. When, for instance, even row is selected, memory cells are read to even column lines and reference cells are read to odd column lines. Voltage difference (tens of millivolts) is detected by read detectors and converted to logical 0 or 1. Then read cells are charged back to full voltage (refreshed) and row is deselected. After that, all column lines should be discharged to fixed voltage level, it is called "RAS precharge".

Maximum noise to column lines occures when all cells are charged to same "low" or "high" state, this means that adjacent rows should be written with inverted data. To achieve this, test pattern is inverted every 4 to 64 KB (step is doubled on every test pass), and data is read from interlaced rows - 32 bytes from one row, 32 bytes from adjacent one. "All zeros" and "all ones" patterns allow also to induce maxium noise on adjacent column lines.

After every test pass the program relocates itself in the physical memory, to test the area it just occupied.

Every other pass includes 1 second delay between memory writing and reading. During the delay there are no accesses to the DRAM, because all instructions are fetched from the L1 cache. This allows to check how reliable is memory refresh. On two passes from 64 the delay is increased to 60 seconds. These delays can be specified in the command line at the program start.

To test transfers from L2 cache to the processor, some of test passes are performed with data prefetched from the memory to L2 cache. Without such prefetch, the data goes directly from memory to the processor. To test transfers from processor to L2 cache, some of the test passes are performed with data prefetched to L2 cache during test pattern write. This prevents  the direct writes from CPU to RAM.

Changes history

1.03 (March 28, 1999). Fixed a bug in timer function in V1.02, which was caused by compiler upgrade to MSVC 5.0. Added /preheat command line option.

1.02 (Feb 25, 1999). Fixed i386 and i486 processor detection. Fixed problem with Intel P-II motherboards, which caused the test to reboot a computer. Added /nocheck command line option to disable machine check interrupt on P5 and P6 processors.

1.01 (Jan 22, 1998). Changed way to reset CPU for reboot. Instead of putting the CPU to shutdown mode (did not work on Pentium Pro+FX440) reset by keyboard controller is used. Added reset of floppy drives' motors before going to protected mode.

1.0 (Dec 30, 1997). First released.


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Last changed 04/04/99.