DRAM FAQ

Index

1. What's the difference between 2K and 4K SDRAM?

2. What is CL? and the difference between CL2 and CL3.

3. What's the difference between buffered and unbuffered DIMMs?

4. 2 clock versus 4 clock SDRAM DIMMs

5. Sometimes I gets questions asking for help picking out a product...

6. Will the 100MHz SDRAM I buy today work in a future 100MHz system?

7. What are the risks of mixing Gold plated SIMMs in tin plated connectors

The following was written in 1994, so some is out of date.

Part I : Memory Overview

Part II : DRAM Technology
: What's so special about SDRAM? (1994)

1. What's the difference between 2K and 4K SDRAM?
: Short answer: not much, don't worry about it.

Long answer: The SDRAM has multiple internal banks. The 16M SDRAM has 2 banks, the 64M has 4 banks. When you tell the SDRAM a ROW or COLUMN address you must also specify which BANK you are referring to. The way to do this is by the 'bank address' (BA). Herein lies the problem.

For reasons unknown to me some suppliers have lumped together the ROW address pins with the BANK address pins and simply refer to them as 'address' pins. For the 2Mx8 SDRAM some suppliers claim to have 11 ROW address plus 1 BA, other just say 12 addresses. That's just addressing, for refresh requires you also specify the refresh interval (tREF). For a distributed refresh scheme you simply divide tREF by the number of refresh cycles to get the auto-refresh interval. In both cases for the SDRAM it works out like:

2. What is CL? and the difference between CL2 and CL3.

CL stands for CAS Latency. It is a programmable register in the SDRAM that sets the number of clock cycles between the issuance of the READ command and when the data comes out. CL is set when the device is powered up and remains fixed until it is reset or power is removed.

Related to CL is the number of clocks that are allowed between the 'activate' (RAS) command and the 'read' (CAS). This parameter is tRCD and in the HP specification is 30ns. This means at a 15ns clock cycle the total number of cycles from activate to read is 2.

With this information you can construct a typical clock profile. For the activate command the address must be set up before the clock by more than tSS (3ns); in reality you typically set up the address 1 full clock early. Then you issue an activate command, then you wait for tRCD to be satisfied (but while you wait you set up the column address), that's 2 more clocks, then you must wait for the CL value to get the data out. That's 1 (setup) + 2 (tRCD) + 2 (CL) = 5 clocks to get the first word out. Then, because it is SDRAM the rest of the data comes out -1-1-1.

If you choose to use CL3 and rely on 'envelope' specifications
( http://techweb.cmp.com/oem/cdrom/memory/ ) that include all suppliers with a tRCD of 36ns then your clock profile is 1 + 3 + 3 = 7 at 66MHz.

At 66MHz using 7-1-1-1 CL3 the device performance is comparable to a 70ns asynchronous DRAM, but 5-1-1-1 CL2 is comparable to a 50ns asynchronous DRAM.

3. What's the difference between buffered and unbuffered DIMMs?

High density DIMMs have lots of DRAM on them and therefore a higher capacitive load on the address and control signals compared to lower densities. Some designers use re-drive buffers on the DIMM boost the signals to get to the SDRAM faster compared to the same high density module without buffers. BUT! ...

The buffers introduce a small delay into the electrical signal, so adding buffers to a standard density module would have the effect of SLOWING DOWN the signal, compared to the same low density module without buffers.

For JEDEC DIMMs based on 16Mbit SDRAM the 'standard density' refers to modules from 8MB to 32MB.

For JEDEC DIMMs based on 64Mbit SDRAM the 'standard density' refers to modules from 32MB to 128MB.

4. 2 clock versus 4 clock SDRAM DIMMs

The original JEDEC standard for SDRAM DIMMs had only 2 clock lines. This was found to be insufficient due to loading on these lines and the standard was changed to 4 clock lines. SOME 4 clock modules will not work in systems that are designed for 2 clock, but some will. SOME 2 clock modules might not work in systems designed for 4 clocks, but then again some will.

4 clock modules are the current standard and it is unlikely to change again.

5. Sometimes I gets questions asking for help picking out a product...

> Hello,
>
> Michael Sporer wrote:
> >
> > Victor wrote:
>
> > > I picked the following listing up somewhere, any ideas how correct
> > > it is????
> > > sdram 15 ns - up to busspeeds of 66 mhz
> > > sdram 12 ns - up to busspeeds of 83 mhz
> > > sdram 10 ns - up to busspeeds of 100 mhz.
> > >
> > > {perhaps these are specified/advised numbers, just like the one for
> > > EOD ram, however 83mhz busppeed is also possible with 60ns ram).
> >
> > Unfortunately not that simple. Full explanation is at:
> >
> > http://www.hpl.hp.com/dram/ns_mhz.htm
>
> Informative link, but I don't know what to do with the following quote:
>
> 'The bottom line is that HP believes that it makes no sense whatsoever
> to specify SDRAM based on their rated maximum clock frequency. Only systems
> with extremely short interconnect lengths can actually run them that fast.
> HP now specifies SDRAM based on access time and
> recommends that this would be a good thing for the entire industry to do as
> well.'
>
> I'm an end consumer and I want my TXboard to run (stable) at 83mhz with sdram.
> Basically MHZ ratings mean everything to me and access times I don't care
> about.
> Stores don't sell sdramm with access time (ns).
> So how do I know which sdram with what access time is capable of
> running at the 83 mhz busspeed??????
>

The whole point is that MHz ratings of SDRAM are meaningless. That's why I was
given authorization to set up this web site. The site merely documents the
problem that you are having.

One of the restrictions that I have is that I'm not allowed to recommend any
particular product or supplier. My employer wouldn't like that.

But people who overclock are generally resourceful, my site is only trying
to help clear up some of the problems you might have and give you hints as
to the right questions to ask when you go shopping.

Good Luck! Sorry I couldn't be of more help.

Michael

> TIA.
>
>

6. Will the 100MHz SDRAM I buy today work in a future 100MHz system?

PC100 DIMMs typically require a 125MHz or -8 speed SDRAM, not the

100MHz or -10 which is more common.

Subject: Re: SDRAM worth buying today?

From: Michael Sporer <sporerX@hplabsz.hpl.hp.com>

Date: 1997/05/29 Message-Id: <338DD2A9.2C3D@hplabsz.hpl.hp.com>

Newsgroups: comp.sys.ibm.pc.hardware.chips

MICHAEL R. SHUST wrote:

> > Michael Sporer (sporerX@hplabsz.hpl.hp.com) wrote:

> : SDRAM that you buy today will not work in 100MHz systems of the future,

> : and at 66MHz there may or may not be an advantage over EDO depending

> : on many factors as outlined at my website.

> > Why not?

> -Mike

Current SDRAM running in systems at 66MHz have an access time of around 9ns,

while the system is running at a 15ns (66MHz) clock rate. The output hold time

of the SDRAM is around 3ns, and the edge rates of the signals are about 1ns,

so the timing window where data is available is:

15ns - 9ns - 1ns + 3ns = 8ns

Within those ample 8ns the signals have to travel from the SDRAM to the controller (at a fraction of the speed of light) ... it takes about 3ns for that (depending on the length of the interconnect and the capacitive load) ... so now we are down to 5ns.

In the remaining 5ns you have to account for signal skew, setup and hold time of the controller and also guardband from the minimally loaded system to the maximum capacitive load. After all that there's not much margin left. Now to run at 100MHz you reduce the clock cycle time to 10ns instead of 15ns ... it can't work. If the devices available today could actually run at 100MHz then everyone wouldn't be having so many problems at 66MHz!

Over time the technology will improve to the point where this is a non-issue, at which time the next insurmountable hurdle will be in front of us.

7. What are the risks of mixing gold plated SIMMs in tin plated connectors

Galvanic corrosion occurs in the presence of humidity. The rate of corrosion is a function of the humidity level. The presence of electrolytes (salt) accelerates the corrosion rate.

The tin corrodes, the gold does not. The corrosion product can cause the electrical interconnect to fail. The time to first failure can vary between a few months and many, many years.

Removing and reseating the connection can temporarily cure the problem,

but the protective layer of plating will eventually be worn or corroded

away. At some point the failures will become more frequent than the time

to first failure.

here's some filler material:

I) Memory : Volatile and Non-Volatile Memory (NVM)

NVM : retains data when power is removed

NVM types : ROM (Read Only Memory)
MROM (Mask programmable ROM)
PROM (Programmable ROM)
EPROM (Erasable PROM)
UV-EPROM (the traditional EPROM) erased with UV light
EEPROM (Electrically Erasable PROM)
Flash (some special kind of EEPROM that costs a lot less than regular EEPROM)

Others: Ferro-electric

Volatile : forgets when power is removed

Volatile types:

RAM (Random Access Memory)

SAM (Serial Access Memory) a FIFO is a SAM. Other types of SAM are
generally VERY application specific; used for example for
broadcast media such as televisions, video recorders, etc.
These memories are optimized for specific display resolutions,
color depth and bandwidth; i.e. 100% of the storage locations
are used, there are no surplus cells which would be otherwise
wasted.

Some RAM types :

DRAM (Dynamic RAM) - requires refresh
SRAM (Static RAM) - does not require refresh
FSRAM (Fast SRAM) - for cache
SlowSRAM - for low power
SSRAM - synchronous interface SRAM
PSRAM (Pseudo SRAM) = DRAM core + SRAM interface = dying tech
SDRAM - DRAM with synchronous interface AND _multiple_banks!_
SGRAM - SDRAM + graphics functions

The devices above have only 1 d5. Someata port and connect only to 1 bus;
the devices below are multi-port:
For example: VRAM has 2 data 'ports' for connecting to 2
independent busses; The RAM port connects to the
controller, the SAM port connects to the RAMDAC.

VRAM (Video RAM) = DRAM + SAM + graphics
TPRAM - Triple port = DRAM + 2 SAM - used primarily for
data buffering.

Other:
RDRAM - Rambus interface DRAM (protocol/packet based)
CDRAM - cache DRAM = DRAM + SRAM cache.
EDRAM - Similar to CDRAM.

II) RAM Technologies :

DRAM - 2 elements per storage node; capacitor and transistor
SRAM - 4 or 6 elements per node; transistors

Why DRAM?
Answer: Lowest Cost per bit.

What's so special about SDRAM?

'Regular' DRAM is sometimes being called 'Asynchronous' in order to
distinguish from Synchronous.

SDRAM has two significant advantages over DRAM. The first is the
synchronous interface; SDRAM has a clock, DRAM does not; all critical
timing signals in SDRAM are referenced to the (1) clock; the control
signals are then non-critical. Compare this to DRAM where the
critical timing signals are reference to any one of 5 of the
control signals. This allows two things to occur, 1) The board
routing and controller are greatly simplified, and 2) The device
can be specified at much tighter margins allowing the interface to
run much faster. Compare 60ns EDO DRAM which can run at 25ns page
cycle time to SDRAM interface built with the exact same process,
technology and DRAM core which still operates at 60ns access time but
10 ns page cycle time.

The second MAJOR advantage that SDRAM has over DRAM is generally
ignored. This is the fact that it has multiple banks internally,
offering significant advantage to the memory system designer who
designs a multi-bank architecture. In the past multibank architecture
was available only to systems that had an overall memory size that
LARGE enough to to implement multiple banks EXTERNALLY to the DRAM.
For example an 8MB Pentium system has only a single bank
using 4Mbit DRAM, doubling the memory size to 16MB adds a second bank,
but since most PCs have the minimum memory size of 8MB, the chipset
designers generally don't bother to even add multi-bank capabilities
to the controller. Compare this to a large server system which
ships with 8 banks minimum. (but larger minimum memory size as well.)

The bottom line is that by putting two banks in a 16M DRAM (SDRAM or
even DRAM if it were available) cuts the minimum memory size and also
the memory GRANULARITY in half, allowing multi-bank architecture
(and higher performance) into lower price point entry level systems.

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Address bits	Refresh Cycles	tREF	Auto-refresh interval
11 row	2^11 = 2048 = 2K	32ms	32ms / 2048 = 15.6 us
12	2^12 = 4096 = 4K	64ms	64ms / 4096 = 15.6 us

DRAM FAQ

You are visitor number since April 24, 1997

Contact Information

Disclaimer

Copyright © 1997 Hewlett Packard Company Last modified: June 19, 1997

Copyright © 1997 Hewlett Packard Company
Last modified: June 19, 1997