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The Ultimate Memory Guide

Memory Data Integrity Checking

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Memory data integrity checking

One aspect of memory design involves ensuring the integrity of data stored in memory. Currently, there are two primary methods to ensure the integrity of data stored in memory: Due to price competition, it is becomming more common among personal computer manufacturers not to use data integrity checking. They are eliminating the need for more expensive parity memory, for example, to lower the price of their computers. (This trend is complemented by the increased quality of memory components available from certain manufacturers and, as a result, the relative infrequency of memory errors.)

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A word about the memory controller

The memory controller is an essential component in any computer. Simply stated, its function is to oversee the movement of data into and out of memory. The memory controller determines what type of data integrity checking, if any, is supported. With methods such as parity and ECC, the memory controller plays an active role in the process.

The decision about data-integrity checking must be made when you purchase your computer. If the computer is to play a critical role -- as a server, for example -- then a computer with an ECC-capable memory controller is an appropriate choice. Most computers designed for use as high-end servers are designed to support ECC. Most desktop computers designed for use in business and government are designed to support parity. Most low-cost computers designed for use at home or in small businesses are designed for nonparity memory.

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Parity

When parity is in use on a computer system, one parity bit is stored in DRAM along with every 8 bits (1 byte) of data. The two types of parity protocol -- odd parity and even parity -- function in similar ways. This table shows how odd parity and even parity work. The processes are identical but with opposite attributes.

The parity method does have its limitations. For example, a parity circuit can detect an error, but cannot perform any correction. This is because the circuit can't determine which of the 8 data bits are invalid. Furthermore, if multiple bits are invalid, the parity circuit will not detect the problem if the data matches the odd or even parity condition that the parity circuit is checking for. For example, if a valid 0 becomes an invalid 1 and a valid 1 becomes an invalid 0, the two defective bits cancel each other out and the parity circuit misses the resulting errors. Fortunately, the chances of this happening are extremely remote.

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An advisory about `fake parity'

With normal parity, when 8 bits of data are written to DRAM, a corresponding parity bit is written at the same time. The value of the parity bit (either a 1 or 0) is determined at the time the byte is written to DRAM, based on an odd or even quantity of 1's. Some manufacturers use a less expensive `fake parity' chip. This chip simply generates a 1 or a 0 at the time the data is being sent to the CPU in order to accommodate the memory controller. (For example, if the computer uses odd parity, the fake parity chip will generate a 1 when a byte of data containing an even number of 1's is sent to the CPU. If the byte contains an odd number of 1's, the fake parity chip will generate a 0.) The issue here is that the fake parity chip sends an `OK' signal no matter what. This way, it `fools' a computer that's expecting the parity bit into thinking that parity checking is actually taking place when it is not. Fake parity cannot detect an invalid data bit.

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ECC

Error Correction Code is used primarily in high-end PCs and file servers. The important difference between ECC and parity is that ECC is capable of detecting and correcting 1-bit errors. With ECC, 1-bit error correction usually takes place without the user even knowing an error has occurred. Depending on the type of memory controller your computer uses, ECC can also detect rare 2-, 3-, or 4-bit memory errors. However, while ECC can detect these multiple-bit errors, it can only correct single-bit errors. In the case of a multiple-bit error, the ECC circuit reports a parity error.

Using a special algorithm (mathematical sequence) and working in conjunction with the memory controller, the ECC circuit appends ECC bits to the data bits and together they are stored in memory. When data is requested from memory, the memory controller decodes the ECC bits and determines if one or more of the data bits are corrupted. If there's a single-bit error, the ECC circuit corrects the bit. As mentioned, in the rare case of a multiple-bit error, the ECC circuit reports a parity error.

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What kind of simms are used in ECC configurations?

If you see a 72-pin SIMM with a x39 or x40 width specification, you can be reasonably certain that the SIMM is designed exclusively for ECC. However, some high-end PCs and many file servers use pairs of x36 SIMMs for ECC error checking. Two x36 SIMMs supply a total of 72 bits; 64 bits are used for data and 8 bits are used for ECC. This can be confusing because when these same x36 modules are used in other configurations, they are simply parity modules. This reinforces the point that whether or not a system performs parity or ECC error checking depends more on the memory controller than it does on the memory module. The memory module provides the bits, but it is the memory controller that decides how they will be used. Generally, in order to use ECC memory, your computer must include a memory controller designed to take advantage of ECC technology.

There is a new technology called ECC on SIMM, or EOS, that offers ECC capability on systems designed for parity. So far, this technology has been rather expensive. In addition, its application may remain limited simply because most people who want ECC decide so before purchasing a computer and therefore can get ECC support in the computer more affordably than on EOS modules.

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