
18.6 Cache Test Mode Protocol

Normal Write Protocol
A cache test mode normal write operation writes a selected RAM array. The write address, way, array, and data are specified in the write command.
The external agent issues a normal write command by:
Normal writes have a repeat rate of 8 PClk cycles.
Figure 18-3 depicts two cache test mode normal writes.

Figure 18-3 Cache Test Mode Normal Write Protocol

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96



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