9. Error Protection and Handling
CacheErr register to the CP0 CacheErr register to complete, the EW bit is set in its local CacheErr register. Once the Cache Error exception is taken, the EW bit in the CP0 CacheErr register is set and the Cache Error exception handler now determines that a second error has occurred.
Once the CP0 CacheErr register EW bit is set, it can only be cleared by a reset sequence.