6.13 System Interface Bus Encoding
Table 6-21 Encoding of SysAD[63:0] for Address Cycles
When the processor is in slave state, an external agent uses the target indication field to specify which processors are targets of an external request.
Table 6-22 presents the processor request address cycle address alignment.
Table 6-22 Processor Request Address Cycle Alignment
Table 6-23 presents the external coherency request address cycle address alignment.
Table 6-23 External Coherency Request Address Cycle Alignment
For example, consider the data cycle for a byte request whose address modulo 8 is 1. When MemEnd is negated (little endian), the SysAD[15:8] byte lane is valid. When MemEnd is asserted (big endian), the SysAD[55:48] byte lane is valid.
SysAD[63:0] Address Cycle Encoding
Table 6-21 presents the encoding of the SysAD[63:0] bus for address cycles.
SysAD[63:60]
During the address cycle of processor noncoherent block read, double/single/partial-word read, block write, double/single/partial-word write, and eliminate requests, the processor always drives a target indication of 0 on SysAD[63:60]. This indicates that the request targets the external agent only. When the CohPrcReqTar mode bit is negated, during the address cycle of processor coherent block read and upgrade requests, the processor also drives a target indication of 0 on SysAD[63:60]. However, when the CohPrcReqTar mode bit is asserted, during the address cycle of processor coherent block read and upgrade requests, the processor drives a target indication of 0xF on SysAD[63:60]. This indicates that the request targets all processors, together with the external agent, on the cluster bus. In multiprocessor systems using the cluster bus, the CohPrcReqTar mode bit is asserted for a snoopy-based coherency protocol, and negated for a duplicate tag or directory-based coherency protocol.SysAD[59:58] Uncached Attribute
During the address cycle of processor double/single/partial-word read and write requests and during the address cycle of processor Uncached accelerated block write requests, the processor drives the uncached attribute onto SysAD[59:58]. See the section titled, Support for Uncached Attribute, in this chapter for more information.SysAD[57]
During the address cycle of processor block read, typical block write, upgrade, and eliminate requests, SysAD[57] contains the secondary cache block way indication. This information may be useful for system designs implementing a duplicate tag or a directory-based coherency protocol.SysAD[56:40]
When processor is in master state, it drives SysAD[56:40] to zero during address cycles.SysAD[39:0]
During the address cycle of processor and external requests, SysAD[39:0] contain the physical address.
SysAD[63:0] Data Cycle Encoding
During System interface data cycles, when less than a doubleword is transferred on the SysAD[63:0] bus, the valid byte lanes depend on the request address and the MemEnd mode bit.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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