S
SC instruction
SC(A,B)Addr, signals [1] [2]
SC(A,B)DWay, signals [1] [2] [3]
SCBlkSize, mode bits [1] [2] [3]
SCClk frequency [1] [2]
SCClk, signal [1] [2]
SCClkDiv, mode bits [1] [2] [3]
SCClkTap, mode bits
SCCorEn, mode bits
SCDataChk, bus
scheduling, dynamic
SCSize, mode bits [1] [2]
SCTag, signals
SCTagChk, bus
SCTagLSBAddr, signal
SCTWay, signal [1] [2] [3]
SECDED
secondary cache interface signals, see also individual signals
secondary cache, see also cache, secondary
SelDVCO, signal
serial operations and CACHE instructions
setup times, AC electrical
signal integrity
decoupling capacitance
maximum input voltage levels
power supply regulation
reference voltage
signals
power interface, see also individual signals
secondary cache interface, see also individual signals
System interface, see also individual signals
test interface, see also individual signals
size, page in memory
slave state
and flow control
soft (warm) reset [1] [2]
Soft Reset exception
Soft Reset
exception
software interrupts
sparse encoding protection
special interrupt vector
specifications, test, AC electrical
speculative branching
speculative execution [1] [2]
square-root unit, FPU
SR, bit [1] [2]
sseg space
SSRAM [1] [2]
stage, definition of
stalls, improving performance
standard package configuration
state
master
slave
Status register
in FPU, see also FSR
store conditional
store operations, FPU registers
stores
and uncached buffer
nonblocking
strong ordering
example of
superpipeline, architecture
superscalar processor
superscalar
processor
definition of
pipeline
processor
Supervisor mode
address mapping
csseg space
operations
sseg space
suseg space
xsseg space
xsuseg space
suseg space
switch, context
SX, bit [1] [2]
SYNC
instruction [1] [2] [3]
prevented from graduating
SysAD, bus signals [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
SysADChk, bus
SysADChk, signal
SysAD\[20\
16\]
interrupt register
SysAD\[39\
0\]
during address cycle
SysAD\[56\
40\]
SysAD\[57\]
secondary cache block way indication
SysAD\[59\
58\]
uncached attribute
SysAD\[63\
0\]
address cycle encoding
data cycle encoding
60\]
address cycle
interrupt
SysClk cycle [1] [2] [3]
SysClk, signal [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
SysClkDiv, mode bits [1] [2]
SysClkRet, signal [1] [2]
SysCmd, bus [1] [2] [3]
SysCmdPar, signal
SysCmd\[0\]
ECC
ECC checking
external address cycles
processor data cycles
SysCmd\[10\
8\]
data response
external intervention and invalidate requests
SysCmd\[11\
0\]
map
protocol
SysCmd\[11\]
SysCmd\[2\
processor write requests
1\]
block data response
processor requests
SysCmd\[4\
3\]
data cycles
external special requests
processor read requests
processor upgrade requests
SysCmd\[5\], bit
SysCmd\[5\]
data cycles
SysCmd\[7\
5\]
external requests
processor requests
SysCorErr, signal [1] [2] [3]
SysCyc, signal
SysGblPerf, signal [1] [2] [3]
SysGnt, signal [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
SysNMI, signal [1] [2]
SysRdRdy, signal [1] [2]
and flow control
SysRel, signal [1] [2] [3] [4] [5] [6] [7]
SysReq, signal [1] [2] [3] [4] [5] [6]
SysReset, signal [1] [2] [3] [4] [5] [6] [7] [8] [9]
SysResp, bus [1] [2] [3]
SysRespPar, signal
SysRespVal, signal [1] [2] [3] [4] [5]
SysResp\[4\
0\]
external completion response
2\]
driving completion indication
SysState, bus [1] [2] [3] [4]
SysStatePar, signal
SysStateVal, signal [1] [2]
SysState\[0\]
processor coherency data response [1] [2]
SysState\[2\
0\]
encoding
System Call exception
system configuration
multiprocessor
uniprocessor
System interface [1] [2]
arbitration
in a cluster bus system
in a uniprocessor system
rules
external agent
external block data response protocol
external duplicate tags, support for
external response
protocol
frequencies
processor request
processor response
request
response
split transaction
arbitration
in a cluster bus system
protocol
block write request protocol
buffers
bus encoding
description of buses
SysAD
SysCmd
SysResp
SysState
cached request buffer
clock domain
cluster bus
cluster request buffer
coherency
coherency conflicts, action taken
connecting to an external agent
connections to various system configurations
directory-based coherency protocol
error handling
on buses
on SysResp bus
schemes
on SysAD bus
on SysCmd bus
on SysState bus
error protection
for buses
schemes
external allocate request number request protocol
external coherency conflicts
external coherency requests, action taken
external completion response protocol
external data response flow control [1] [2]
external double/single/partial-word data response protocol
external interrupt request protocol
external intervention exclusive request
external intervention request protocol
external intervention shared request
external invalidate request
protocol
external request [1] [2]
flow control
protocol
external response
flow control
grant parking
hardware emulation, support for
I/O
incoming buffer
internal coherency conflicts
interrupts
master state
multiprocessor connections
with cluster bus
with dedicated external agents
outgoing buffer
outstanding processor requests
outstanding requests on the System interface
port
processor block read request protocol
processor coherency data response protocol
processor coherency state response protocol
processor double/single/partial-word read request protocol
processor double/single/partial-word write request protocol
processor eliminate request protocol
processor request
flow control protocol
protocol
processor response
protocols
processor upgrade request protocol
register-to-register operation
request
protocol
cycle
number field
response
protocol
signals [1] [2]
slave state
support for I/O
uncached attribute
uncached buffer
uniprocessor connections
SysUncErr, signal [1] [2] [3] [4] [5]
SysVal, signal [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
SysWrRdy, signal [1] [2]
and flow control