R10000 Microprocessor User's Manual


7. Clock Signals


The R10000 processor has differential PECL clock inputs,
SysClk and SysClk*, from which all processor internal clock signals and secondary cache clock signals are derived.

Three major clock domains are in the processor:

These domains are described in this chapter.


Chapter Contents

7.1 - System Interface Clock and Internal Processor Clock Domains
7.2 - Secondary Cache Clock
7.3 - Phase-Locked-Loop


Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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