R10000 Microprocessor User's Manual


18. Cache Test Mode


The R10000 processor provides a cache test mode that may be used during manufacturing test and system debug to access the following internal RAM arrays:


Chapter Contents

18.1 - Interface Signals
18.2 - System Interface Clock Divisor
18.3 - Entering Cache Test Mode
18.4 - Exit Sequence
18.5 - SysAD(63:0) Encoding
18.6 - Cache Test Mode Protocol


Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


Generated with CERN WebMaker