I
I/O signals, DC characteristics
I/O, support for
IE, bit
IM, (interrupt mask) field
implementation number, R10000 processor
incoming buffer [1] [2]
Index Hit Invalidate CACHE instruction
Index Invalidate CACHE instruction
Index Load Data CACHE instruction
Index Load Tag CACHE instruction [1] [2] [3] [4] [5] [6] [7]
Index Load Tag instruction
Index register
Index Store Data CACHE instruction [1] [2]
Index Store Tag CACHE instruction [1] [2]
Index Writeback Invalidate CACHE instruction
indexing, the secondary cache
inexact result (FP)
initialization
input voltage levels, maximum
instruction cache, block size see also cache, primary instruction
instruction register, JTAG
instruction
DMFC1
issue
superscalar
latencies
load linked
queue
repeat rates
store conditional
CACHE, see also CACHE instructions [1] [2] [3]
CacheOp, see also CACHE instructions
completion
COP0 see also CP0
COP1
COP2
decoding
dependencies
DMFC0
DMTC0
ERET
execution
fetching
FPU, processor specific
CFC1
CTC1
CVT.L.fmt
for valid FP control registers
moves and conditional moves
graduation
issue
MFC0
MFC1 [1] [2]
MFPC
MFPS
MTC0
MTPC
MTPS
processor-specific
queue
SWC1
SYNC [1] [2] [3]
TLBP
TLBR
TLBWI
TLBWR
unsupported CACHE
integer ALU pipeline
Integer Overflow exception
integer queue
integer
queue
branch instructions
divide instructions
multiply instructions
ports
shift instructions [1] [2]
interface, external
internal coherency conflicts
internal processor clock domain
Interrupt exception
interrupt mask, bit
Interrupt register
interrupt request, external
interrupts
hardware
nonmaskable
software
timer
invalid operation, FP
invalidate request, external
invalidation, and CACHE instructions
ISA (Instruction Set Architecture)
MIPS II
MIPS IV
MIPS I
MIPS III
MIPS IV
issue, dynamic
issuing, an instruction
iterative execution units
ITLB (instruction TLB)
ITLBM, field