17.3 TLB Refill Vector Selection
In the R4400 processor, a Virtual Coherency exception occurs when a primary cache miss hits in the secondary cache but VA[14:12] are not the same as the PIdx field of the secondary cache tag, and the cache algorithm specifies that the page is cached. When such a situation is detected in the R10000 processor, the primary cache lines at the old virtual index are invalidated and the PIdx field of the secondary cache is written with the new virtual index.