stalls usually delay all subsequent instructions.
A clever compiler can improve performance by re-arranging instructions to reduce the frequency of these stall cycles.
- In an in-order superscalar processor, several consecutive instructions may begin execution simultaneously, if all their operands are valid, but the processor stalls at any instruction whose operands are still busy.
- In an out-of-order superscalar processor, such as the R10000, instructions are decoded and stored in queues. Each instruction is eligible to begin execution as soon as its operands become valid, independent of the original instruction sequence. In effect, the hardware rearranges instructions to keep its execution units busy. This process is called dynamic issuing.