10. CACHE Instructions
All parity and ECC errors caused by Index Load Tag (D) are ignored.
The following mapping defines the operation:
TagLo[6:0] = Tag ECC bits
TagLo[8:7] = Virtual index bits
TagLo[11:10] = State bits
TagLo[31:14] = Tag[35:18]
TagHi[3:0] = Tag[39:36]
TagHi[31] = MRU Bit
All other CP0 TagLo and TagHi register bits are set to 0.