1.3 What is an R10000 Microprocessor?
R10000 Superscalar Pipeline
The R10000 superscalar processor f
etches and decodes four instructions in parallel each cycle (or pipeline stage). Each pipeline includes stages for fetching (stage 1 in
Figure 1-4
), decoding (stage 2) issuing i
nstructions (stage 3), reading register operands (stage 3), executing instructions (stages 4 through 6), and storing results (stage 7).
Figure 1-4
Superscalar Pipeline Architecture in the R10000
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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