4. Cache Organization and Coherency
The instruction cache has a fixed block size of 16 words and is two-way set associative with a least-recently-used (LRU) replacement algorithm.*1
The instruction cache is indexed with a virtual address and tagged with a physical address.
Figure 4-1 Organization of Primary Instruction Cache
Each instruction cache block is in one of the following two states:
Figure 4-2 Primary Instruction Cache State Diagram
An instruction cache block can be changed from one state to the other as a result of any one of the following events:
These events are illustrated in Figure 4-2, which shows the primary instruction cache state diagram.