14. Coprocessor 0
read-only register that handles ECC errors in the secondary cache or system interface, and parity errors in the primary caches.
R10000 processor correction policy is as follows:
- Parity errors cannot be corrected.
- Single-bit ECC errors can be corrected by hardware without taking a Cache Error exception.
- Double-bit ECC errors can be detected but not corrected by hardware.
- All uncorrectable errors take Cache Error exceptions unless the DE bit of the Status register is set.
- As in the R4400, cache errors are imprecise.
The CacheErr register provides cache index and status bits which indicate the source and nature of the error; it is loaded when a Cache Error exception is taken.