C


cache
Cache Barrier CACHE instruction
Cache Error exception [1] [2]
   precision
   prioritization
Cache Error handler
CACHE instruction
   support for I/O
CACHE instructions [1] [2] [3] [4]
   effect on the uncached buffer
   and a hit in the cache
   and Address Error exception
   and CE bit
   and CH bit
   and CP0
   and invalidation
   and TLB Invalid exception
   and TLB Refill exception
   and Watch exception
   and write back
   Cache Barrier
   Hit Writeback Invalidate
   Index Hit Invalidate
   Index Invalidate
   Index Load Data
   Index Load Tag [1] [2] [3] [4] [5] [6] [7]
   Index Store Data
   Index Store Tag
   Index Writeback Invalidate
   op field encoding
   serial operations
   unsupported instructions
   using the physical address
   using the virtual address
cache miss stalls
cache test mode
   entry
   exit
cache
   algorithms
      and processor requests
      cacheable coherent exclusive on write, description of
      cacheable coherent exclusive, description of
      cacheable noncoherent, description of
      fields, encoding of
      for kseg0 address space
      for mapped address space
      for xkphys address space
      uncached accelerated, description of
      uncached, description of
      where specified
   block ownership
   nonblocking
   primary data
      refill
      block size
      changing states
      description of
      diagram, state
      index and tag
      interleaving
      state diagram
      states
      subset of secondary cache
      write back protocol
   primary instruction
      refill
      block size
      description of
      diagram, state
      index and tag
      state diagram
      states
   rules, ownership of a cache block
   secondary
      associativity
      block size
      block state
      changing states
      data array
      data array width
      description of
      diagram, state
      index and tag
      indexing the data array
      indexing the tag array
      interface frequencies
      specifying block size
      specifying cache size
      state diagram
      states
      tag
      tag and data array ECC
      tag array
      way prediction
      write back protocol
   associativity
   misses
   ordering constraints
   pages
   primary
   primary data
      error handling
   primary instruction
      error protection
   secondary
      associativity
      blocks
      sizes
      clock domain
      ECC
      error handling
      indexing
      way prediction table
   strong ordering
      example of
   structure, two-level
cacheable coherent exclusive on write, cache algorithm [1] [2]
cacheable coherent exclusive, cache algorithm [1] [2]
cacheable noncoherent, cache algorithm [1] [2]
cached request buffer [1] [2]
CacheErr register [1] [2] [3] [4] [5]
CacheOp, see also CACHE instructions [1] [2]
capacitors, decoupling
cause bits, FPU
Cause register [1] [2] [3] [4] [5]
Cause, field (FP)
CE, bit [1] [2]
CH, bit [1] [2]
chip revisions, R10000
ckseg0 space
ckseg1 space
ckseg3 space
cksseg space
CLGA (ceramic land grid array)
   layout
   electrical characteristics
   mechanical characteristics
   package
   pinout
   thermal characteristics [1] [2]
clock
   domain
      secondary cache clock domain
clock divisor, system interface [1] [2]
clock
      in secondary cache
      internal processor clock domain
      System interface clock domain
   signal
      PClk
      SCClk
      SysClk
      SysClkRET
cluster bus [1] [2]
   operation
cluster coordinator [1] [2]
cluster request buffer [1] [2]
coherency conflicts
coherency protocol, directory-based
coherency request, external
coherency schemes
coherency, System interface
   external intervention exclusive request
   external intervention shared request
   external invalidate request
CohPrcReqTar, mode bit [1] [2] [3]
cold reset
Cold Reset exception
cold reset
   sequence
Compare register [1] [2]
completing, an instruction
completion, definition of
condition bit dependencies
Condition, field (FP)
conditional move instruction (FP)
Config register
conflicts
   coherency
      external
      internal
   TLB, avoiding
Context register [1] [2]
context switch
control registers, FPU
controller, TAP
coordinator, cluster
COP1 instructions
COP2 instructions
Coprocessor 0, see also CP0
Coprocessor 1 see also CP1, COP1
Coprocessor 2 see also CP2, COP2
Coprocessor 3 see also CP3, COP3
Coprocessor Unusable exception
correctable error
Count register [1] [2]
CP0 (coprocessor 0)
   hazards
   instructions
   branch on CP0 instructions
   instructions
   load hazards
   move instructions
   registers, list of
csseg space
CTM, mode bit [1] [2]
CU, (coprocessor usability) field [1] [2]
CVT.L.fmt instruction