10. CACHE Instructions

10.2 Index Invalidate (I)


Index Invalidate (I) sets a block in the primary instruction cache to Invalid. VA[13:6] defines the address and VA[0] defines the way to be invalidated.

The invalidation takes place by writing the primary instruction cache state bit to 0 (Invalid). This also sets the instruction cache state parity bit to 0.

The LRU bit does not change.

Parity check is suppressed.




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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