
5. Secondary Cache Interface

5.2 Secondary Cache Interface Frequencies
The secondary cache interface operates at the frequency of SCClk, which is derived from PClk. The SCClkDiv mode bits select a PClk to SCClk divisor of 1, 1.5, 2, 2.5, or 3, using the formula described in Chapter 7, the section titled "Secondary Cache Clock."
Synchronization between the PClk and SCClk is performed internally and is invisible to the system. The processor supplies six complementary copies of the secondary cache clock on SCClk(5:0) and SCClk(5:0)*.

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96



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