14.22 CacheErr Register (27)

CacheErr Register Format for System Interface Errors


Figure 14-27 shows the format of the CacheErr register when a System interface error occurs.



Figure 14-27 CacheErr Register Format for System Interface Errors

EW: set when CacheErr register is already holding the values of a previous error

EE: data error on a CleanExclusive or DirtyExclusive

D: uncorrectable system block data response error (way1 || way0)

SA: uncorrectable system address bus error

SC: uncorrectable system command bus error

SR: uncorrectable system response bus error

SIdx: secondary cache physical block index


0: Reserved. Must be written as zeroes, and returns zeroes when read. (See page 224 of Errata.)





Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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