
15.3 Floating-Point General Registers (FGRs)

32- and 64-Bit Operations
The FR bit (26) in the Status register determines the number of logical floating-point registers available to the program, and it alters the operation of single-precision load/store instructions, as shown in Figure 15-2.
- FR is reset to 0 for compatibility with earlier MIPS I and MIPS II ISAs, and instructions use only the 16 physical even-numbered floating-point registers (32 logical registers). Each logical register is 32 bits wide.
- FR is set to 1 for normal MIPS III and MIPS IV operations, and all 32 of the 64-bit logical registers are available.

Figure 15-2 Floating-Point Registers

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96



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