L


latency
   accessing secondary cache
   definition of
   external coherency request
   FPU
least-recently used replacement algorithm (LRU)
level sensing, input
list, free
LL instruction
LLAddr register
load hazards, CP0
load linked
load operations, FPU registers
Load/Store Unit pipeline
loads
   nonblocking
logic diagram, FPU
logical register, see also physical register
logical register
   initialization (necessity for)
LRU (least-recently used) replacement algorithm