P


package configuration
package, see CLGA
page table entry (PTE) array
page
   address
   size
      code
      defined
   offset
   size
      in TLB
   virtual
PageMask register [1] [2] [3]
parity protection
PClk, signal [1] [2] [3] [4]
pending response
Performance Counter interrupt
Performance Counter register
performance
   branch prediction
   cache
   R10000 [1] [2]
permanent register
PFN
   bits
   fields, in EntryLo registers
phase-locked loop
physical address [1] [2]
physical memory addresses
physical page frame number
physical register, see also logical register
PIdx, primary cache index
pipeline
   fetch
   stage 1 [1] [2]
   stage 2
   stages 4-6
   definition of
   fetch
   floating-point
   floating-point multiplier
   integer ALU
   latency
   Load/Store Unit
   out of order execution
   repeat rate
   sequence
   stage (definition)
   stalls
PLL
PLLDis, signal [1] [2]
PLLRC, capacitor
PLLSpare, signals
power interface signals, see also individual signals
power supply
   levels, DC
   regulation
power-on reset
   sequence
PrcElmReq, mode bit [1] [2] [3]
PrcReqMax, mode bits [1] [2]
precise exceptions
prediction, branch
prediction, secondary cache, way
prefetch instruction
primary data cache, see also cache, primary data
primary instruction cache, see also cache, primary instruction
processor block read request protocol
processor block write request
   protocol
processor coherency data response [1] [2]
processor coherency state response protocol
processor double/single/partial-word read request protocol
processor double/single/partial-word write request protocol
processor eliminate request protocol
processor request [1] [2]
   flow control protocol
   protocol
processor response [1] [2]
   protocols
Processor Revision Identifier (PRId) register
processor upgrade request
   protocol
processor-specific instructions
program order
   dynamic execution
   instruction completion
   instruction decoding
   instruction execution
   instruction fetching
   instruction graduation
   instruction issue
protection
   memory
   ECC
   parity
   SECDED
   sparse encoding
protocol
   write back
   write invalidate cache coherency
   arbitration, System interface
   error handling
PTE (page table entry)