9. Error Protection and Handling

9.5 CP0 CacheErr Register EW Bit


When a unit detects an uncorrectable error, it records information about the error in its local CacheErr register and posts a Cache Error exception. If a subsequent uncorrectable error occurs while waiting for the Cache Error exception to be taken and transfer of the local CacheErr register to the CP0 CacheErr register to complete, the EW bit is set in its local CacheErr register. Once the Cache Error exception is taken, the EW bit in the CP0 CacheErr register is set and the Cache Error exception handler now determines that a second error has occurred.

Once the CP0 CacheErr register EW bit is set, it can only be cleared by a reset sequence.




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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