6.14 Interrupts
An external interrupt request consists of a single address cycle on the System interface. During the address cycle, SysAD[63:60] specify the target indication, which allows an external agent to define the target processors of the external interrupt request. If a processor determines it is an external interrupt request target, SysAD[20:16] are the write enables for the five individual Interrupt register bits and SysAD[4:0] are the values to be written into these bits, as shown in Figure 6-5. This allows any subset of the Interrupt register bits to be set or cleared with a single external interrupt request.
The Interrupt register is an architecturally transparent, level-sensitive register that is directly readable as bits 14:10 of the Cause register. Since it is level-sensitive, an interrupt bit must remain asserted until the interrupt is taken, at which time the interrupt handler must cause a second external interrupt request to clear the bit.
The processor clears the Interrupt register during any of the reset sequences.
Figure 6-5 Hardware Interrupts