1.8 R10000-Specific CPU Instructions

SYNC


The SYNC instruction is implemented in a "lightweight" manner: after decoding a SYNC instruction, the processor continues to fetch and decode further instructions. It is allowed to issue load and store instructions speculatively and out-of-order, following a SYNC.

The R10000 processor only allows a SYNC instruction to graduate when the following conditions are met:

A SYNC instruction is not prevented from graduating if the uncached buffer contains any uncached accelerated stores.




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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