14. Coprocessor 0

14.22 CacheErr Register (27)


The CacheErr register is a 32-bit
read-only register that handles ECC errors in the secondary cache or system interface, and parity errors in the primary caches.

R10000 processor correction policy is as follows:

The CacheErr register provides cache index and status bits which indicate the source and nature of the error; it is loaded when a Cache Error exception is taken.




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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