4.4 Cache Algorithms
Store hits to a Shared block result in a processor upgrade request. This indicates to external agents containing caches that the block must be invalidated.
There is no difference between an uncached accelerated load and an uncached load. Only word or doubleword stores can take advantage of this mode.
Stores under the Uncached accelerated cache algorithm bypass the primary and secondary caches. Stores to identical or sequential addresses are gathered in the uncached buffer, described in Chapter 6, the section titled "Uncached Buffer."
Completely gathered uncached accelerated blocks are issued to the System interface as processor block write requests. Incompletely gathered uncached accelerated blocks are issued to the System interface using processor double/single-word write requests; this is also described in Chapter 6, the section titled "Uncached Buffer."
Uncached
Loads and stores under the Uncached cache algorithm bypass the primary and secondary caches. They are issued directly to the System interface using processor double/single/partial-word read or write requests.Cacheable Noncoherent
Under the Cacheable noncoherent cache algorithm, load and store secondary cache misses result in processor noncoherent block read requests. External agents containing caches need not perform a coherency check for such processor requests. Cacheable Coherent Exclusive
Under the Cacheable coherent exclusive cache algorithm, load and store secondary cache misses result in processor coherent block read exclusive requests. Such processor requests indicate to external agents containing caches that a coherency check must be performed and that the cache block must be returned in an Exclusive state.Cacheable Coherent Exclusive on Write
The Cacheable coherent exclusive on write cache algorithm is similar to the Cacheable coherent exclusive cache algorithm except that load secondary cache misses result in processor coherent block read shared requests. Such processor requests indicate to external agents containing caches that a coherency check must be performed and that the cache block may be returned in either a Shared or Exclusive state.Uncached Accelerated
The R10000 processor implements a new cache algorithm, Uncached accelerated. This allows the kernel to mark the TLB entries for certain regions of the physical address space, or certain blocks of data, as uncached while signalling to the hardware that data movement optimizations are permissible. This permits the hardware implementation to gather a number of uncached writes together, either a series of writes to the same address or sequential writes to all addresses in the block, into an uncached accelerated buffer and then issue them to the system interface as processor block write requests. The uncached accelerated algorithm differs from the uncached algorithm in that block write gathering is not performed.
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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