5.6 Read Sequences
Figure 5-3 depicts a secondary cache 4-word read sequence. A quadword is read from the index specified by PA(23:6), and the way specified by VA(0) of the CACHE instruction.
The doubleword specified by VA(3) is then stored into the CP0 TagHi and TagLo registers, and the corresponding check bits are stored into the CP0 ECC(9:0) register. The data may be examined by copying the CP0 TagHi, TagLo, and ECC registers to the general registers with the MTC0 instruction.
Figure 5-3 4-Word Read Sequence