5.5 Secondary Cache Tag
The PIdx field contains VA(13:12), which are the two lowest virtual address bits above the minimum 4 Kbyte page size. This field is written into the secondary cache tag during a secondary cache refill. For each processor-initiated secondary cache access, the virtual address bits are compared with the PIdx field of the secondary cache tag. If a mismatch occurs, a virtual coherency condition exists and the value of the PIdx field is used by internal control logic to purge primary cache locations, so that all primary cache blocks holding valid data have indices known to the secondary cache. This mechanism, unlike that of the R4400 processor, is implemented in hardware. It helps preserve the integrity of cached accesses to a physical address using different virtual addresses, an occurrence called virtual aliasing. For each external coherency request, the PIdx field of the secondary cache tag provides a mechanism to locate subset lines in the primary caches.