5.3 Secondary Cache Indexing

Indexing the Tag Array


The processor supplies the secondary cache tag array's least significant index bit on SCTagLSBAddr to support two block sizes without system hardware changes. This signal functions normally as a least significant index bit when the secondary cache block size is 16 words. However, when the secondary cache block size is 32 words, this signal is always negated, since only half as many tags are required. The processor supplies the secondary cache tag way on SCTWay.

Table 5-2 presents the secondary cache tag array index for each secondary cache size; it shows each index is composed of a physical address loaded onto SC(A,B)Addr(), concatenated with SCTWay and SCTagLSBAddr.

Table 5-2 Secondary Cache Tag Array Index

For a system design that only supports a secondary cache block size of 32 words, the secondary cache tag array need not use SCTagLSBAddr as an index bit.




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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