A
AC electrical specifications
asynchronous inputs
delay time
hold time
maximum operating conditions
setup time
test specification
timing
secondary cache
System interface
access privileges, address space
ACK completion response
ACK, signal
active list, definition of
add unit, FPU
Address Error exception
Address Space Identifier, see also ASID
address
calculation of
encodings, mode
mapping
Kernel mode
Supervisor mode
User mode
mode
page
queue [1] [2]
instruction graduation
issue ports
number of entries
number of instructions written per cycle
organized as FIFO
sequencing
space
access privileges
kernel
supervisor
user
virtual
translation
Kernel mode
physical
Supervisor mode
User mode
virtual
AdEL, indication
AdES, indication
algorithms
cache, five types of [1] [2]
aliasing, virtual
allocate request number requests, external
ALU (arithmetic logic unit)
No. 1
No. 2
ALU1 [1] [2]
ALU2 [1] [2]
ANDES, Architecture with Non-sequential Dynamic Execution Scheduling [1] [2]
arbitration protocol, System interface
arbitration rules, System interface
arbitration, cluster bus
Architecture with Non-sequential Dynamic Execution Scheduling, see also ANDES
arithmetic instructions, FPU
arithmetic logic unit, see also ALU
array, page table entry (PTE)
ASID (Address Space Identifier)
context switch
relationship to Global (G) bit in TLB entry
ASID (Address Space Indentifier)
stored in EntryHi register
asynchronous inputs, AC electrical specification
auto-increment read, cache test mode
auto-increment write, cache test mode