17.3 TLB Refill Vector Selection
The Soft Reset exception occurs in response to a Soft Reset (See Chapter 8, the section titled "Soft Reset Sequence").
A Soft Reset exception is not maskable.
The processor differentiates between a Cold Reset and a Soft Reset as follows:
Processing
When a Soft Reset exception occurs, the SR bit of the Status register is set, distinguishing this exception from a Cold Reset exception.
When a Soft Reset is detected, the processor initializes minimum processor state. This allows the processor to fetch and execute the instructions of the exception handler, which in turn dumps the current architectural state to external logic. Hardware state that loses architectural state is not initialized unless it is necessary to execute instructions from unmapped uncached space that reads the registers, TLB, and cache contents.
The Soft Reset can begin on an arbitrary cycle boundary and can abort multicycle operations in progress, so it may alter machine state. Hence, caches, memory, or other processor states can be inconsistent: data cache blocks may stay at the refill state and any cached loads/stores to these blocks will hang the processor. Therefore, CacheOps should be used to dump the cache contents.
After the processor state is read out, the processor should be reset with a Cold Reset sequence.
A Soft Reset exception preserves the contents of all registers, except for:
A Soft Reset exception is intended to quickly reinitialize a previously operating processor after a fatal error.
It is not normally possible to continue program execution after returning from this exception, since a SysReset* signal can be accepted anytime.
Servicing
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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