5.6 Read Sequences

4-Word Read Sequence


A 4-word read sequence is performed by a CACHE Index Load Data (S) instruction to read a doubleword of data and 10 check bits from the secondary cache data array.

Figure 5-3 depicts a secondary cache 4-word read sequence. A quadword is read from the index specified by PA(23:6), and the way specified by VA(0) of the CACHE instruction.

The doubleword specified by VA(3) is then stored into the CP0 TagHi and TagLo registers, and the corresponding check bits are stored into the CP0 ECC(9:0) register. The data may be examined by copying the CP0 TagHi, TagLo, and ECC registers to the general registers with the MTC0 instruction.



Figure 5-3 4-Word Read Sequence




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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