10. CACHE Instructions

10.7 Index Load Tag (S)


Index Load Tag (S) reads the secondary cache tag fields into the CP0 TagLo and TagHi registers. The PA[Cachesize-2..Blocksize] defines the address and PA[0] defines the way to be read.

All parity and ECC errors caused by Index Load Tag (D) are ignored.

The following mapping defines the operation:

TagLo[6:0] = Tag ECC bits

TagLo[8:7] = Virtual index bits

TagLo[11:10] = State bits

TagLo[31:14] = Tag[35:18]

TagHi[3:0] = Tag[39:36]

TagHi[31] = MRU Bit

All other CP0 TagLo and TagHi register bits are set to 0.




Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96


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