used in the R10000 processor.
The format of the CACHE instruction is:
CACHE op, offset(base)
In a CACHE instruction, the 16-bit offset is sign-extended and added to the contents of the general register base to form a Virtual Address (VA). The VA is translated to a Physical Address (PA) using the TLB. The 5-bit sub-opcode specifies a cache instruction variation for that address.
Chapter Contents
- 10.1 - Notes on CACHE Instruction Operations
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- 10.2 - Index Invalidate (I)
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- 10.3 - Index WriteBack Invalidate (D)
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- 10.4 - Index WriteBack Invalidate (S)
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- 10.5 - Index Load Tag (I)
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- 10.6 - Index Load Tag (D)
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- 10.7 - Index Load Tag (S)
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- 10.8 - Index Store Tag (I)
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- 10.9 - Index Store Tag (D)
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- 10.10 - Index Store Tag (S)
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- 10.11 - Hit Invalidate (I)
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- 10.12 - Hit Invalidate (D)
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- 10.13 - Hit Invalidate (S)
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- 10.14 - Cache Barrier
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- 10.15 - Hit Writeback Invalidate (D)
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- 10.16 - Hit WriteBack Invalidate (S)
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- 10.17 - Index Load Data (I)
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- 10.18 - Index Load Data (D)
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- 10.19 - Index Load Data (S)
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- 10.20 - Index Store Data (I)
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- 10.21 - Index Store Data (D)
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- 10.22 - Index Store Data (S)
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Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96



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