R
R10000 processor
ANDES architecture
caches
execution pipelines
geometry
pipeline stages
superscalar pipeline
overview
R4000 superpipeline
Random entries
Random register
RE, (reverse endian) bit
read port, FPU
read sequences
32-word
4-word
8-word
tag
16-word
reference voltage
DC
register
dependency
renaming
Status
ERL bit
EXL bit
USL field
write before reading (necessity for)
BadVAddr [1] [2] [3]
boundary scan, JTAG
bypass, JTAG
CacheErr [1] [2] [3] [4] [5]
Cause [1] [2] [3] [4] [5]
Compare [1] [2]
Config
Context [1] [2]
Count [1] [2]
CP0 (description of)
dependency
Diagnostic
ECC [1] [2] [3]
EntryHi
EntryLo0
EntryLo1
EPC
Error Exception Program Counter (ErrorEPC)
Exception Program Counter (EPC)
file
FPU
ports
FrameMask [1] [2]
Index
instruction, JTAG
LLAddr
logical, see also physical register [1] [2]
PageMask [1] [2]
Performance Counter
permanent
physical, see also logical register [1] [2]
Processor Revision Identifier (PRId)
Random
renaming [1] [2]
Status [1] [2]
SX bit
TS bit
UX bit
TagHi [1] [2] [3]
TagLo [1] [2] [3]
temporary
unnamed
WatchHi
WatchLo
Wired [1] [2]
XContext
renaming, register
repeat rate
accessing secondary cache
definition of
FPU
replacement algorithm, cache
request cycle
request number
freeing with completion response
Reserved Instruction exception
reset
cold [1] [2]
power-on [1] [2]
soft (warm) [1] [2]
response cycle
revision number, R10000 processor
RM, field (FP)
RN, field (FP)
rounding modes, in FSR
RP, (reduced power) bit
RP, field (FP)
rules, arbitration for System interface
RZ, field (FP)