T


table
   busy-bit
   mapping
tag bus, secondary cache, SCTag
tag read sequence
tag write sequence
TagHi register [1] [2] [3]
TagLo register [1] [2] [3]
tags, external, duplicate
TAP controller [1] [2]
TCA, signal
TCB, signal
temporary register
test access port (TAP)
test interface signals, see also individual signals
test mode, cache [1] [2]
Timer interrupt
   disabling
TLB [1] [2]
TLB (Translation Lookaside Buffer)
   JTLB
TLB Invalid exception [1] [2]
TLB Modified exception
TLB Probe (TLBP) instruction [1] [2]
TLB Read (TLBR) instruction
TLB Read Indexed (TLBR) instruction
TLB Refill
TLB Refill exception [1] [2]
TLB Write Indexed (TLBWI) instruction [1] [2]
TLB Write Random instruction [1] [2]
TLB
   number of entries
   physical address
   32-bit-mode entry format
   64-bit-mode entry format
   address
      calculation
      translation, avoiding multiple matches
   ASID field
   avoiding conflict
   Cache Algorithm fields
   entry formats
   exceptions
   Global (G) bit
   ITLB
   misses
   multiple matches, avoiding
   number of entries
   page size code
   used with Context register
TLBP, instruction
TLBR, instruction
TLBWI, instruction
TLBWR, instruction
Translation Look-Aside Buffer, see also TLB
translation, virtual address [1] [2]
Trap exception
trap physical address, and Watch registers
TriState, signal
TS, (TLB shutdown) bit
TS, bit, in Status register
two-level cache structure