UWVFP( FP0 ‹؋F&O F&G&G<ʋЋ™Ƌ$6&~&6&F&9EtL2pP3P F&EĞ&(6&>pt*6&>vt TF&EF,6&>~FvFĞ&^&9~Ì~ڹ-F*Ftz8ft F^&8Gui~t F^&8GuWF+F;F| F9Fu~tF@t8F^&8Gt,F+F;F~<.6&>t0^&GĞ&v&@F[FF,6&9~2F^&8Gu FuӋvzvĞ&7X06&?&&DPĞ&&& 26&>|u 46&z66&^&Gȋƻ[؎86&>&I86&&a~t;F*PĞ&&& 46&zF*Pv:6&& ud26&>|u 46&zĞ&&& <6&6&6` P, >6&F&H t8PP  |FPPh P:6&6&6P  |FPPh P*6&>vt BlPP] @6&6&6`Ğ&&& pP B6&R&TĞ&7FD6&FF6& fĞ&7FtH6&&J6&H6&J6&f%=؎L6&FD6&FF6& ^_]ːUVN6&6 &6rP N6&6 &6"P vPrPh P"Ph FPrPXX @uNFP"PXX @uQN6&6 &6"P P6&6(&6&"Ph FP"PXX @uFV9Vvr9Fv~} ~[sPrPC uƆrPrPVj3 6d6brP  udpP~QPVj3 FPF-P86&6&6VP R6&[RPFV-RP ,6&V2 ^]UWV+PP( FVN6&6 &6FP N6&6 &64P PFPh P4Ph FP4PXX @uQN6&6 &64P P6&6(&6&4Ph FP4PXX @u3FV9Vw1r9Fs*FVFV06&X&& FVFVFVPPFPC uP6d6bVh4 pP~QPVh4 3,602&9?~Dv3ɉNރ,.&Gt &u&g[GĞ0&9?ЋvFP[Ğ0&/P86&6&6VW V2 FPFPR ^_]ːUTWVN6&6 &6FP PFPh PFP V t)FPVQpQ~RQx WV ^_]ːU"WVFP( FP0 V<&m&EFT6&F&M FF &EF~,6&F 86&&؉V$6&FN9Nu~t F&u|v&DF&8G tl&G *Fta&G:F t F&D8FuJF&G9F t F&D8Fu0Fw&F;FF&@t+~9~~~[A9N~a~}+FFf~@~F39N86&&>؉V~؃~t Fw&uZFw&*FtJF&F t F&8Eu4Fw&F t F&8EuFw&FF;F}F[A9N~V~t}^_]ːear all searchUWVP V t5P6  u$FPVVP VPƆVPVPh FPVPXX  t$VPP(P P ~WP V u P(P P P-PVP26 FV u$VP0P(P P vvWPvV ;t2VPLP(P vv P vv  t$VPwP(P P F  3RT&7&GLX"3NP&&G&MVv~~؎ZX&&+NjV&&PIuvĞN&F&7&GĞR&&&GÌV&$3& &> & & ߎ&&3&OF&&&ʋH(3JL&&G*3&&F&ʋFPQ" @FĞJ&&?~G~VvN~&&+NjV&&PAĞJ&&9ڋ~v*3&F&7&GĞJ&&@&GF,3&> & M.3& & ^_]ː&u0 U.WV4Z9&3\9&6^9&"`9& b9&r d9&bf9&dh9&fj9&h+ɉNNvvZ RP"Pr QP V^V۹^VNVl9&>nu-n9&X&B&@ "P| 3br QP t~ PvvP t!2PP] p9&tN릐2PP] p9&u, QP2PP] p9&u0 ~+PP( FVP+PP( ȋ+FV~9&&SQvvvVr FV~9&&d3SQRP FVdRPvv FVvvRP<RPSQRPvv⚺ RPFމVT SQvvމFډVܚT <3SQvvF։Vؚ FV؋Nڋ^+SQF҉VԚT +FVRPvvvvvvZ RPn9&X&r&p N~9&pr9^F&?tt9&>vt^&?t;^9&>"u\9&>6u `9&> tPvv^&?tMt9&>vtAPPv9&68&66`Px9&GPv9&68&66 tظ[.ظ&&،F&Gt1&9}&Gع&;z ~36&z F&9G|&F u &>tF&Gu & t~u &>tF&Gt & uPvvP t}pr9^F&?tMt9&>vtAPPv9&68&66`Px9&JPv9&68&66+PP( FVz9&>|u |9&z, QP |%^&?tMt9&>vtAPPv9&68&66`Px9&GPv9&68&66PvvPn9&X&F&D PvvPr9&>ptMt9&>vtAPPv9&68&66`Px9&GPv9&68&66^_]UWV P3Z9&P QP 9+&& ~ u19&9>"t2PP] p9&u |] u9&9&F |#[n9&&@t 9&2P P] =tz9&>|u |9&zr9&>ptt9&>vtT9&>"t2PP] p9&t t3Pt9&N& LtsdP FV|] t6~vv`  u!dP FV] |] u͚] 3P9&6N&6LtmpP FVRP`  tP~|] t@2P P] =t* vv`  t 3b2PP] p9&t;3PN^9&>"u\9&>6u `9&> t N(^_]ːUWV9 &?|%[&/9&&~ڹ-Ğ &?}^9&>"t5~t/F*Pn9&X&N&L F*P3~9&& t1B*PWn9&X&R&P B*PFF;r `9&?u \9&>6t?Ğ &?|5~t/F*Pn9&X&V&T F*PO9&& uĞ&?u\9&>6u^9&>"un9&X&Z&X 9&6&6` P, 9&6&6P Ğ &?|FPPh PPP] n9&X&^&\ 9&6&6`pP 9&R&T3^9&"\9&6Ğ&^_]ːU욀"P9&6&6n9&X&& 9&6&6`嚖t9&>vt9&63P] 9&>Ltr 9&>du.] v ]UVv u3, ȋƙ+T؋ʙùdP ^]ːUWV~9&B&DF&9Eu &9U u&E & Eu 9&&9&6&6KP KP" KF^F9&& u~N؋W&9Du&9T tGG u9&&V uVV‹&?u$~9&>t3"PvW ~^FFG&<u^&7"PvW_9&6&6KP KP" K^9&F&9t&9&>uF&5"PDvP K^_]ːUt9&>vur9&>pu3P, 9&@P"Pr QP PQ9&6&6`r QP9&6&6mcha^n Trung co^.ng. Ve^` bo^. chie^'n, dde^? cho^'ng la.i cuo^.c chie^'n tranh qui u+o+'cco^? ddie^?n, ddo^'i phobF t'P9&6&6"Pr QP $9&6&6 #Pr QP PQ9&6&6`#P9&6&6ZPP9&6&6`r QP9&6&6Z3P9&6^ ]ːt9&>vt&r9&>pt P9&6&6ːU.WV~FL^ }dǹ[FԻ9^֌F&&GtFLBƌ@V~t ‹F& ^&^&GtFF&C~t FF& ^&^&GtFF&D~t FF& ~t$^&^&G@tFF&FFF& ^&^&GtFF&H~t FF& ^&^&GtFF&K~t FF& ^&^&GtyFF&L~ti^&^&GF |@P+# +FP0#PFP FڌҋȎڋ6?t!vNG^F&=uv~~t$^&^&GtFF&MFF& ^&^&GtFF&N~t FF& ^&^&GtFF&S~t FF& ^&^&G tFF&R~t FF& ~t^~&=&At FF&XF&FL^_]ÐUt9&>vur9&>pu9&>u3P9&6+RP9&@P5#Pr QP PQ9&6&6`r QP9&6&6Z PP9&6&6`vv9&6&6ZT]UWV3Pz9`b&?}Tt9&>vuEWĞ`&@PXn9\^&&f&ddP PP9XZ&w&7`dPĞX&w&7ZPĞ`&7‹؋F&?tTPVĞ\&&j&hdP PPĞX&w&7`dPĞX&w&7Z9TV&G& u9&w&7dP A#PdPh PJ#PdP26 V uFPVQQNQ FWV ~uvrĞT&w&7dP M#PdPh 3PdQNQ*6 uqvFP ;PdPFP*6 t@2PPĞX&w&7`Ğ\&&n&lĞX&w&7ZT^_]R$bCLSU.WV4 ع4& &QP( 4+&,&*&(&0&.p4^F&9t&4&9vtotice and authorship remains intact. &?u-~ٹ~t%FFF4&F ~FFFP RP4&6&6 Pr QP r QPB FP RP Pr QP r QPB F ~js)+FFFFFF4^ތF&4&>v% 4^ڌF&4&>x ^&4& 4&9s 4&> t^&3PN։VRQQD~u QPP  tuHtpHtHHtMc uW^&^&ub4&h4&d4&X&& 뤚 u ^&^&u2봎4&h3P4&T4&ht F҉NԐ3^&9?~14&t&4 QPF  uG^&9?ҚHuHuGHtvHu}W4&t ;E2PP] 4&u)FPP 3PvvָP4& u^&^&t4&d4&h4&X&&  u^&^&t밐62PP] 4&u_4&>tPFPP 3PvvָP"2PP] 4&uFFPQ F4&^&?tp4&>vtd4&6&6 Pr QP PP4&6&6`r QP4&6&6ZT4&h3PO QPP 4&^&?tp4&>vtd4&6&6 Pr QP PP4&6&6`r QP4&6&6ZT4&T4&h QPP 4&^&?tp4&>vtd4&6&6 Pr QP PP4&6&6`r QP4&6&6ZT3P5& 5&b4&d5&f4&hPvvָPf3PvvָPQ^_]WV+ &&r & &6&"&& & ع^_ːUVXP FVRP`  uuv2PP] 4&tY uP2PP]  tFF& t*<t&P]  vv`  t'2PP] :] P ] 3^]ːU(WVb5&?u]v vFVF tHt#HuHuHu)F396F~(D Pv vWd u F;6F|ۋ~F &}t=&u&uvv PbP F &u/ PFP 2vvbP F &u&u8 PFP FLJFĞ&7bPE PP T PP V us5&& tZFLJFbP Ğ&7bPW PP f PP VF u-~ uyP4&X&>&< UFPV FPbPh bPP<  uX9F t!bP4&X&B&@ FDF^FFV ~~ t+v vZ RP4&X&F&D PB >Fuy396F~%D Pv vWd t F;6F|96F/~ u=v vZ RP4&X&J&H~F &}t=&u&uvvi PbP F &uy PFP 2vvbP F &u&u PFP F?t5&6&6bP FPbPh F;6F}rFFFFDFDFF+ƉF~vF^^F^FF F NuFbPB  u$9F ubP4&X&N&L?~ ubP4&X&R&P 5&& uĞ&7P PbP  PbP RP D5&& t-Ğ&7P PbP bPB 3^_]U($ 5^ތF&?u5^ڌF&G& u  t6 6 `  udP   5&bF tP^&w&7 PNFP ^&w&7 PNFP FPNFPXX  uDNFPB ^&74&X&&  5&z^&7]39&RzLxL9&9ptI9&9vt>PP9&6&6`#P9&6&6ZT#P| ] 9&$PP] P u 9&X&N&L 3n9&>ptJ9&>vt>PP9&6&6`#P9&6&6ZT$P| PV39&RzLxL9&9ptH9&9vt=PP9&6&6`&$P9&6&6ZT H$P| :] 9&$PP] 3PN tz9&>ptK9&>vt?PP9&6&6`S$P9&6&6ZTu$P| 3P u4^ːUWV9& & VȋڀFV$PSQ $PvW QPr9&QPZ RP$P 9&QPZ RPvW'3FF9&9~Q~9&9>t,$PvvPVZ RPvv G9&9>~$PvW89^F+&G&9Ft QP: '~uZzL0QP: ~9^&G& t-P&w&7vv< ^&GSvW%$PvW~t)9&>^u9&>`t$6$1$+9&t$PvW9&u$PvW$PvW9&> بt+& ~u:& #Ft&ِFtvt &6 بt$`~t6t$PvWt$PvWƨt3$"t$t$ ƨt$PvW9&t~t9&>zu$PvW$PvW$PvWw$PvWh9&>ju9&X&&$ډFVRP9&69&6$PP%Pvv vvvW%PvW9&6&69&6&6:&6&6#%Pvv vvvWB:&6&6:&6&6:&6&60%Pvv vvvW=%PvWD:&&&(0T|RPE%Pvv vvvW vW" 9&$PP] FpP FVv~vvO%PvV vV" PvVj! FPQ\%QJ] PvV" PvVJ] PvvvJ] F~~;~v^^؋NJ*3QNJ*&3ZF;v|։~v] v_%PvV PvV" PvVJ] FF=vP FVvv`  t 2PP]  :&uvv`  t|] u t 3P( -*ui%PvV vV2 ui6`#6^#vVF  uN6p#6n#vvF  t~9&X&&e%PFPW ƋFv2PP] 9&X&&V\2PP]  :&u9&X&&ˎ9&X&&k%PFPV NjFvW 3^_]U WVFdžPƆ{dž8o%:dždž@~%BdžD%FdžH%J+NL9& & vx~prt89 +&G&n9&9ptH9&9vt=PP9&6&6`%P9&6&6ZT %P| T :&P FVpP FV+FF{{<vv~uZ6`#6^#%P~V P~V" P~VJ] Tools: (From John Lazzaro ) Caltech VLSI CAD Tool Distribution We are offering to the Internet community a new revision of the Caltech electronic CAD system for analog VLSI neural networks. This distribution contains tools for schematic capture, netlist creation, and analog and digital simulation (log), IC mask layout, extraction, and DRC (wol), sim- ple chip compilation (wolcomp), MOSIS fabrication request generation (mosis), netlist comparison (netcmp), data plotting (view) and postscript graphics editing (until). These tools were used exclusively for the design and test of all the integrated circuits described in Carver Mead's book "Analog VLSI and Neural Systems". Until was used as the primary tool for figure creation for the book. The distribution also contains an example of an analog VLSI chip that was designed and fabricated with these tools, and an example of an Actel field-programmable gate array design that was simulated and converted to Actel format with these tools. These tools are distributed under a license very similar to the GNU license; the minor changes protect Caltech from liability. Highlights of the new revision includes: * Ports to new platforms (Supported platforms now include: Sun SPARC, Sun 3, HP Series 300/400/700/800, DEC MIPS-based Ultrix, Apple AU/X, linux, and IBM RS/6000 support). * Support for black and white displays, and resource database support for user preferences for sizing and placement of windows. New display modes in analog to support small screens. * Direct generation of SPICE netlists in analog, and new models for floating-well FET's, two-terminal devices with arbitrary i-v curves, and quantum-well tunnel diodes. * Many bug fixes for analog, wol, view, and until, and new features for view. If you are interested in some or all of these tools, 1) ftp to hobiecat.pcmp.caltech.edu on the Internet, 2) log in as anonymous and use your username as the password 3) cd pub/chipmunk 4) copy the file README, that contains more information. European researchers can access these files through anonymous ftp using the machine ifi.uio.no in Norway; the files are in the directory chip- munk. We are unable to help users who do not have Internet ftp access. A small but rather important bug was found in the "analog" program of the new Chipmunk distribution announced several weeks ago -- a key MOS transistor parameter was off by an order of magnitude! The current copies of the distribution on hobiecat.caltech.edu and ifi.uio.no have this bug corrected; however, if you've already picked up and installed the distri- bution since the new release (early april), here are the directions for patching your current installation w/o bringing over and rebuilding the whole package: 1) anonymous ftp to hobiecat.pcmp.caltech.edu, cd to pub/chipmunk 2) get the file models.cnf 3) in your distribution, use this file to replace log/lib/models.cnf That's it! Sorry for the inconvenience ... 36: Switcap2 (Current version 1.1): This is a switched capactor simulator. It is available from: SWITCAP Distribution centre, 411 Low Memorial Library, New York, N.Y. 10027. 37: Test Software based on Abramovici Text: (Contributed by Mel Breuer of the Univ. of Southern California) Many faculty are using the text by Abramovici, Breuer, and Fried- man entitled "Digital Systems Testing and Testable Design" in a class on testing. They have expressed an interest to supplement their course with software tools. At USC we have developed such a suite of tools. They include a good value simulator, fault simulator, fault col- lapsing module, and D-algorithm-based ATPG module for combinational logic. The software has been specifi- cally designed to be easily understood, modified and enhanced. The algorithms follow those described in the text. The software can be run in many modes, such as one module at a time, single step, interactively or as a batch process. Stu- dents can use the software "as is" to study the operation of the various algo- rithms, e.g. simulation of a latch using different delay models. Also, simple programming projects can be given, such as extend the simulator from a 3-valued system to a 5-valued system; or change the D-algorithm so that it only does single path sensiti- zation. There are literally over 50 interesting software enhancements that can be made by changing only a small part of the code. The system is written in C and runs on a SUN. If you are currently using the Abramovici text and would like a copy of this software, please send a message to Prof. Melvin Breuer at mb@poisson.usc.edu. 38: Test Generation and Fault Simulation Software (Contributed by Dr. Dong Ha of Virginia Tech) Two automatic test pattern generators (ATPGs) and a fault simula- tor for combinational circuits were developed at Virginia Tech, and the source codes of the tools are now ready for public release. ATLANTA is an ATPG for stuck-at faults. It is based on the FAN algorithm and a parallel-pattern, single-fault propaga- tion technique. It consists of optional sessions using random pattern testing, deterministic test pattern generation and test compaction. SOPRANO is an ATPG for stuck-open faults. The algo- rithm of SOPRANO is similar to ATLANTA except two consecutive patterns are applied to detect a stuck-open fault. FSIM is a parallel-pattern, single-fault simulator. All the tools are written in C. The source codes are fully commented, and README files contain user's manuals. Technical papers about the tools were presented at DAC-90 and ITC-91. All three tools are free to univer- sities. Companies are requested to make a contribution of $5000 but will have free technical assistance. For detailed in- formation, con- tact: Dr. Dong Ha Electrical Engineering Virginia Tech Blacksburg, VA 24061 TEL: 703-231-4942 FAX: 703-231-3362 dsha@vtvm1.cc.vt.edu 39:or DECStation and Sparcstation, although we are running it quite suc- cessfully at YSU under the CMS operation system on an Amdahl mainframe. Two new and helpful manuals are available for the simulator. They should be available at the Youngstown State University Bookstore, Youngs- town, OHio 44555: Their approximate cost should be $7 each: "WATAND Users Manual," by Dr. Phil Munro, Youngstown State University, April 1992, 233 pages, 10 chapters, 4 appendices, index. "WATAND Introduction and Examples," by Dr. Phil Munro, Youngstown State Unversity, June 1992, 204 pages, 12 chapters, index. Watand does *not* include digital simulation at this time, nor does it have any transmission-line elements. A self-heating BJT model has been developed and is proving useful. Monte Carlo statistical simulation is possible with dc and ac analyses using macro based analyses which have been developed at YSU. 35: Caltech VLSI CAD AD, connect to "eceserv0.ece.wisc.edu" using FTP. Log in as "anonymous" with password "guest". Galaxy is in directory "pub/galaxy". The file "README" in that directory gives further instruc- tions. Please register as a user by sending e-mail to "beetem@engr.wisc.edu". John F. Beetem ECE Department University of Wisconsin - Madison Madison, WI 53706 USA (608) 262-6229 beetem@engr.wisc.edu 43: WireC graphical/procedural system for schematic information (From Larry McMurchie ) WireC is a graphical specification language that combines schematics with procedural constructs for describing complex microelectronic systems. WireC allows the designer to choose the appropriate representation, either graphical or procedural, at a fine-grain level depending on the characteristics of the circuit being designed. Drawing traditional schematic symbols and their interconnections provides fast intuitive interaction with a circuit design while procedural constructs give the power and flexibility to describe circuit structures algorithmically and allow single descriptions to represent whole families of devices. The procedural capability of WireC allows other CAD tools to be incor- porated into the design system. For example, we have defined an inter- face to the SIS logic synthesis system wherein the designer can represent part of the system behaviorally. WireC invokes logic synthesis on these components to produce a structural description that can be incorporated into the rest of the design. Libraries of devices defining a particular netlist output format may be defined by the user. The libraries currently distributed with WireC include a default CMOS gate library whose output is the SIM format. This format can be simulated with COSMOS or IRSIM and compared against a cir- cuit extracted from layout. This library also includes devices that allow a behavioral description to be synthesized and mapped using MIS or SIS and incorporated into a larger circuit. Another library is the xnf library for designing systems with Xilinx FPGAs. Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC, this library contains devices specific to the 2000 and 3000 series Xilinx LCA's. In addition to drawing the devices explicitly, one can represent parts of a circuit with equations and have these synthesized automati- cally. Currently in progress is a library of CMOS gates for Cascade Design Automation's ChipCrafter product. WireC provides a mixed schematic/procedural design frontend for ChipCrafter, which uses module generation, timing analysis and place and route software to create a phy- sical layout from the WireC design specification. WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed Tellman. We are interested in any libraries you may develop and will provide a limited degree of support. WireC requires an X-Windows compatible environment and a C++ compiler such as Gnu G++ and AT&T CC. WireC is available via ftp on the Internet. For details send mail to larry@cs.washington.edu ebeling@cs.washington.edu 44: LateX circuit symbols for schematic generation (From Adrian Johnstone ) A set of circuit schematic symbols are available for use in LaTeX picture mode. The set includes all basic logic gates in four orientations, FETs, power supply pins, transmission gates, capacitors, resistors and wiring T-junctions. All pins are on a 1mm grid and the symbols are designed to be easily used with Georg Horn's TeXcad program: we even supply you with a palette picture file that displays all 52 symbols in a compact grid that you can cut and paste from within TeXcad. Each symbol lives in its own .mac file and is defined as a 'savebox' so as to reduce memory con- sumption. You must add the [bezier] option to your 'documentstyle' com- mand. A small manual is provided in both Postscript and .dvi forms. The files lcircuit.zip and lcircuit.tar are available for anonymous ftp from cscx.cs.rhbnc.ac.uk (134.219.200.45) in directory pub/lcircuit. I will also be uploading them to various ftp servers in the coming week. 45: Tanner Research Tools (Ledit and LVS) (From Bhusan Gupta ) Low cost, yet very powerful commercial ASIC design tools are available from Tanner Research, Inc. in Pasadena, CA. These products are used by industry and universities alike. Tanner's products are nominally priced at $995 per program, with a combined package named L-Edit Pro available for $3,495 on the PC. Universities are offered a 75% discount. Here is a list of their current programs: L-EditTM : A full-custom layout editor with CIF and GDSII input/output. Features a 32-bit coordinate space, all-angle geometry, unlimited hierarchy and number of layers. The L-Edit Pro package includes L-Edit/DRC for design rule checking, L-Edit/SPR for automatic standard cell placement and routing, L-Edit/Extract for extracting transistors, capacitors, resistors and generic devices for SPICE-level simulation or comparison to a schematic and LVS ,a netlist comparison tool for topological and parametrical verification. Optional layout libraries are also available. T-Spice: Circuit level simulator (See item 41 for detail GateSimTM : Gate-level simulator. A full array of technology mapping libraries are also available. Products are available for the PC, Macintosh, Sun and Hp UNIX platforms. For more information contact Bhushan Mudbhary at Tanner Research (bhushan @ tanner.com), phone 818-792-3000 and fax 818-792-0300. 46: SIMIC, a full-featured logic verification simulator. (From comp.archives.msdos.announce) SIMIC is a full-featured logic verification simulator. It has been demonstrated that SIMIC can uncover a number of critical design errors that other simulators miss. SIMIC has shown superior accuracy and throughput when compared to competitive products. Here are some of SIMIC's important features: - Mixed-mode simulation allows the free intermixture of true bilateral switches (ideal and resistive), gate, plus functional level built-in and user defined primitives. - A wide variety of output, whose detail, content and format are, to large extent, user defined. - A large repetoire of simulation options and controls that can be applied interactively, or in batch operation, and simplify trouble-shooting of your design. - Automated Test equipment emulation, allows debugging test programs using SIMIC troubleshooting techniques. - Sophisticated hazard analysis including: Spike, Pulse, Conflict, Oscillation, Setup, Hold, Pulse-width, Near (what-if) detection, among others. Hazard propagation is also supported. The student version of SIMIC is limited to a maximum of 500 elements (parts). In all other respects it is the same program as the commercial offering. The PC student version requires a 386 or better and at least 2 Meg of memory. Both a DPMI and a VCPI version are included in the pack- age. Both versions require EMS *NOT* be disabled. SIMIC is also avail- able on Sun and other platforms. The latest version is 1.02.00. The changes from revision 1.00.04 are: Bug Fixes: - Rams properly handled by circuit compiler. - BTG (Ideal switches) compiled correctly with dynamic delays. - By-name pin connections accepted by circuit compiler. - JK Flip-flop timing checks can now be disabled. Enhancements: - Reduction in storage requirements for small RAMS. - Fault Sensitization analysis added. - Fault Simulation and grading added. This revision can be taken from oak.oakland.edu in pub/msdos/electrical, or wuarchive.wustl.edu in mirrors/msdos/electrical. The files in question are sim120bn.zip (Simic logic and fault simulator plus examples) and sim120dc.zip (Simic Engineering and User's Guides). 47: LASI CAD System, IC and device layout for IBM compatibles (from Mike Fitsimmons ) On behalf of the author I have uploaded to WSMR-SIMTEL20.Army.Mil: pd1: LASI41A.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASI41B.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASI41C.ZIP LASI v4.1 IC layout CAD prgm: unzip in LASIDEMO.ZIP LASI v4.1 DEMO drawing: unzip in The LASI CAD System has been developed to do integrated circuit and dev- ice layout on almost any IBM compatable personal computer. LASIDEMO is a small IC layout to be used as a demonstration when first learning to use LASI. I offered to pay the author for some sort of site license for this pro- gram, but he refused, saying that he actually wants educational institu- tions to use it for free. What a guy! 48: EEDRAW, an electrical/electronic diagramming tool for IBM compatibles (from ) I have uploaded to WSMR-SIMTEL20.Army.Mil: pd1: EEDRAW24.ZIP Electrical Engineering drawing (with layers) This is the 2.4 release of EEDRAW, an electrical/electronic diagramming tool for the IBM PC. pd1: EEDSRC24.ZIP C sources for EEDRAW24.ZIP program. TC/BC++ This is the source of the EEdraw 2.4 program. Please read the readme file in the primary archive for information on other source programs needed such as the Libary files. 49: MagiCAD, GaAs Gate Array Design through MOSIS (from Tom Smith ) The Mayo Graphical Integrated Computer Aided Design (MagiCAD) system is a package which provides a comprehensive design environment for the development of digital systems, from initial concept to post-layout verification of integrated circuits (ICs). MagiCAD focuses on the development of high-speed Gallium Arsenide (GaAs) gate array designs. Specialized electromagnetic simulation tools are provided to address high clock rate issues such as crosstalk and reflections, which become more important as clock rates exceed several hundred MHz or signal edge rates become less than 500 pico- seconds. MagiCAD provides all the necessary tools for high clock rate GaAs IC design, and is also integrated with non-Mayo circuit, logic, and fault simulators. MagiCAD provides a lower risk approach than full-custom design for universities wishing to perform digital GaAs design through MOSIS. This is done by providing a gate array design environment where low-level transistor design and layout issues have already been solved and abstracted into a technology library of pre-defined cells. This frees the student or researcher to solve the still challenging tasks of system and gate-level design and layout to get high clock rate chips fabricated through MOSIS that meet all specifications. MagiCAD supports hierarchical, top-down, middle-out, or bottom-up development styles. MagiCAD has been used in the design of many GaAs chips that have been successfully fabricated. The MagiCAD electromagnetic modeling tools have been used in the analysis of many actual packages, multi-chip modules (MCMs), and printed circuit boards (PCBs), uncovering and avoiding problems that are commonly associated with high-frequency, fast edge-rate designs. The Vitesse Fury (TM) GaAs VSC2K gate array is provided as a MagiCAD technology library, and has been used for both gra- duate and undergraduate student chip designs. Functionality that has been integrated into MagiCAD includes: o Vitesse VSC2K GaAs gate array technology library o Database which integrates all tools o Schematic entry through a general purpose graphics editor o Circuit simulator o Logic and timing simulators o Fault analysis o Place and route tools o Layout verification tools o Retargeting from generic design to specific technology o Output to standard GDSII format for mask creation o Electromagnetic analysis - Cross section entry with graphics editor - Multilayer multiconductor transmission line (MMTL) modeling - Network tool for solving cases with many transmission line components - Lossy and non-lossy cases - Frequency and time domain result displays - Used for analyzing complex design paths, through chip, MCM, and PCB The Vitesse VSC2K has the following characteristics: o HGaAs-2 (TM) process o 2700 available gates o Enhancement/depletion MESFET process o 80 signal pads o 2 GHz flip-flop toggle rates o 40 power, ground pads o 280 psec loaded gate delays o 2.4 watts maximum o 170 mils x 135 mils o ECL or TTL I/O o 132 pin LDCC package available o 2 routing layers