The PowerPC 603 RISC Microprocessor

Product Description

The PowerPC 603e(tm) microprocessor is a 32-bit implementation of the PowerPC(tm) family of Reduced Instruction Set Computer (RISC) microprocessors. The PowerPC 603 microprocessor provides both industry leading RISC performance and power management to the notebook and energy sensitive desktop markets. High performance is achieved through concurrent execution of up to five instructions in five parallel execution units: the fixed-point unit, floating point unit, branch unit, system unit and load/store unit. Low-power is delivered through a low power static design and dynamic power management with three power saving modes. It is this industry segment leading combination of high performance and low power that offers a competitive edge to the system developers using the PowerPC 603 microprocessor.

The 100 Mhz version extends the performance leadership of the PowerPC 603 microprocessor in notebooks and energy sensitive desktops. The design, enhanced for higher speed and performance, contains twice the cache size of the original PowerPC 603 microprocessor and extends its speed from 80 Mhz to 100 MHz.

The PowerPC Architecture(tm) is derived from IBM's Performance Optimized With Enhanced RISC (POWER(tm)) architecture The PowerPC Architecture shares all the benefits of POWER and is optimized for single-chip implementations.

Highlights

Power Management Unit

• Static low-power design
• Dynamic power management
• Hardware support for power saving modes
• Processor clock multiplier of lx, 1.5x, 2x, 2.5x, 3x, 3.5x, and 4x from bus clock

Instruction Fetching & Branch Unit

• 6-instruction prefetch queue
• Static branch prediction

Dispatch Unit

• Dispatches 2 instructions per cycle
• 4-stage pipeline: Fetch, Dispatch, Execute, and Complete

Load/Store Unit

• One cycle cache access

Fixed-Point Execution Unit

• One cycle add, subtract, shift, or rotate
• Hardware multiply and divide
• Thirty-two 32-bit General Purpose Registers

Floating-Point Unit

• Optimized for single-precision multiply/add
• IEEE-754 standard single and double-precision floating point arithmetic
• Thirty-two 32-bit General Purpose Registers

System Unit

• Executes Condition Register logical, special register transfer, and other system instructions
• Execute integer add/ compare instructions

Memory Management Unit

• 52-bit virtual and 32-bit real addressing
• 8 Block Address Translation registers
• 64-entry, 2-way data and instruction TLB
• Fast-trap mechanism for software reload TLB
• Support Big/Little-endian addressing

Cache Unit

• 16k, 4 way or 8k, 2 way set associative instruction cache
• 16k, 4 way or 8k, 2 way set associative data cache
• 3-state coherency
• Physically tagged and addressed
• Copy-back data cache
• Data coherency in hardware

Bus Interface Unit

• General purpose interface for a wide range of system configurations
• 32-bit address and 64- or 32-bit data bus
• Powerful diagnostic and test interface through the Common On-Chip Processor (COP) and IEEE 1149.1 (JTAG) interface

(C) International Business Machines Corporation 1995

Printed in the United States of America 1995

All Rights Reserved

IBM and the IBM logo are registered trademarks and IBM

Microelectronics is a trademark of the IBM Corporation.

POWER is a trademark licensed to International Business Machines Corporation. PowerPC is a trademark of International Business Corporation. PowerPC Architecture is a trademark of International Business Machines Corporation. PowerPC 603 is a trademark of International Business Machines Corporation.

All performance data contained in this publication was obtained in a specific environment, and is presented as illustration. The results obtained in other operating environments may vary.

This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility of liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE OFFERED IN THIS DOCUMENT.