PowerPC 604 RISC Microprocessor
100, 120, 133, 150MHz


Highlights
Dispatch Unit
  • 8-instruction buffer
  • Dispatches 4 instructions per cycle
Six Execution Units
  • Branch
  • 3 integer
  • Floating point (IEEE-754 single
    and double precision)
  • Load/store
Advanced CPU Design
  • Speculative execution past 2 unresolved branches
  • 16-entry reorder buffer
  • 2-entry reservation station per execution unit
  • Register renaming on GPR, FPR, and CH
Dynamic Branch Prediction
  • Branch prediction in fetch, decode and dispatch stages
  • 64-entry, fully associative branch target address cache
  • 512-entry branch history table
Caches
  • 16K bytes, 4-way set associative instruction cache
  • 16K bytes, 4-way set associative data cache
  • Non-blocking, write-thru or copy-back data cache
  • Byte parity on both caches
  • Software cache disable, locking and invalidate
Memory Management
  • 52-bit virtual and 32-bit real addressing 4 instruction,data block address translation registers
  • 128-entry, 2-way set associative instruction TLB
  • 128-entry, 2-way set associative data TLB
Multiprocessing Support
  • Coherent cache access (MESI)
  • Bus snooping
  • Separate data cache tag array
Bus Interface Unit
  • 32-bit address and 64-bit data buses with byte parity
  • 60x bus compatible (split transaction, pipelined)
  • An optional mode optimized for fast secondary cache
  • Up to 66 MHz bus clock
  • On-chip PLL to generate 1x, 1.5x, 2x or 3x processor clockfrom the bus clock
Software/System Support
  • Performance monitor functions
  • Instruction and data address breakpoints
  • Nap mode power management
  • IEEE 1149.1 (JTAG) interface








Product Description

The PowerPC 604TM microprocessor delivers the next generationof performance to the desktop, today. The PowerPC 604 processorline extends desktop performance beyond 200 SPECint92, and can delivergreater than twice the performance of most desktop processorsshipping today.

The PowerPC 604 RISC microprocessor is a 32-bit implementationof the PowerPC ArchitectureTM, and is software and bus compatiblewith thePowerPC 601TM and PowerPC 603TM microprocessors. It can sustaina maximum rate of 4 instructions per cycle to provide balancedhigh integer and floating point performance suitable for desktoppersonal computers, workstations and midrange servers.

The PowerPC 604 microprocessor uses a 6-stage pipeline to achieveits high speed design: fetch, decode, dispatch, execute, completionand writeback. It uses a superscalar design to provide six independentexecution units: branch, three integer, floating point and load/store.It also uses dynamic branch prediction techniques to enhance instructionprefetching as well as speculative execution techniques to takeadvantage of the improved instruction prefetching and multipleexecution units. Instructions are executed out-of-order, and arecompleted in-order to support precise exceptions.












Specifications
Technology: 0.5 micron CMOS, four levels of metal © International Business Machines Corporation 1995

Printed in the United States of America

10-95

All Rights Reserved

® IBM and the IBM logo are registered trademarks of the IBM Corporation.

TMPowerPC, the PowerPC logo, PowerPC Architecture, PowerPC 601, PowerPC 603 and PowerPC 604 are trademarks of the IBM Corporation.

The performance information contained in this document are estimates based on various assumptions, including, but not limited to, the characteristics of the systems that the products described in this document are incorporated. Such systems may not be presently available, and IBM makes no commitments to make such systems available in the future. All performance data contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. The information contained in this document (which includes, but is not limited to, the aforementioned performance information) is subject to change without notice.

The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not effect or change IBM's product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties.

THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for any damages arising directly or indirectly from any use of the information contained in this document.

IBM Microelectronics Division
1580 Route 52, Bldg. 504
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Tel: 1-800-POWERPC

The IBM home page can be found at http://www.ibm.com/

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Die Size: 12.4mm x 15.8mm, 196mm2
Number of Transistors 3.6 million (approx. 1.5 million for logic)
Performance:


Estimated 160 SPECint92, 165 SPECfp92 @ 100 MHz
Estimated 180 SPECint92, 180 SPECfp92 @ 120 MHz
Estimated 200 SPECint92, 200 SPECfp92 @ 133 MHz
Estimated 185-228 SPECint92 @ 150MHz*
*Dependent on memory and L2 subsystem components specified.
Power Supply: 3.3V
Power Dissipation (typ.) 14 W @ 100 MHz (est)
Signal I/O 171, CMOS/TTL compatible
Packaging: 304 pin CQFP or 256 pin BGA
Part Numbers: C4FP
IBM25PPC604FD-100-C
IBM25PPC604FD-120-C
IBM25PPC604FD-133-C
IBM25PPC604FD-150-E
BGA
IBM25PPC604BD-100-C
IBM25PPC604BD-120-C
IBM25PPC604BD-133-C
IBM25PPC604BD-150-E
UNITED STATES
AND CANADA

IBM Microelectronics Division
1580 Route 52, Bldg. 504
Hopewell Junction, NY
12533-6531

Tel: 1-(800)-POWERPC















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