PowerPC 601 100 MHz RISC Microprocessor
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Product Description
The IBM Microelectronics PowerPC 601 microprocessor is the first
implementation of the PowerPC family of Reduced Instruction Set
Computer (RISC) microprocessors It is a 32-bit implementation of the
PowerPC Architecture and achieves its performance through concurrent
execution of up to three instructions per cycle in its three parallel
execution units: the Fixed-Point unit, Floating-Point unit, and the Branch
Processing unit. The PowerPC product strategy addresses a broad range of
customer requirements: performance optimization at the high end, extreme
cost-sensitivity at the low end, and peak price-performanee in the mid
range.
The IBM Microelectronics 100MHz PowerPC 601 processor is a higher
performance processor which is functionally identical to the original
PowerPC 601 processor. The 100MHz processor was developed in a 0.5µ
CMOS technology with a high performance 2.5v, 0.25µm Leff device and
multilevel 1.8µm pitch wiring capability to achieve a higher performance,
lower power, and smaller die size processor.
Compared to the original PowerPC 601, the 100MHz PowerPC 601 is
packaged in a physically identical 304 pin Ceramic Quad Flat Pack with
improved electrical characteristics to minimize noise at the higher
performance. Input, output, and ground pin locations are identical to the
original PowerPC 601 processor. Positive power supply pins are divided
between 2.5V pins for internal circuits and either 5.0V or 3.3V pins for
the driver and receiver circuits.
Input and output signal levels arc identical to the original PowerPC 601
processor through the development of special driver and receiver circuits
that interface with the 2.5V internal eireuits. A more sensitive clock
receiver circuit was also developed to interface with the higher
performance clock signals.
The PowerPC Architecture is derived from the IBM Performance
Optimized with Enhanced RISC (POWERtm) architecture. The
PowerPC Architecture shares all of the benefits of the Power
Architecture but is optimized for single-chip implementations.
PowerPC 601 100Mhz Product Highlights
Instruction Queue & Dispatch Unit
- Up to three instructions dispatch per cycle
- Eight-word wide instruction fetch bus from cache
Branch Processing Unit
- Early exposition of branches effectively
producing zero cycle branches
- Four-entry translation shadow buffer
Fixed Point Execution Unit
- Most instructions execute in one cycle
- Hardware multiply and divide
- 32 - 32-bit general purpose registers
Floating Point Execution Unit
- IEEE-754 compliant single and double precision
- Hardware support for all data types
- Single cycle multiply-add instruction
- 32 - 64-bit general purpose registers
Memory Management Unit
- 52-bit virtual and 32-bit real addressing
- Four Block address translation registers
- 256 entry two-way set associative
TLB
- Big-or-little endian addressing
Cache Unit
- 32 KB, combined I and D, eight-way set associative
- Full set of cache control instructions
- Physically tagged and addressed
- Selectable (through MMU) store-in, store-through or non-cached modes
- Non-blocking
Memory Queue
- Two entry read queue, three entry write queue
- Memory coherency maintained in hardware through
bus snooping
Bus Interface Unit
- General purpose interface for a wide range of
system configurations
- 32-bit address bus, 64-bit data bus
- Operates at integer multiples of
processor cycle time
- Powerful diagnostic and test interface
- Graphics coprocessor support
Multiprocessor Support:
