1000 OPEN1,8,1,"0:RCV.OBJ
1010 [158] 700
1020 .OPT O1
1030 ; COPYRIGHT 1986 JACK BEDARD
1040 ;
1050 ; RECEIVE ASSEMBLED CODE VIA
1060 ; THE SERIAL [131] PORT.
1070 ;
1080 ; RECEIVES ADDRESS [164] S[164]RE
1090 ; (LOW[173]HIGH) [175] THE BYTE
1100 ; [164] S[164]RE THERE.
1110 ;
1120 PTR        [178] $FD
1130 U1[133]    [178] $DC0C
1140 U1ICR      [178] $DC0D
1150 U1CRA      [178] $DC0E
1160 UPDATE91   [178] $F6BC
1170 [144]       [178] $91
1180 ;
1190 OUTPUT     [178] %01000000
1200 SH[139]TREG   [178] %00001000
1210 DISABLALL  [178] %01111111
1220 ENABLE     [178] %10000000
1230 TIMERA     [178] %00000001
1240 ;
1250 [172][178] 828 ;[203]ES IN CASSETTE BUFFER
1260 ;
1261 ;
1270 TSX          ;[148] STACK PTR [129]
1280 STX [148]SP   ; CLEAN EXIT LATER
1290 ;
1300 LDA #DISABLALL
1310 STA U1ICR    ;DISABLE [181]ERRUPTS
1320 ;
1330 LDA U1CRA    ;CLEAR BIT 6 OF CRA
1340 [175] #$FF[171]OUTPUT
1350 ;            ;SERIAL P[176]T [133] AT
1360 STA U1CRA    ; EXTERNAL CLOCK RATE
1370 ;
1380 MAINLOOP [178][172]
1390 JSR [161]SDP   ;[161] [131] BYTE ADDR
1400 STA PTR
1410 JSR [161]SDP
1420 STA PTR[170]1
1430 JSR [161]SDP   ;[161] [131] BYTE
1440 ;
1450 LDY #0
1460 STA (PTR),Y  ;S[164]RE [131] BYTE
1470 BEQ MAINLOOP ;LOOP [129]EVER
1480 ;
1481 ;
1490 EXIT [178][172]
1500 ; RE[171]ENABLE [181]ERRUPTS,
1510 ; [140] STACK [175] QUIT
1520 LDA #ENABLE[170]TIMERA
1530 STA U1ICR
1540 LDX [148]SP
1550 TXS
1560 RTS
1570 ;
1571 ;
1580 [161]SDP [178][172]
1590 ; [161] BYTE FROM SERIAL [131] PORT
1600 JSR UPDATE91 ;CHECK [144] KEY
1610 LDA [144]
1620 BPL EXIT
1630 ;
1640 LDA U1ICR    ;[146] [129] [133] BYTE
1650 [175] #SH[139]TREG
1660 BEQ [161]SDP   ;NO BYTE; LOOP AGAIN
1670 LDA U1[133]  ;[135] THE BYTE
1680 RTS
1690 ;
1700 [148]SP [172][178][172][170]1