[2] case=case $: $\n$ def=#define $\n$ default=default $: $\n$ dowhile=do\n{\n $\n}\nwhile ($);\n$ dowhiles=do\n $\nwhile ($);\n$ else=else\n{\n $\n}\n$ elseif=else if ($)\n{\n $\n}\n$ elseifs=else if ($)\n $\n$ elses=else\n $\n$ for=for ($;$;$)\n{\n $\n}\n$ fors=for ($;$;$)\n $\n$ func=$ $($)\n{\n $\n return $;\n}\n$ if=if ($)\n{\n $\n}\n$ ifelse=if ($)\n{\n $\n}\nelse\n{\n $\n}\n$ ifelses=if ($)\n{\n $\n}\nelse\n $\n$ ifs=if ($)\n $\n$ ifselse=if ($)\n $\nelse\n{\n $\n}\n$ ifselses=if ($)\n $\nelse\n $\n$ inc=#include <$>\n$ incl=#include "$"\n$ main=int main(int argc, char* argv[])\n{\n $\n}\n switch=switch ($)\n{\n $\n}\n$ while=while ($)\n{\n $\n}\n$ whiles=while ($)\n $\n$ [3] case=case $: $\n$ class=class $ {\nprivate:\n $\nprotected:\n $\npublic:\n $\n};\n$ def=#define $\n$ default=default $: $\n$ dowhile=do\n{\n $\n}\nwhile ($);\n$ dowhiles=do\n $\nwhile ($);\n$ else=else\n{\n $\n}\n$ elseif=else if ($)\n{\n $\n}\n$ elseifs=else if ($)\n $\n$ elses=else\n $\n$ for=for ($;$;$)\n{\n $\n}\n$ fors=for ($;$;$)\n $\n$ func=$ $($)\n{\n $\n return $;\n}\n$ hclass=#ifndef $\n#define $\n\nclass $ {\nprivate:\n $\nprotected:\n $\npublic:\n $\n};\n\n#endif\n$ if=if ($)\n{\n $\n}\n$ ifelse=if ($)\n{\n $\n}\nelse\n{\n $\n}\n$ ifelses=if ($)\n{\n $\n}\nelse\n $\n$ ifs=if ($)\n $\n$ ifselse=if ($)\n $\nelse\n{\n $\n}\n$ ifselses=if ($)\n $\nelse\n $\n$ inc=#include <$>\n$ incl=#include "$"\n$ main=int main(int argc, char* argv[])\n{\n $\n}\n switch=switch ($)\n{\n $\n}\n$ while=while ($)\n{\n $\n}\n$ whiles=while ($)\n $\n$ [8] b=$$ black=#000000 blue=#0000FF body=\n $\n\n$ comment=\n$ cyan=#00FFFF form=
\n $\n
\n$ green=#00FF00 grey=#C0C0C0 h1=

$

\n$ h2=

$

\n$ h3=

$

\n$ h4=

$

\n$ h5=
$
\n$ h6=
$
\n$ head=\n $\n\n$ html=\n \n $\n $\n \n \n $\n \n\n$ i=$$ img=$\n$ input=\n$ li=
  • $
  • \n$ link=$$ mangenta=#FF00FF ol=
      \n
    1. $
    2. \n $\n
    \n$ p=

    $

    \n$ pre=
    $
    \n$ red=#FF0000 span=$$ table=\n \n \n $\n \n $\n
    $
    \n$ td=$\n$ title=$\n$ tr=\n $\n\n$ ul=\n$ white=#FFFFFF yellow=#FFFF00 [29] else=} else {\n $ foreach=foreach $ $ {\n $\n}\n$ if=if { $ } {\n $\n}\n$ ifelse=if { $ }\n $\n} else {\n $\n} proc=# $\nproc $ { $ } {\n $\n}\n$ regsub=regsub -all {$} "$" {$} $\n$ [38] com=--\n-- $\n-- access=type $ is access $;\n$ alias=alias $ is $;\n$ archi=architecture $ of $ is\n$\nbegin\n$\nend $;\n$ array=type $ is\n array ( $ ) of $;\n$ assert=assert ( $ )\n report "$"\n sevrity $;\n$ block=$ : block $\nbegin\n $\nend block $;\n$ case=case $ is\n when $ =>\n $;\n when others =>\n $;\nend case;\n$ component=component $\n port (\n $\n );\nend component $;\n$ config=for $ : $\n use $\n $;\n$ constant=constant $: $;\n$ elsif=elsif ( $ ) then\n $; entity=entity $ is\n port (\n $\n );\nend $;\n$ enum=type $ is ( $, $ ); exit=exit $ when $;\n$ file=file $ : $ is $;\n$ for=$ : for $ in $ downto $ loop\n $;\nend loop $;\n$ function=function (\n $\n )return $ is\n $\nbegin\n $\nend $; functiond=function $ (\n $\n) return $;\n$ geneif=$ : if ( $ = $ ) generate\n $\nbegin\n $\nend generate $; generate=$ : for $ in $ downto $ generate\n $\nbegin\n $\nend generate $;\n$ generic=generic (\n $\n );\n$ genmap=generic map (\n $\n)\n$ group=group $ is ( $ );\n$ ieee=library ieee;\n use ieee.std_logic_1164.all;\n $ if=if ( $ ) then\n $;\n$end if;\n$ ifelse=if ( $ ) then\n $\nelse\n $\nend if;\n$ ifelsif=if ( $ ) then\n $\nelsif ( $ )\n $\nend if;\n$ loop=$ : loop\n $\nend loop;\n$ map=$ : $\n port map (\n $\n );\n$ mapgen=$ : $\n generic map (\n $\n )\n port map (\n $\n );\n$ next=$ : next $ when $;\n$ numeric=use ieee.numeric_std.all;\n$ pack=package $ is\n $\nend package $;\n\npackage body $ is\n $\nend package body $;\n$ port=port (\n $\n );\n$ procedure=procedure $ (\n $\n ) is\n$\nbegin\n $\nend procedure $;\n$ procedured=procedure $ (\n $\n);\n$ process=$ : process ( $ )\nbegin\n $\nend process $;\n$ proclk=$ : process ( $, $ )\n begin\n if ( $ = '$' ) then\n $ <= $;\n elsif( Rising_Edge( $ ) ) then\n $\n end if;\nend process $; protected=protected\n $\nend protected ; Ris=Rising_Edge ( $ )$ record=type $ is\n record\n $ : $ ;\nend record $;\n$ start=library ieee;\n use ieee.std_logic_1164.all;\n\nentity $ is\n port (\n $\n );\nend $;\n\narchitecture $ of $ is\n$\nbegin\n$\nend $;\n$ std=signal $ : std_logic$;\n$ stdpi=$ : in std_logic;\n$ stdpio=$ : inout std_logic;\n$ stdpo=$ : out std_logic;\n$ stdtextio=use ieee.std_logic_textio.all;\n$ stdv=signal $ : std_logic_vector( $ downto 0);\n$ stdvar=variable $ : std_logic;\n$ stdvpi=$ : in std_logic_vector( $ downto $);\n$ stdvpio=$ : inout std_logic_vector( $ downto $);\n$ stdvpo=$ : out std_logic_vector( $ downto $);\n$ stdvvar=variable $ : std_logic_vector( $ downto 0);\n$ subtype=subtype $ is $;\n$ textio=use std.textio.all;\n$ units=units\n $;\nend units;\n$ waitf=wait for $;\n$ waitu=wait until $;\n$ waituf=wait until $ for $;\n$ when=when $ =>\n $;$ whene=when ( $ ) else $; while=$ : while $ loop\n $;\nend loop;\n$ x=x"$"$