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Jumper Pins -01 -02 -03 -04 Function
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J100 4 2-3 2-3 1-2 1-2 Quadrature Clock Phasing
J101 3 2-3 2-3 2-3 2-3 FPU Clock Source
J102 3 2-3 2-3 2-3 2-3 System Clock Source
J103 4 3-4 3-4 3-4 3-4 FPU CS/BERR
J104 3 1-2 1-2 1-2 1-2 CPU Clock Source
J151 3 2-3 2-3 1-2 1-2 ROM Timing
J152 3 2-3 2-3 1-2 1-2 ROM Timing
J180 3 2-3 2-3 2-3 2-3 A2000 ROM Compatibility Jumpers
J181 3 2-3 2-3 2-3 2-3 A2000 ROM Compatibility Jumpers
J200 3 1-2 2-3 1-2 2-3 NTSC/PAL Select
J350 3 1-2 1-2 1-2 1-2 Tick Clock Source
J351 3 2-3 2-3 2-3 2-3 Disable DF1: (1-2 to enable)
J352 3 2-3 2-3 2-3 2-3 Light Pen Source
J481 3 2-3 2-3 2-3 2-3 VDE Scan Double Only Jumper
J482 3 1-2 1-2 1-2 1-2 VDE PLL Loop Adjust
J483 3 - - - - VDE Factory Test Points
J800 3 1-2 1-2 1-2 1-2 WD33C93
J851 3 1-2 1-2 2-3 2-3 RAM Controller Speed Jumper
J852 5 4-5 4-5 4-5 4-5 -012A Ramsey only (See Notes)
J853 3 2-3 2-3 2-3 2-3 -012A Ramsey only (See Notes)
J852 connecting pins 2 & 3 : 1Mbit, in 256k x 4
J852 connecting pins 1 & 2 : 4Mbit, in 1m x 4
Notes:
J150, J151: ROM Timing.
The ROM timing circuit provides four different speed settings to
match the output enable and access timing of the system ROMs.
To set the jumpers, determine the output enable time and access
times for the ROMs you wish to use. The ROM must have lower values
than for the setting you select.
System standard ROMs have T(oe) = 110ns and T(acc) = 250ns.
CLK J151 J150 T(oe)(min.) T(acc)(min.)
16 MHz 2-3 2-3 157ns 250ns
16 MHz 2-3 1-2 220ns 312ns
16 MHz 1-2 2-3 282ns 375ns
16 MHz 1-2 1-2 345ns 437ns
25 MHz 2-3 2-3 90ns 160ns
25 MHz 2-3 1-2 130ns 200ns
25 MHz 1-2 2-3 170ns 240ns
25 MHz 1-2 1-2 210ns 280ns
J180, J181: ROM Compatibility Jumpers
J180 J181
A2000/A500 ROMS: 1-2 1-2
A3000 ROMs: 2-3 2-3
J851-J853: RAM Controller Compatibility Settings
J852 J853
-012A Ramsey w/ 256K4 RAMs 4-5 2-3
Later Ramseys w/ 256K4 RAMs 2-3 1-2
Later Ramseys w/ 1M4 RAMs 1-2 1-2
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