{SYNCHRONOUS SERIAL INTERFACE} ({SSI})

    The synchronous serial interface ({SSI}) provides a full-duplex serial
port for serial communication with a variety of serial devices including 
one or more industry-standard codecs, other DSPs, microprocessors, and
peripherals which implement the Motorola SPI. The {SSI} consists of
independent transmitter and receiver sections and a common {SSI} clock
generator. Three to six pins are required for operation, depending on the
operating mode selected.

	The following is a short list of SSI features:

		A 6.75 Million Bit/Second at 27 Mhz serial interface

		Double Buffered

		User Programmable

		Separate Transmit and Receive Sections

		Control and Status Bits

		Interface to a Variety of Serial Devices, Including:
			Codecs (usually without additional logic)
				MC145500
				MC145501
				MC145502
				MC145503
				MC145402 (13-bit linear codec)
				MC145554 Family of Codecs
			Serial Peripherals (A/D, D/A)
				Most Industry-Standard A/D, D/A
				DSP56ADC16 (16-bit linear A/D)
			DSP56000 to DSP56000 Networks
			Motorola SPI Peripherals and Processors
			Shift Registers

		Interface to Time Division Multiplexed Networks without Additional
		Logic

		Six Pins:
			{STD} SSI Transmit Data
			{SRD} SSI Receive Data
			{SCK} SSI Serial Clock
			{SC0} Serial Control 0 (defined by SSI mode) 
			{SC1} Serial Control 1 (defined by SSI mode) 
			{SC2} Serial Control 2 (defined by SSI mode) 

		On-chip Programmable Functions Include:
			Clock - Continuous, Gated, Internal, External
			Synchronization Signals:
				- Bit Length
				- Word Length
			{TX}/{RX} Timing - Synchronous, Asynchronous
			Operating Modes - Normal, Network, On-Demand
			Word Length - 8, 12, 16, 24 Bits
			Serial Clock and Frame Sync Generator

		Four Interrupt Vectors:
			Receive
			Receive with Exception
			Transmit
			Transmit with Exception


	This interface is named synchronous because all serial transfers
are synchronized to a clock. Additional synchronization signals are used to
delineate the word frames. The normal mode of operation is used to transfer
data at a periodic rate, but only one word per period. The network mode is
similar in that it is also intended for periodic transfers; however, it will
support up to 32 words (time slots) per period. This mode can be used to
build time division multiplexed (TDM) networks. In contrast, the on-demand
mode is intended for nonperiodic transfers of data. This mode can be used to
transfer data serially at high speed when the data becomes available. This
mode offers a subset of the SPI protocol.

SSI DATA and Control Pins

	The SSI has three dedicated I/O pins, which are used for transmit data
({STD}), receive data ({SRD}), and serial clock ({SCK}), where {SCK} may be used
by both the transmitter and the receiver for synchronous data transfers or
by the transmitter only for asynchronous data transfers. Three other pins
may also be used, depending on the mode selected; they are serial control
pins {SC0}, {SC1}, and {SC2}. These serial control pins may be programmed as SSI
control pins in the port C control register.

{SSI} Interface Programming Model

    The {SSI} can be viewed as two control registers, one status register,
a transmit register, a receive register, and special-purpose time slot
register.The following paragraphs give detailed descriptions and operations
of each of the bits in the {SSI} registers.


{SSI CONTROL REGISTER A} ({CRA}):{ˆPM0}{ˆPM1}{ˆPM2}{ˆPM3}{ˆPM4}{ˆPM5}{ˆPM6}{ˆPM7}{ˆDC4}{ˆDC3}{ˆDC2}{ˆDC1}{ˆDC0}{ˆWL0}{ˆWL1}{ˆPSR}

   {CRA} is one of the two 16-bit read/write control registers used to direct
the operation of the {SSI}. The {CRA} controls the {SSI} clock generator bit
and frame sync rates, word length, and number of words per frame for the
serial data. The high-order bits of {CRA} are read as zeros by the DSP CPU.
The {CRA} control bits are described in the following paragraphs.

{Prescale Modulus Select} ({PM7}-{PM0}) {CRA} Bits 0-7:

   The {PM0}-{PM7} bits specify the divide ratio of the prescale divider in the
{SSI} clock generator. A divide ratio from 1 to 256 (PM = 0 to $FF) may be
selected. The bit clock output is available at the transmit clock (SCK)
and/or the receive clock (SC0) ins of the DSP. The bit clock output is also
available internally for use as the bit clock to shift the transmit and
receive shift registers. Careful choice of the crystal oscillator frequency
and the prescaler modulus will allow the industry-standard codec master
clock frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz to be generated.
Hardware and software reset clear {PM0}-{PM7}.

{Frame Rate Divider Control} ({DC4}-{DC0}) {CRA} Bits 8-12:

   The {DC4}-{DC0} bits control the divide ratio for the programable frame rate
dividers used to generate the frame clocks. In network mode, this ratio may
be interpreted as the number of words per frame minus one. In normal mode,
this ratio determines the word transfer rate. The divide ratio may range
from 1 to 32 (DC = 00000 to 11111) for normal mode and 2-32 (DC = 00001 to
11111) for network mode.

A divide ratio one (DC = 00000) in network mode is a special case. In normal
mode, a divide ratio of one (DC = 00000) provides continuous periodic data
word transfers. A bit-length sync ({FSL1} = 1, {FSL0} = 0) must be used in this
case. Hardware and software reset clear {DC4}-{DC0}.

{Word Length Control} ({WL0},{WL1}) {CRA} Bits 13 and 14:

   The {WL1} and {WL0} bits are used to select the length of the data words
being transferred via the {SSI}. Word lengths of 8, 12, 16, or 24 bits may
be selected according to the following assignements:

   +-----+-----+---------------------+
   | {WL1} | {WL0} | Number of Bits/Word |
   +-----+-----+---------------------+
   |   0 |   0 |            8        |
   +-----+-----+---------------------+
   |   0 |   1 |           12        |
   +-----+-----+---------------------+
   |   1 |   0 |           16        |
   +-----+-----+---------------------+
   |   1 |   1 |           24        |
   +-----+-----+---------------------+

These bits control the number of active clock transitions in the gated clock
modes and control the word length divider, which is part of the frame rate
signal generator for continuous clock modes. The WL control bits also
control the frame sync pulse length when {FSL0} and {FSL1} select a WL bit
clock. Hardware and software reset clear {WL0} and {WL1}.

{Prescaler Range} ({PSR}) {CRA} Bit 15:

   The {PSR} controls a fixed divide-by-eight prescaler in series with the
variable prescaler. This bit is used to extend the range of the prescaler
for those cases where a slower bit clock is desired. When {PSR} is cleared,
the fixed prescaler is bypassed. When {PSR} is set, the fixed divide-by-eight
prescaler is operational.

The maximum internally generated bit clock frequency is fosc/4, the minimum
internally generated bit clock frequency is fosc/4/8/256 = fosc/8192.
Hardware and software reset clear {PSR}.


{SSI CONTROL REGISTER B} ({CRB}):{ˆOF0}{ˆOF1}{ˆSCD0}{ˆSCD1}{ˆSCD2}{ˆSCKD}{ˆSHFD}{ˆFSL0}{ˆFSL1}{ˆSYN}{ˆGCK}{ˆMOD}{ˆTE}{ˆRE}{ˆTIE}{ˆRIE}

   The {CRB} is one of two 16-bit read/write control regioster used to direct
the operation of the {SSI}. Interrupt enable bits for each data
registerinterrupt are provided in this control register. When read by the
DSP, {CRB} appears on the two low-order bytes of the 24-bit word, and the
high-order byte reads as zeros. Operating modes are also selected in this
register. Hardware and software reset clear all the bits in the {CRB}. The
{SSI} {CRB} bits are described in the following paragraphs.

{Serial Output Flag 0} ({OF0}) {CRB} Bit 0:

   When the {SSI} is in the synchronous clock mode and the serial control
direction zero bit ({SCD0}) is set, indicating that the SC0 pin is an output,
then data present in {OF0} will be written to SC0 at the beginning of the
frame in normal mode or at the beginning of the next time slot in network
mode. Hardware and software reset clear {OF0}.

{Serial Output Flag 1} ({OF1}) {CRB} Bit 1:

   When the {SSI} is in the synchronous clock mode and the serial control
direction one ({SCD1}) bit is set, indicating that the SC1 pin is an output,
then data present in {OF1} will bewritten to the SC1 pin at the beginning of
the frame in normal mode or at the beginning of the next time slot in
network mode.

The normal sequence for setting output flags when transmitting data is to
set {TDE} ({TX} empty), to first write the flags, and then write the transmit
data to the {TX} register. {OF0} and {OF1} are double buffered so that the flag
states appear on the pins when the {TX} data is transfered to the transmit
shift register (i.e., the flags are synchronouswith the data). Hardware and
software reset clear {OF1}.

{Serial Control 0 Direction} ({SCD0}) {CRB} Bit 2:

   {SCD0} controls the direction of the SC0 I/O line. When {SCD0} is cleared,
SC0 is an input; when {SCD0} is set, SC0 is an output. Hardware and software
reset clear {SCD0}.

{Serial Control 1 Direction} ({SCD1}) {CRB} Bit 3:

   {SCD1} controls the direction of the SC1 I/O line. When {SCD1} is cleared,
SC1 is an input; when {SCD1} is set, SC1 is an output. Hardware and software
reset clear {SCD1}.

{Serial Control 2 Direction} ({SCD2}) {CRB} Bit 4:

   {SCD2} controls the direction of the SC2 I/O line. When {SCD2} is cleared,
SC2 is an input; when {SCD2} is set, SC2 is an output. Hardware and software
reset clear {SCD2}.

{Clock Source Direction} ({SCKD}) {CRB} Bit 5:

   {SCKD} selects the source of the clock signal used to clock the transmit
shift register in the asynchronous mode and both the transmit shift register
and the receive shift register in the synchronous mode. When {SCKD} is set,
the internal clock source becomes the bit clock for the transmit shift
register and word length divider and is the output on the SCK pin. When {SCKD}
is cleared, the clock source is external; the internal clock generator is
disconnected from the SCK pin, and an external clock source may drive this
pin. Hardware and software reset clear {SCKD}.

{Shift Direction} ({SHFD}) {CRB} Bit 6:

   This bitcauses the transmit shift register to shift data out MSB first
when {SHFD} equals zero or LSB first when {SHFD} equals one. Receive data is
shifted in MSB first when {SHFD} equals zero or LSB first when {SHFD} equals
one. Hardware reset and software reset clear {SHFD}.

{Frame Sync Length} ({FSL0} and {FSL1}) {CRB} Bits 7 and 8:

    These bits select the type of frame sync to be generated or recognized.
If {FSL1} equals zero and {FSL0} equals zero, a word-length frame sync is
selected for both {TX} and {RX} that is the length of the data word defined by
bits {WL1} and {WL0}. If {FSL1} equals one and {FSL0} equals zero, a 1-bit clock
period frame syncis selected for both {TX} and {RX}. When {FSL0} equals one, the
{TX} and {RX} frame syncs are different lengths. Hardware reset and software
reset clear {FSL0} and {FSL1}.

   +------+------+----------------------------------------------+
   | {FSL1} | {FSL0} |        Frame Sync Length                     |
   +------+------+----------------------------------------------+
   |  0   |  0   | WL bit clock for both {TX}/{RX}                  |
   +------+------+----------------------------------------------+
   |  0   |  1   | One-bit clock for {TX} and WL bit clock for {RX} |
   +------+------+----------------------------------------------+
   |  1   |  0   | One-bit clock for both {TX}/{RX}                 |
   +------+------+----------------------------------------------+
   |  1   |  1   | One-bit clock for {RX} and WL bit clock for {TX} |
   +------+------+----------------------------------------------+

{Sync/Async} ({SYN}) {CRB} Bit 9:

   {SYN} controls whether the receive and transmit functions of the {SSI}
occur synchronously with respect to each other. When {SYN} is cleared,
asynchronous mode is chosen and separate clock and frame sync signals are
used for the transmit and receive sections. When {SYN} is set, synchronous
mode is chosen and the transmit and receive sections use common clock and
frame sync signals. Hardware reset and software reset clear {SYN}.

{Gated Clock Control} ({GCK}) {CRB} Bit 10:

   {GCK} is used to select between a continuously running data clock or a
clock that runs only when there is data to be sent in the transmit shift
register. When {GCK} is cleared, a continuous clock is selected; when {GCK} is
set, the clock will be gated. Hardware reset and software reset clear {GCK}.

NOTE:   For gated clock mode with externally generated bit clock, internally
generated frame sync is not defined.

{SSI Mode Select} ({MOD}) {CRB} Bit 11:

   {MOD} selects the operational mode of the {SSI}. When {MOD} is cleared, the
normal mode is selected; when {MOD} is set, the network mode is selected. In
the normal mode, the frame rate divider determines the word transfer rate --
one word is transferred per frame sync during the frame sync time slot. In
network mode, a word is (possibly) transferred every time slot. Hardware and
software reset clear {MOD}.

{SSI Transmit Enable} ({TE}) {CRB} Bit 12:

   {TE} enables the transfer of data from {TX} to the transmit shift register.
When {TE} is set and a frame sync is detected, the transmit portion of the
{SSI} is enabled for that frame. When {TE} is cleared, the transmitter wille
be disabled after completing transmission of data currently in the {SSI}
transmit shift register. Theserial output is three-stated, and any data
present in {TX} will not be transmitted (i.e., data can be written to {TX} with
{TE} cleared; {TDE} will be cleared, but data will not be transferred to the
transmit shift register).

The normal mode transmit enable sequence is to write data to {TX} or {TSR} befor
setting {TE}. The normal transmit disable sequence is to clear {TE} and {TIE}
after {TDE} equals one.

In the network mode, the operation of clearing {TE} and setting it again will
disable the transmitter after completing transmission of the current data
word until the beginning of the next frame. During that time period, the STD
pin will remain in the high-impedance state. Hardware reset and software
reset clear {TE}.

The on-demand mode transmit enable sequence can be the same as the normal
mode, or {TE} can be left enabled.

NOTE:   {TE} does not inhibit {TDE} or transmitter interrupts. {TE} does not
affect the generation of frame sync or output flags.

{SSI Receive Enable} ({RE}) {CRB} Bit 13:

   When {RE} is set, the receive portion of the {SSI} is enable. When thisbit
is cleared, the receiver will be disabled by inhibiting data transfer into
{RX}. If data is being received while this bit is cleared, the remainder of
the word will be shifted in and transfered to the {SSI} receive data
register.

{RE} must be set in the normal mode and on-demand mode to receive data. In
network mode, the operation of clearing {RE} and setting it again will disable
the receiver after reception of the current data word until the beginning of
the next data frame. Hardware and software reset clear {RE}.

NOTE:   {RE} does not inhibit {RDF} or receiver interrupts. {RE} does not affect
the generation ofa frame sync.

{SSI Transmit Interrupt Enable} ({TIE}) {CRB} Bit 14:

   The DSP will be interrupted when {TIE} and the {TDE} flag in the {SSI}
status register is set. When {TIE} is cleared, this interrupt is disabled.
However, the {TDE} bit will always indicate the transmit data register empty
condition even when the transmitter is disabled with the {TE} bit. Writing
data to {TX} or {TSR} will clear {TDE}, thus clearing the interupt. Hardware and
software reset clear {RE}.

There are two transmit data interrupts that have separate interrupt vectors:

   1. Transmit data with exceptions -- This interrupt is generated on the
following condition:
    {TIE}=1, {TDE}=1, and {TUE}=1

   2. Transmit data without exceptions -- This interrupt is generated on the
following condition:
    {TIE}=1, {TDE}=1, and {TUE}=0

{SSI Receive Interrupt Enable} ({RIE}) {CRB} Bit 15:

   When {RIE} is set, the DSP wil be interrupted when {RDF} in the {SSI} status
register is set. When {RIE} is cleared, this interrupt is disabled. However,
the {RDF} bit still indicates the receive data register full condition.
Reading the receive data register will clear {RDF}, thus clearing the pending
interrupt. Hardware reset and software reset clear {RIE}.

There are two receive data interrupts that have separate interrupt vectors:

   1. Receive data with exceptions -- This interrupt is generated on the
following condition:
    {RIE}=1, {RDF}=1, and {ROE}=1

   2. Receive data without exceptions -- This interrupt is generated on the
folowing condition:
    {RIE}=1, {RDF}=1, and {ROE}=0


{SSI STATUS REGISTER} ({SSISR}):{ˆIF0}{ˆIF1}{ˆTFS}{ˆRFS}{ˆTUE}{ˆROE}{ˆTDE}{ˆRDF}

    The {SSISR} is an 8-bit read-only status register used by  the DSP to
interrogate the status and serial input flags of the {SSI}. When the {SSISR}
is reda to the internal data bus, the register contents occupy the low-order
byte of the data bu, and the high-order portion is zero filled. The status
bits are described in the following paragraphs.

{Serial Input Flag 0} ({IF0}) {SSISR} Bit 0:

    The {SSI} latches data present on the SC0 pin during reception of the
first received bit after frame sync is detected. {IF0} is updated with this
data when the receive shift register is transfered into the receive data
register. The {IF0} bit is enabled only when {SCD0} is cleared and {SYN} is set,
indicating that SC0 is an input and the synchronous mode is selected;
otherwise, {IF0} reads as a zero whenit is not enabled. Hardware, software,
{SSI} individual, an STOP reset clear {IF0}.

{Serial Input Flag 1} ({IF1}) {SSISR} Bit 1:

   The {SSI} latches data present on the SC1 pin during reception of the
first received bit after frame sync is detected. The {IF1} flag is updated
with the data when the receiver shift register is transfered into the
receive data register. The {IF1} bit is enable only when {SCD1} is cleared and
{SYN} is set, indicating that SC1 is an input and the synchronous mode is
selected; otherwise, {IF1} reads as zero when it is not enabled. Hardware,
software, {SSI} individual, and {STOP} reset clear {IF1}.

{Transmit Frame Sync Flag} ({TFS}) {SSISR} Bit 2:

   When set, {TFS} indicates that a transmit frame sync occured in the current
time slot. {TFS} is set at the start of the first time slot in the frame and
cleared during all other time slots. Data written to the transmit data
register during the time slot when {TFS} is set will be transmitted (in
network mode) during the second time slot in the frame. {TFS} is useful in
network mode to identify the start of a frame.

NOTE:   In normal mode, {TFS} will always read as a one when transmitting data
because there is only one time slot per frame -- the "frame sync" time slot.

{Receive Frame Sync Flag} ({RFS}) {SSISR} Bit 3:

   When set, {RFS} indicates that a receive frame sync occurred during
reception of the word in the serial receive data register. This indicates
that the data word is from the first time slot in the frame. When {RFS} is
clear and a word is received, it indicates (only in the network mode) that
the frame sync did not occur during reception of that word.

NOTE:   In normal mode, {RFS} will always read as a onewhen reading data
because there is only one time slot per frame -- the "frame sync" time slot.

{RFS}, which is cleared by hardware, software, {SSI} individual, or {STOP}
reset, isnot affected by {RE}.

{Transmitter Underrun Error Flag} ({TUE}) {SSISR} Bit 4:

   {TUE} is set when serial transmit shift register is empty (no new data to
be transmitted) and a transmit time slot occurs. When a transmit underrun
error occurs, the previous data (which is still present in the {TX}) will be
retransmitted.

In the normal mode, there is only one transmit time slot per frame. In the
network mode, there can be up to 32 transmit time slots per frame.

{TUE} does not cause any interrupts; however, {TUE} does cause a change in the
interrupt vector used for transmit interrupts so that a different interrupt
handler may be used for a transmit underrun condition. If a transmit
interrupt occurs with {TUE} clear, the transmit data without errors interrupt
will be generated.

Hardware, softwre, {SSI} individual, and {STOP} reset clear {TUE}. {TUE} is
also cleared by reading the {SSISR} with {TUE} set, followed by writing {TX} or
{TSR}.

{Receive Overrun Error Flag} ({ROE}) {SSISR} Bit 5:

   This flag is set when the serial receive shift register is filled and
ready to transfer to the receiver data register ({RX}) and {RX} is already full
(i.e., {RDF}=1). The receiver shift register is not transfered to {RX}. {ROE} does
not cause any interrupts; however, {ROE} does cause a change in the interrupt
vector used for receive interrupts so that adifferent interrupt handler may
be used for a receive error condition. If a receive interrupt occurs with
{ROE} set, the receive data with exception status interrupt will be generated;
if a receive interrupt occurs with {ROE} clear, the receive data without
errors interrupt will be generated.

Hardware, software, {SSI} individual, and {STOP} reset clear {ROE}. {ROE} is
also cleared by reading the {SSISR} with {ROE} set, followed by reading the {RX}.
Clearing {RE} does not affect {ROE}.

{SSI Transmit Data Register Empty} ({TDE}) {SSISR} Bit 6:

    This flag is set when the contents of the transmit data register are
transferred to the transmit shift register; it is also set for a disabled
time slot period in network mode (as if data were being transmitted after
the {TSR} was written). Thirdly, it can be set by the hardware, software,
{SSI} individual, or {STOP} reset. When set, {TDE} indicates that data
should be written to the {TX} or to the time slot register ({TSR}). {TDE} is
cleared when the DSP writes to the transmit data register or when the DSP
writes to the {TSR} to disable transmission of the next time slot. If {TIE} is
set, a DSP transmit data interrupt request will be issued when {TDE} is set.
The vector of the interrupt will depend on the state of the transmitter
underrun bit.

{SSI Receive Data Register Full} ({RDF}) {SSISR} Bit 7:

   {RDF} is set when the contents of the receive shift register are
transferred to the receive data register. {RDF} is cleared when the DSP reads
the receive data register or cleared by hardware, software, {SSI}
individual, or {STOP} reset. If {RIE} is set, a DSP receive data interrupt
request will be issued when {RDF} is set. The vector of the interrupt request
will depend on the state of the receive overrun.


{SSI Receive Shift Register}:

   This 24-bit shift register receives the incoming data from the serial
receive data pin. Data is shifted in by the selected (internal/external) bit
clock when the associated frame sync I/O (or gated lock) is asserted. Data
is assumed to be received MSB first if {SHFD} equals zero and LSB first if
{SHFD} equals one. Data is transferred to the {SSI} receive data register
after 8,12,16, or 24 bits have been shifted in, depending on the word-length
control bits in the {CRA}.


{SSI Receive Data Register} ({RX}):

   {RX} is a 24-bit read_only register that accepts data from the receive
shift register as it becomes full. The data read will occupy the most
significant portion of the receive data register. The unused bits (least
significant portion) will read as zeros. The DSP is interrupted whenever {RX}
becomes full if the associated interrupt is enabled.


{SSI Transmit Shift Register}:

   This 24-bit shift register contains the data being transmitted. Data is
shifted out to the serial transmit data pin by the selected
(internal/external) bit clock when the associated frame sync I/O (or gated
clock) is asserted. The number of bits shifted out before the shift register
is considered empty and may be written to again can be 8,12,16, or 24 bits
(determined by the word-length control bits in {CRA}). The data to be
transmitted occupies the most significant portion of the shift register. The
unused portion of the register is ignored. Data is shifted out of this
register MSB first if {SHFD} equals zero and LSB first if {SHFD} equals one.


{SSI Transmit Data Register} ({TX}):

   {TX} is a 24-bit write-only register. Data to be transmitted is written
into this register and is automatically transferred to the transmit shift
register. The data written (8,12,16, or 24 bits) should occupy the most
significant portion of {TX}. The unused bits (least significant portion) of {TX}
are don't care bits. The DSP is interrupted whenever {TX} becomes empty if the
transmit data register empty interrupt has been enabled.


{SSI Time Slot Register} ({TSR}):

   {TSR} is effectively a null data register that is used when the data is not
to be transmitted in the available transmit time slot. For the purposes of
timing, {TSR} is a write-only register that behaves like an alternative
transmit data register, except that, rather than transmitting data, the
transmit data pin is in the high-impedence state for time slot.


